Integrated, Low Voltage, Dynamically Adaptive Buck-Boost Boost Converter A Top-Down Design Approach

Transcription

1 Integrated, Low Voltage, Dynamically Adaptive Buck-Boost Boost Converter A Top-Down Design Approach Georgia Tech Analog Consortium Biranchinath Sahu Advisor: Prof. Gabriel A. Rincón-Mora Analog Integrated Circuits Laboratory School of Electrical and Computer Engineering Georgia Institute of Technology

2 Abstract 2 Power-aware, portable, electronic systems incorporate algorithms for dynamically changing the supply voltage depending on workload/throughput to extend battery life. Single inductor, non-inverting buck-boost converters are best-suited to generate a voltage that is higher and lower than the battery supply, with minimum number of external components. Dynamically-Adaptive Buck-Boost Converters High efficiency Improvement in battery life Low voltage Single cell operation (Li-ion/NiCd/NiMH/Fuel Cell) Integrated External components, Cost Low noise Interference This work addresses the design challenges and trade-offs involved in realizing an integrated circuit (IC) for such a system with a wide range of supply voltage. Lower limit Minimum supply voltage for circuits to be operational (1.4 V) Higher limit Process technology constraints (5 V)

3 3 Understanding the Load Battery Supply 3.5 Control Signal Non-inverting Buck-Boost DC- DC Converter Output ( V) Probability (%) Urban Suburban RF input Power Amplifier The System RF Output Load Output power (dbm) Loading Profile The output power of the power amplifier varies over a wide range Output voltage range of the buck-boost converter For WCDMA architecture, the power transmitted can increase or decrease by 1-dB is every 666 µsec Transient requirements The RF power amplifier must meet its adjacent channel leakage ratio (ACLR) and error vector magnitude (EVM) specifications Output voltage accuracy (DC, AC, Transient) requirements

4 Requirements of the Converter 4 Under light-load conditions, the converter can operated in buck-mode with a lower switching frequency, thereby reducing switching losses and consequently improving system efficiency. Converter output voltage Can be operated with low frequency, no need to meet any transient requirements 0.5 V Converter needs to satisfy transient requirements 5 V Boost Buck-boost Buck Control signal - 50 dbm 10 dbm PA Output power 27 dbm 1 db Tpower_change Tresponse Typical transient response Output voltage Linearity degradation Time Specifications Value Input voltage (VIN) V Output voltage (VOUT) V Load current [ILOAD = f (VOUT)] A Output voltage accuracy [f (VOUT)] 95 % Load resistance Ohms Switching frequency 1 MHz ± 20% Closed-loop bandwidth 50 khz 1-dB step change response time 20 µsec Full-load efficiency 90 %

5 Converter Block Diagram 5 Vin MP1 Vph1 Vph2 MN3 L D2 Vout MN1 D1 MN2 MP2 RESR ILOAD Salient Features C Voltage mode control Type III compensation Drive and dead-time control Drive and dead-time control Duty cycle limit COMPBOOST Error amplifier Level shifting circuit Start-up and control signal by-pass circuit 1 MHz switching frequency 0.8 µh power inductor 10 µf output capacitor with 10 mω ESR Feedback control COMPBUCK Vcontrol Triangular wave generator Buck/Buck-Boost/Boost Mode 1 of operation for improved efficiency Low power, sleep mode of operation for optimal efficiency 1 FA7618 controller as presented in US Patent No. 5,402,060 (1995) and LTC 3440 application notes (2003).

6 Dynamic Sizing of Power MOSFETS 6 Common Drain Node 1.4E+06 Vsupply 1.2E+06 I PMOS NMOS 0.5 pf 3.5 pf 0.35 V W/L Ratio 1.0E E E E+05 II III IV 0.25 V 2.0E V UVLO Signal Gate Drive Signal 0.0E Battery Voltage (V) V Battery State Monitoring Block Power MOSFET sizing strategy Aspect ratio for same switch ON-resistance with variation in supply voltage Dynamic sizing of Power MOSFETs allow minimization of conduction and switching losses for optimal efficiency at a given supply voltage. Conduction loss Switch resistance 1/W Switching loss Switch capacitance W

7 Gate Drive Circuits 7 VGATE_MN3 VIN MN3 VIN_MAX Vph1 L Vph2 D2 V out 1 VOUT < VIN - VTN 2 VOUT = VIN - VTN 1 MP2 OFF 2 MN2 OFF MP2 RESR IO VOUT > VIN - VTN VGATE_MP2 C VIN_MIN Output Switch V OUT_MIN VTP VOUT Except the Boost PMOS switch, all the other switches can be driven by a chain of inverters. For the output switch, transmission gate is used to reduce the voltage range for which body diode conducts. The PMOS gate driver is powered from the output of the converter to ensure its operation. PWM Signal Transmission gate operation Level Shift Circuit PMOS Drive Circuit NMOS Drive Circuit VOUT VGATE_MP2 VBAT VGATE_MN3 Level shifting circuit for PMOS Boost Drive

8 Designing the Error Amplifier 8 Requirements of the Op-amp Input common-mode range (ICMR) With V TP +V TN > V DD, the ICMR of NMOS and PMOS exist only close to supply and ground rail, respectively. By dynamically shifting the input signal as a function of supply voltage the input signal a PMOS input stage can be used. ICMR, Noise, Offset voltage Input Offset Voltage Error in output voltage = Offset voltage Closed loop gain of the converter. Depending on the accuracy requirement, offset cancellation techniques can be used. DC Gain and Bandwidth As DC gain, steady-state error UGF OPAMP >> Loop BW CONVERTER VCM_ref V IN+ Aaux I X IX I X I X V DD V IN A main Low voltage, large ICMR op-amp Minimum supply voltage = V T + 3 V ON sets lower limit of operation for the integrated converter V out

9 9 Reducing Noise Spread Spectrum Switching VDD = V MP3 MN3 MP2 MP1 MN1 MN2 COMP1 COMP2 S Q R Q MP4 MN4 The frequency of the triangular waveform generator is changed in a pseudo-random manner by varying the charging and discharging current of the capacitor. Programmable Current Source Triangular Wave Generator PSIN RFIN Circuit/System RFOUT By incorporating spread-spectrum switching, the ripple noise voltage is distributed over a wider frequency band resulting in a lower side-lobe power with respect to the signal power. Improved signal-to-noise ratio (a) (b) PSIN RFIN RFOUT (b) Reduced Out-of-band distortion using switching (a) Without spread-spectrum, (b) With spread-spectrum (a)

10 Simulation Results 10 V IN = 2 V Control signal Boost Boost Buck Buck/Boost Output voltage Inductor current Transient Response (V IN = 2V) V IN = 4.2 V Control signal Boost Buck Buck Buck Output voltage Inductor current

11 Summary 11 A top-down approach for integrated circuit design of key building blocks in a non-inverting buck-boost converter is discussed considering the challenges involved in realizing low voltage circuits. Performance Enhancements Efficiency Improvement Buck/Buck-Boost/Boost Mode of operation Dynamic sizing of power MOSFET switches Decreasing/Increasing the switching frequency to minimize losses depending on the battery voltage Accuracy DC accuracy Low offset, wide input common-mode range op-amp for error amplifier Ripple voltage/noise spectrum Spread-spectrum clocking Transient accuracy Higher bandwidth, slew rate Future Work: Layout and performance evaluation of the IC