A Dynamically Adaptive, Power Management IC for WCDMA RF Power Amplifiers in Standard CMOS Process. Georgia Tech Analog Consortium.

Transcription

1 A Dynamically Adaptive, Power Management IC for WCDMA RF Power Amplifiers in Standard CMOS Process Georgia Tech Analog Consortium Biranchinath Sahu Advisor: Prof. Gabriel A. Rincón-Mora oratory School of Electrical and Computer Engineering Georgia Institute of Technology Abstract 2 Energy-efficient, linear RF power amplifiers are critical and paramount to achieve longer battery life in state-of-the-art wireless handsets. In the proposed system, the energy-efficiency of a WCDMA RF PA is improved by dynamically adjusting the supply and current as a function of its transmitted power. Key Features of the Power Management IC Low Single cell operation (Li-ion/NiCd/NiMH) Integrated Except filter inductor, capacitor and compensation High efficiency Buck, Buck-boost, and Boost mode operation Low quiescent power PFM Mode at light load for better standby performance Integrated dynamic gate(base) bias circuit 1.96 GHz, 3.84 MHz HK Modulation WCDMA RF PA 25 dbm maximum output power Less than 35 dbc/-58 dbc adjacent/alternate channel leakage ratio (ACLR) Less than 10 % rms error vector magnitude (EVM) More than seven times average efficiency improvement over fixed-supply class- AB PA

2 High Efficiency WCDMA RF PA V Battery I C I B increasing V DS,sat 3.6 V 1.5 V 3/5 V I C_MAX Display Audio Interface 2.5/5 V DSP DAC PA core Baseband LO digital I/O ADC LNA Analog/RF 2.5 V 2.5 V Reduce the input power drawn from the battery as transmitter output power decreases Gain variation requires calibration with the rest of the transmitter chain Control Signal I CQ_A I CQ_AB I CQ_C V IN = V RF input DC-DC Converter and Dynamic Bias Circuit Power Amplifier The System V SUPPLY Q A RF Output V CE Output ( V) Load Block Diagram of the Chip 4 MNBUCK MPBUCK P GND Integrated Power FETS MPBOOST MNBOOST Boost DTC Buck DTC PA Bias Circuit PWM Bias Bandgap Reference PFM Controller Triangular Wave Error Amplifier Buffer AVDD A GND PFMRES ITW VSFT VEAO VFB VBUF Dual-mode, noninverting buckboost converter for high efficiency over wide loading conditions Voltage-mode PWM controller at high PA output power PFM controller at light loading conditions Integrated bandgap reference Integrated power amplifier dynamic bias circuit MODE ENBL PABIAS I PARES BIAS VREF IREF VCON

3 Die Plot and Pin Diagram 5 NMOS BUCK PMOS BUCK BUNMOS BUPMOS AVDD PMOS BOOST NMOS-2 BOOST PWM Comparators PFM Controller Triangular Wave BOPMOS Radio Frequency Power Amplifier Power Management Integrated Circuit AGND PFMRES VSFT VFB 1 52 VCON BONMOS CHIPEN TWEN LCC 52 MODE PARES PABIAS VREF IBIAS3 IBIAS2 IBIAS SSPIN BUFOUT BUFIN VEAO IBTWG NMOS BOOST Bias PA Dynamic Bias Error Amplifier Buffer Bandgap Reference Only external components Power Inductor, output capacitor Frequency compensation network Input bulk capacitor Buck-Boost Boost Converter PWM Mode 6 Vin Intermediate buck-boost mode operation MP1 Vph1 Vph2 MN3 L D2 Vout MP2 MN1 D1 MN2 RESR ILOAD C Drive and dead-time control Feedback control Drive and dead-time control Duty cycle limit COMPBUCK COMPBOOST Error amplifier Level shifting circuit Start-up and control signal by-pass circuit Vcontrol Inductor current Control-step transient response Triangular wave generator Key features of the converter in PWM Mode Input supply range of V Output V with maximum load of 0.3 A Peak efficiency of 90 % Worst-case peak-to-peak ripple of 90 mv Output Control signal

4 Buck-Boost Boost Converter PFM Mode 7 M1 Vph1 L T PMOS 2C V V V IN ( V V ) IN OUT L OUT PMOS gate PFM mode functionality -1 D2 RESR ILOAD R1 NMOS gate C R2 Gate Drive Qb S VFB Inductor current R Gate Drive Delay Delay COMP1 VCON PFM mode functionality -2 Q S COMP2 Vph1 PMOS gate R PFM Controller NMOS gate Key features of the converter in PFM Mode Adaptive on-time keeps peak-to-peak ripple less than 25 mv over V supply Efficiency of 80 % at light load: 0.5 V with 50 ma load Output ripple PA System Experimental Results 8 V CON V IN PA Output spectrum at peak power HBT 2 Dynamic Bias IC V IN HBT 3 Buck-Boost Converter IC HBT 1 RF OUT Collector current in the PA stage is adjusted by varying R BIAS HBT 1 and HBT 2 can be easily implemented in an IC as current mirror R BIAS Adjacent Channel Leakage Ratio [dbc] Fixed Supply Dynamic Supply RF IN PA System Implementation -70 Adjacent Channel Leakage Ratio RF PA Module Peak output power of 25 dbm Class-AB operation at high output power ACLR 1 < -35 dbc throughout the output power range ACLR 2 < -58 dbc Degradation at lower power due to noise floor of the spectrum analyzer -70 Alternate Channel Leakage Ratio Alternate Channel Leakage Ratio [dbc] Fixed Supply Dynamic Supply

5 PA System Experimental Results 9 Error vector magnitude less than 10 % throughout the output power range EVM degradation with dynamic supply and bias current is due to output ripple of the power supply Gain [db] Gain of the PA Dynamic supply 2 Fixed supply Overall Error Vector Magnitude [% rms] Error Vector Magnitude Dynamic supply Fixed supply Gain variation from 4-dB to 10-dB with bias current adjustment Open-loop look-up table based calibration with automatic gain control circuit to achieve the transmitter s output power dynamic range Alternate: finite step control instead of continuous control PA Supply Voltage / Converter s Output Voltage [V] Discrete and Continuous Control Schemes VMAX 2-step control VMIN 3-step control PTH PMAX Accurate cont. control Approx. cont. control Battery Life Improvement 10 Input Supply Power [W] Battery Life [Hours] E E E E E E E+00 Battery life is dependant on the average efficiency over the period for which the PA is operational and standby power consumption of the system when the PA is in sleep mode. Activity Cycle = Active Mode / (Active Mode + Standby Mode) Dynamic-supply: PWM+PFM Dynamic-supply: PWM Fixed-supply PWM+PFM PWM Fixed Supply Activity Cycle If the PA remains operational all the time, there is no advantage of using dual-mode control However, most portable applications remain in standby mode, and therefore lower quiescent current is desirable along with high efficiency over loading range Efficiency in continuous 1- db control in almost twice compared to 3-step control Trade-off: complexity of calibration circuit and efficiency improvement 1.2E E E E E E E+00 Input Supply Power [W] Battery Life [Hours] Continuous 3-step 2-step Activity Cycle Continuous Three step Tw o step

6 Summary 11 This work experimentally demonstrates the feasibility and potential battery life improvement in PA driven application using a powertracking dynamically-adaptive supply and bias current control scheme Nominal and current at peak PA output power Reduced supply and current as PA output power decreases Power change (1dB in 666 µsec) is slower than envelope (3.84 MHz) Low bandwidth power supply High efficiency High efficiency buck-boost power supply IC with Dual-Mode operation (PWM+PFM) Minimum input supply of 1.4 with nominal V TP = 0.95 V, V TN = 0.75 V Adaptive on-time control for accurate peak-to-peak ripple critical for PA Conclusion: Design, Implementation, and experimental validation of a novel, integrated buck-boost supply and dynamic biasing circuit for high efficiency, WCDMA RF PAs in a standard CMOS process