26.8: A 1.9GHz Single-Chip CMOS PHS Cellphone

Transcription

1 26.8: A 1.9GHz Single-Chip CMOS PHS Cellphone William W. Si, Srenik Mehta, Hirad Samavati, Manolis Terrovitis, Michael Mack, KeithOnodera, SteveJen, Susan Luschas, Justin Hwang, SuniMendis, DavidSu, BruceWooley 1 Atheros Communications, Santa Clara, California 1 Stanford University, Stanford, California

2 Outline Introduction Overall Architecture RF Transceiver Synthesizer Receiver Transmitter Calibration Measurement Results

3 Integrated PHS SoC Solution Personal Handy-Phone System (PHS) Commercially launched in 1995 Resurgence in China (> 50M subscribers in 2004) Single-Chip PHS Solution in 0.18mm CMOS RF/Analog: RF transceiver, audio/voiceband data converters and audio amplifiers Digital: PHS MODEM, TDMA, CPU, Voice subsystem, Interfaces PHS System TDMA/TDD - Time Domain Multiple Access / Duplexing p/4 QPSK modulation with 192kHz channel bandwidth 1.9GHz frequency band, 300kHz channel spacing Support seamless handover fi fast channel switching

4 Advantages of System-on-Chip SoC Low cost, small form factor with fewer external components Digital calibration Wide digital-analog interface without package pins and associated power for I/Os Digital calibration to repair analog impairments, eases requirements of analog RF circuits

5 Block Diagram of Single-Chip PHS Cellphone SRAM Power Mgmt PHS TDMA PHS MODEM PHS RF Transceiver Flash LCD Display LED Keypad WLAN Interfaces CPU Voice Subsystem Audio Amplifiers Data- Converters Microphone Earpiece Speaker

6 RF Transceiver Block Diagram Transmitter XPA PA I Q LO LO RF Loop back I Q Receiver DAC DAC 2 2 ADC ADC ChannelFrequency Sigma Delta 3.8GHz Fractional-N Synthesizer f vco = 2 xf rf weaker PA pulling smaller inductor easy quad. LO gen

7 Sigma-Delta Fractional-N Synthesizer 38.4MHzcrystal / TCXO Phase Detector Charge Pump Loop Filter VCO 2 f RF 3.8GHz Retiming P/S Counter 3 SD Modulator ChannelFrequency 8/9 Prescaler Total current = 25mA

8 Voltage Controlled Oscillator Regulated V DD (1.8V) 7-bit control C Metal C Metal V c

9 Fast Synthesizer Settling (I) Seamless handover support fi requires fast channel switching Talking Scan other cell station channels... time slot 1 time slot 2 time slot 3 Ch. 1 Ch. 2 Ch. 3 Time for synthesizer settling Traditional approach: Use two interleaving synthesizers fi power and area penalty Synth 1 Synth 2 LO output Synth 1 Synth 2 Synth 1 slot 1 slot 2 slot 3 Ch. 1 Ch. 2 Ch We use only one synthesizer with fast settling

10 Fast Synthesizer Settling (II) Tradeoff between settling time and phase noise: Loop bandwidth optimization Wide loop BW for fast settling Low loop BW to suppress SD quantization noise Optimized loop BW = 120kHz Avoid over-design fi Minimizing loop BW variation BW = (K vco I cp R s ) / (2pN) V ctrl within 200mV fi K vco is roughly constant I cp tracks process variation of R s fi I cp R s constant Loop BW dynamically adjusted during switching to speed up frequency transient response Resulting settling time = 15ms

11 Direct Conversion Receiver LO RF (I) 2 LO RF 2 LO RF (Q) RF in Envelope Detection for AGC I DAC ADC IOffset Control 1 LNA RFVGA1 RFVGA2 Q ADC 1 RF loopback from TX Total current = 32mA DAC QOffset Control

12 Receive Mixer and LO Buffers RF+ BB- RF- M4 M3 M2 M1 BB+ VDD/2 LO RF - LO RF + _ + OP1 + _ M0 OP0 -+ VDD/2 Common-Mode Feedback and Replica Bias LO in + LO in - Passive I/Q Mixer Using NMOS Native Devices Two-Stage Inductorless LO Buffer

13 Direct Conversion Transmitter LO RF (I) 2 LO RF 2 LO RF (Q) 9 DAC PGA I RFVGA PA XPA RF out 9 DAC Q Total current = 29mA RF Loopback to RX

14 Segmented Power Amplifier Vdd V out + V out - Vdd M5 M6 M7 M8 V in + V in -... M1 M2 M3 M4 V in + V in - b1 SW1... b4 SW4

15 Digital Calibration and RF Loopback LO RF DAC RF in ADC 1 RXBB RF out SW0 LO RF DAC 9 TXBB MODEM Calibration of Analog Imperfections Receiver filter bandwidth Receiver DC offset I/Q mismatch Transmitter carrier leak

16 Receiver Sensitivity Sensitivity (dbm) PHS Sensitivity Standard 9dB Sensitivity = -106dBm Receiver Noise Figure = 3.5dB Channel Frequency (MHz)

17 Receiver Adjacent Channel Selectivity (ACS) Adjacent Channel Selectivity (dbc) ACS Spec = 50dBc PHS modulated blocker at 600kHz offset ACS PHS Signal -94dBm 600kHz PHS Blocker Channel Frequency (MHz)

18 Adj. Ch. Selectivity (PHS modulated blocker at 600kHz offset) 55 Receiver 2-Tone Intermodulation Intermodulation (dbc) Intermod Spec = 47dBc Intermod 2 equal sized single-tone blockers at 600kHz &1.2MHz offset PHS Signal -94dBm 600kHz 1200kHz Blockers Channel Frequency (MHz)

19 Ref 10dBm Transmit Spectrum Log 10dB/ PHS standard requires OBW < 288kHz OBW = Occupied BW containing 99% signal power Measured OBW < 250kHz for all channels Center 1.907GHz Res BW 10kHz Span 2MHz

20 Transmitter Modulation Accuracy Q Q Frequency: MHz Frequency Error: khz RMS Vector Error: 3.80% Peak Vector Error: 7.82% Output Power: 0dBm I Frequency: MHz Frequency Error: khz RMS Vector Error: 1.03% Peak Vector Error: 2.50% Output Power: -10dBm PHS Standard requires EVM less than 12.5% I

21 Transmit Adjacent Channel Power (ACP) Adjacent Channel Power (dbm) PHS signal 18.5dBm with xpa Spec >8dB Margin ACP -36 Spec kHz 600kHz ACP dB Margin 900kHz ACP Channel Frequency (MHz)

22 Synthesizer Phase Noise at MHz =-118dBc/Hz Phase Noise (dbc/hz) Frequency Offset (MHz)

23 Measured Synthesizer Settling Time Frequency Offset (Hz) 10M 1.0E+07 1M 1.0E k 1.0E+05 10k 1.0E+04 1k 1.0E E E+01 Settling Time to 1kHz =15ms 1 1.0E Time (ms) Time (us)

24 Die Micrograph TX SYNTH RX BIAS AUDIO

25 Performance Summary Power Dissipation RF Transmitter RF Receiver RF Synthesizer Talk Mode (1/8 duty cycle Tx & Rx) Standby Mode Phase 1.9GHz Settling time to +/- 1kHz Receive Sensitivity Receiver Noise Figure Transmit Power (EVM compliant) Transmit EVM Technology 29mA 32mA 25mA 81mA (including audio and digital) 1mA (including audio and digital) 600kHz offset 15ms -106dBm 3.5dB +4 dbm 4% 1dBm 1% -10dBm Standard 0.18mm CMOS Supply Voltage 3.0V with internally regulated 1.8V Die Size: Package Total RF and Analog 33 mm 2 12 mm pin BGA

26 Conclusions Demonstrated single-chip PHS cellphone in 0.18 µm standard digital CMOS SoC performance meets or exceeds all PHS specifications System on a single chip allows for digital calibration to ease requirements of analog circuits

27 Acknowledgments The authors wish to acknowledge the contributions from the entire PHS team at Atheros, especially their efforts in algorithm development, digital design, and system design and verification