Challenges in Designing CMOS Wireless System-on-a-chip
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1 Challenges in Designing CMOS Wireless System-on-a-chip David Su Atheros Communications Santa Clara, California IEEE Fort Collins, March 2008 Introduction Outline Analog/RF: CMOS Transceiver Building Blocks Digital: System-on-a-chip Integration Conclusion IEEE Fort Collins, March p 2 D. Su,
2 SoC Trends: GSM (1995) Stetzler et al, ISSCC 95 (AT&T) Integrated Transceiver with external components (e.g. filters) IEEE Fort Collins, March p 3 D. Su, 2008 SoC Trends: GSM (2006) Bonnaud et al, ISSCC 06 (Infineon) SoC with integrated transceiver and CPU. IEEE Fort Collins, March p 4 D. Su,
3 SoC Trends: WLAN (1996) Prism WLAN chipset (Harris Semi) AMD App Note ( Multi-Chip b Transceiver IEEE Fort Collins, March p 5 D. Su, 2008 SoC Trends: WLAN (2008) Nathawad et al, ISSCC 08 (Atheros) 11a/b/g/n (2x2 MIMO) Radio SoC IEEE Fort Collins, March p 6 D. Su,
4 Advantages of SoC Integration Increased functionality Smaller Size / Form Factor Lower Power On-chip interface Lower Cost Single package Ease of use Minimum RF board tuning Reduced component count Improved reliability IEEE Fort Collins, March p 7 D. Su, 2008 Cost of WLAN Data Throughput Zargari, 2007 VLSI Symposium Short Course IEEE Fort Collins, March p 8 D. Su,
5 CMOS RF Design Advantages Low-cost, high-yield Multi-layer interconnect makes decent inductors High-level of integration supports sophisticated digital signal processing Challenges: Multi-GHz: narrowband design with inductors No high-q BPF: architecture + dynamic range Process/Temp Variation: DSP algorithms Reduced supply headroom: IO devices Noise coupling: careful design & layout IEEE Fort Collins, March p 9 D. Su, 2008 CMOS Transceiver Building Blocks Signal Amplification Frequency Translation Frequency Selectivity IEEE Fort Collins, March p 10 D. Su,
6 Transceiver Block Diagram Receiver LO I ADC LNA ADC Switch LO LO Q Synthesizer Digital Signal Processor LO I DAC PA DAC RFVGA Transmitter LO Q IEEE Fort Collins, March p 11 D. Su, 2008 Tuned CMOS RF Gain stage V IN C R L gmv IN R L C L Equivalent Model gm R X 2I D V GS V T Q ω o C = 2I D Qω o L V GS V T Low power design: high Q smaller feature size technology: gm, V DD IEEE Fort Collins, March p 12 D. Su,
7 LNA Design Goal Low Noise Figure Sufficient gain Able to accommodate large blockers Large Dynamic Range Large Common-mode Rejection High Linearity IEEE Fort Collins, March p 13 D. Su, 2008 LNA with Cascoded Diff Pair IN IN BIAS Input match Noise Figure IEEE Fort Collins, March p 14 D. Su,
8 LNA with Switchable Gain gain gain gain M1 M2 M3 M4 IN IN BIAS CMRR at RF Switchable gain for high DR Zargari et al, JSSC Dec 2004 (Atheros) IEEE Fort Collins, March p 15 D. Su, 2008 LNA with GM Linearization Single-ended equivalent RF OUT Bias1 RF IN Bias2 M1 M2 Nonlinearity Compensation with two parallel transistors Kim et al, JSSC Jan 2004 (KAIST) IEEE Fort Collins, March p 16 D. Su,
9 CMOS Power Amplifiers Output power (and efficiency) depends on V DD P out 2 V DD R L Lower supply voltage reduces output power Cascoding (to support a higher V DD ) Parallel Combining (of lower power PAs) IEEE Fort Collins, March p 17 D. Su, 2008 Cascoded Power Amplifier L1 L2 RF OUT RF IN M1 M2 Cascoding advantages 3.3V supply voltage Stability Capacitive Level-shift Single-ended equivalent Bias Differential Off-chip balun IEEE Fort Collins, March p 18 D. Su,
10 Cascoded Power Amplifiers RF OUT RF OUT Bias2 Bias1 Bias1 Bias2 RF IN RF IN P MAX = 22 dbm P OFDM = 17.8 dbm (BPSK) Zargari et al, JSSC Dec 2002 (Atheros) IEEE Fort Collins, March p 19 D. Su, 2008 Power Amplifiers with Parallel Amplification IN PA λ/4 Large OUT Small Load IEEE Fort Collins, March p 20 D. Su,
11 Power Amplifiers with Parallel Amplification IN PA Off λ/4 Large OUT Small Load IEEE Fort Collins, March p 21 D. Su, 2008 Power Amplifiers with Parallel Amplification PA1 λ/4 IN PA2 λ/4 OUT PA3 λ/4 Load Shirvani et al, JSSC June 2002 (Stanford) IEEE Fort Collins, March p 22 D. Su,
12 Power Amplifiers with Parallel Amplification Shirvani et al, JSSC June 2002 (Stanford) IEEE Fort Collins, March p 23 D. Su, 2008 PA Peak to Average Ratio Improved spectral efficiency (higher bits per Hz) Large peak to average ratio reduces power efficiency of the PA Example: a/g OFDM has PAR of 17dB Class A efficiency of ~ 1% Infrequent signal peaks 16-QAM OFDM, PAR of 6dB degrades SNR by only 0.25dB* Class A Efficiency ~ 12% 64-QAM OFDM, PAR of 12dB is needed Class A Efficiency ~ 3% * Van Nee & Prasad, OFDM for Wireless Multimedia Communications, Artech House, 2000 IEEE Fort Collins, March p 24 D. Su,
13 Power Amplifiers with Dynamic Bias Predrivers PA IN OUT Bias 1/α 64-QAM OFDM Efficiency ~ 10% Zargari et al, JSSC Dec 2004 (Atheros) IEEE Fort Collins, March p 25 D. Su, 2008 Power Amplifiers with Dynamic Bias Zargari et al, JSSC Dec 2004 (Atheros) IEEE Fort Collins, March p 26 D. Su,
14 Polar Modulated Power Amplifier LF Magnitude RF RF Output Phase RF Power Amplifier IEEE Fort Collins, March p 27 D. Su, 2008 Digitally Modulated Polar Power Amplifier 6 Decoder I Q I/Q to Polar Magnitude Phase PA 1 PA 2 OUT Kavousian et al, ISSC 2007 (Stanford) PA 64 IEEE Fort Collins, March p 28 D. Su,
15 Digitally Modulated Polar Class-A Power Amplifier L2 Matching Network RF OUT Ctrl1 Ctrl2 Ctrl64 Phase M1 M2 Kavousian et al, ISSC 2007 (Stanford) M64 Bandwidth: 20MHz Frequency: 1.6GHz EVM: -26.8dB Power: 13.6dBm IEEE Fort Collins, March p 29 D. Su, 2008 Frequency Translation RF Baseband Architecture: Superhetrodyne Sliding IF, low IF, Direct Conversion Components: Mixers: Active or Passive (lower power) Local Oscillator: Frequency Synthesizer IEEE Fort Collins, March p 30 D. Su,
16 Active CMOS mixer Baseband Output LO LO LO IN IN Brandolini et al, ISSCC 2005 (Univ of Pavia) IEEE Fort Collins, March p 31 D. Su, 2008 Passive CMOS Mixer LO RF- RF+ BB+ LO Buffer LO RF+ VDD/2 + - Bias1 M0 Bias0 + - VDD/2 RF- LO RF- BB- Replica Bias Mehta et al, ISSCC 2006 (Atheros) LO IN + LO IN - IEEE Fort Collins, March p 32 D. Su,
17 Frequency Synthesizer Xtal Osc Reg1 Reg2 Ref Div DFF PFD CP VCO 40MHz Loop Filter 16/17 Divider DFF P & S Counter 8/8.5 Div / 2 Terrovitis et al, ISSCC 2004 (Atheros) f vco/4 I Q LO Buffers IEEE Fort Collins, March p 33 D. Su, 2008 Voltage Controlled Oscillator Regulated V DD Digital Control Analog Control Terrovitis et al, ISSCC 2004 (Atheros) IEEE Fort Collins, March p 34 D. Su,
18 Measured Phase Noise Phase Noise (dbc/hz) GHz 2.4 GHz Terrovitis et al, ISSCC 2004 (Atheros) 1K 10K 100K 1M 10M Frequency Offset (Hz) IEEE Fort Collins, March p 35 D. Su, 2008 Frequency Selectivity Superhetrodyne conversion IF filtering: external SAW filter expensive On-chip RF/IF high-q filtering difficult Direct conversion Baseband filtering: Modest filtering to avoid anti-aliasing Blocker filtering in digital domain IEEE Fort Collins, March p 36 D. Su,
19 Anti-alias Low-pass gm-c Filter Ref Clock Replica Biquad Phase Detector State Machine Capacitor setting IN OUT Low-Q Biquad High-Q Biquad Transresistance Amplifier I in -g m2 Zargari et al, JSSC Dec 2004 g m1 g m3 g m4 I out IEEE Fort Collins, March p 37 D. Su, 2008 System-on-a-Chip Integration Analog/RF DIGITAL Digital Power Consumption Digital Calibration techniques Noise Coupling IEEE Fort Collins, March p 38 D. Su,
20 Digital Power Consumption Digital circuits (PHY, MAC, CPU, IO, memory) occupies most of the area of a wireless SoC: Reducing active digital power Lower supply voltage Lower interconnect capacitance Small geometry CMOS Clock gating of inactive digital logic IEEE Fort Collins, March p 39 D. Su, 2008 Digital Leakage Power Transistor leakage current has increased dramatically with technology scaling Leakage current reduction Customized low-power (LP) process Circuit techniques: Transistor stacking Multiple threshold voltages Dynamically adjusted threshold (backgate bias) Multiple supply voltages Dynamically adjusted supply voltages IEEE Fort Collins, March p 40 D. Su,
21 Digital Calibration Issues Digital logic to compensate/correct for imperfections of analog and RF circuits can enable: Lower power, smaller area, improved reliability of analog/rf Desired properties of calibration: Independent of temperature, aging, frequency Inexpensive (in area and power) to implement Do not interfere with system performance Wireless SoC advantage: Calibration building blocks already exist on-chip: transmitter and receiver, data converters, and CPU No package pin limitation IEEE Fort Collins, March p 41 D. Su, 2008 Calibration Techniques Test Signal Rx Gain: Thermal noise Rx I/Q mismatch: Live Rx traffic Tx carrier leak: Dedicated test signals from DAC Receive filter bandwidth: RF loop back Observation Signal ADC outputs Comparator outputs Tuning Mechanism Dedicated DAC Selectable capacitors, resistors, transistors IEEE Fort Collins, March p 42 D. Su,
22 Example: Tx Carrier Leak LO DAC DAC RX Offset Adj LNA ADC RX Carrier Leak Correction PA LO DAC Test signal: Tx DAC Observation signal: RF loop back to Rx ADC Tuning: Carrier Leak Correction at Tx DAC input + TX Digital Baseband IEEE Fort Collins, March p 43 D. Su, 2008 Noise Coupling IEEE Fort Collins, March p 44 D. Su,
23 Digital Noise Source Reduce noise by turning off unused digital logic Clock gating Avoid oversized digital buffers Stagger digital switching Avoid large number of digital pads switching simultaneously Avoid switching digital logic at the same sampling instance of sensitive analog IEEE Fort Collins, March p 45 D. Su, 2008 Noise Coupling Mechanism Supply noise coupling Separate or star-connected power supplies Capacitive coupling to sensitive signals and bias voltages Careful routing of signal traces to reduce parasitic capacitance Use ground return-path shields Substrate coupling induced V TH modulation Low-impedance substrate connection Guard rings Physical separation Deep Nwell IEEE Fort Collins, March p 46 D. Su,
24 Noise Destination Increase immunity of sensitive analog and RF circuits Fully differential topology Dedicated on-chip voltage regulators Avoid package coupling by keeping sensitive nodes on chip (Example: VCO control voltage) IEEE Fort Collins, March p 47 D. Su, 2008 Conclusions CMOS has become the technology of choice for integrated radio systems Integrating a radio in mixed-signal System-on-a-Chip is no longer a dream but a reality Wireless SoC can provide significant advantages in size, power, and cost IEEE Fort Collins, March p 48 D. Su,
25 Continuing Challenges Wireless SoCs with integrated radios will be as ubiquitous as today s mixed-signal SoCs with integrated ADC Multi-mode radios to support several wireless standards Challenge of radio designers will still be: Power consumption / Battery life Range Data rate Cost IEEE Fort Collins, March p 49 D. Su, 2008 Acknowledgments Many of the slides are based on previous presentations from Atheros Communications, especially those by: Masoud Zargari, Manolis Terrovitis, Srenik Mehta, William Si, William McFarland, Lalitkumar Nathawad of Atheros Communications IEEE Fort Collins, March p 50 D. Su,
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