65-GHz Receiver in SiGe BiCMOS Using Monolithic Inductors and Transformers

Transcription

1 65-GHz Receiver in SiGe BiCMOS Using Monolithic Inductors and Transformers Michael Gordon, Terry Yao, Sorin P. Voinigescu University of Toronto March , UBC, Vancouver

2 Outline Motivation mm-wave overview Receiver design Active and passive components Circuit building blocks Full 65-GHz receiver integration Summary 2

3 Work Motivation 7 GHz of unlicensed spectrum (57-64 GHz) High data rate 60-GHz WLAN (500Mb/s to 2Gb/s) mm-wave sensors for medical / security applications Design advantages over 5-10 GHz RF Simpler radio architecture - A lot of bandwidth available Smaller devices higher integration smaller die area Atmospheric attenuation due to oxygen 3

4 Research Goals Demonstrate a highly integrated 65-GHz receiver in silicon including the VCO Develop and apply low-noise design techniques across different mm-wave receiver building blocks Validate the use of monolithic inductors in mm-wave circuits 4

5 65-GHz Receiver Overview GHz RF RF LNA Vdd Gilbert Mixer 0-5 GHz IF Buffer IF IF GHz LO RF LO RF IF

6 Link Budget Estimation Sensitivity = 10 log ktb + NF + SNR + 30 dbm RF Sensitivity for 1 GHz BW, SNR=10 db, NF=10 db dbm For a dynamic range of 30 db need an input compression point of at least -22 dbm! Must optimize both linearity and noise in receiver design 6

7 Bottom-up system design approach Transistor characterization and optimization Verify foundry models to 65 GHz Passive devices Inductor and transformer design and optimization Building blocks LNA Downconversion Mixer VCO IF Amplifier Receiver integration 7

8 Technology Characterization: Active Devices Production Jazz Semiconductor SBC18HX SiGe BiCMOS process NF min extracted from measured Y-Parameters [S. P. Voinigescu et al, JSSC Sep 97] [K. H. Yau et al, SiRF 2006] Valid below f T /2 5.24μm x 0.2μm HBT f T, f MAX = 150 GHz Good agreement with simulator Validates HBT model Frequency (GHz) NF MIN (60GHz, Sim) NF MIN (60GHz, Meas) f MAX (Meas) f MAX (Sim) f T (Sim) f T (Meas) Current Density (ma / μm 2 ) NF min (db) 8

9 Technology Characterization: Passive Devices 1 Stacked multi-metal spiral inductors Occupy smaller area compared to CPW or μ-strip t-lines METAL6 METAL5 29 μm 9

10 Technology Characterization: Passive Devices 2 1:1 vertically stacked transformer Implemented in adjacent metal layers for tighter coupling Compact and low-loss Operates up to 80 GHz 34 μm Single-ended measurements 240 ph each winding 10

11 Inductors for WiFi Frequencies To achieve Q > 10 at 2-5 GHz must use wide metals Such large inductors radiate stronger mm-wave inductors are x smaller! 250 μm 29 μm 300 ph Q > 60 GHz 700 ph Q > 5 GHz 11

12 LNA Design Methodology 1 Design for concurrent noise and power matching [M. Gordon, ESSCIRC 04] Lowest noise, highest gain 1. Fix transistor biasing 2. Size Q 1 to match R sop Optimal noise matching Z sop 3. Add L E and L B to match Z in Optimal power matching Z in 12

13 R sop matching LNA Design Methodology 2 R sop I f n f C T T ( re + rb) VT β0f 4β0f C T n T ( re + rb) T β0 β0 RnfT f I f f 2V f 4 f 2 nvt n + e + b 2IC ( ) R r r Z in matching Rin = rb +ωtle Xin b e 11 Rsop ~ fle Smaller devices at higher frequencies 1 = ω ( L + L ) r b, C be ωc be Smaller L e, L b 13

14 Building Blocks: 65-GHz LNA V CC =3.3 V L C = 120 ph R C2 =1 k RF OUT-DIFF L PRI/SEC = 160 ph 3.58*2 /0.2um C C = 23 ff 3.58*2 /0.2um RF IN L B = 90 ph 4.52*2 /0.2um 3.58*2 /0.2um 480 μm L E = 60 ph L E2 = 60 ph J C1 = 4.2 ma J C2 = 6.7 ma 2 variants of 65-GHz LNA: Inductor matched output network Transformer matched output network Simulated NF = 10.5 db Input P 1dB = dbm Consumes 45 mw from 3.3V 370 μm 14

15 Building Blocks: Mixer RF IN V CC =3.3 V LO+ 100 ph 100 ph IF /0.2um 7.34 /0.2um /0.2um 7.34 /0.2um LO- IF- LO+ Gilbert Cell Topology Simulated: Conversion gain of 6 db NF ~ 16 db Differential Input P 1dB = -1 dbm 70 ph 70 ph Requires LO > +3 dbm V BIN ma 15

16 Building Blocks: VCO Lc Ls Cp L B LO+ Vbb R B3 4V R B1 R B2 LO- Vdd Cp L B`` Ls Lc Differential Colpitts Topology Based on 59 GHz VCO from [C. Lee, CSICS 2004] LC-varactor tank Need high output power and low phase noise for mixer Requires 4V supply (60 ma tail) L E C1 C2 R B4 Vtune C2 C1 L E Differential LO power +4 dbm PN 1MHz = -104 dbc / Hz Frequency Range GHz EF Buffer to isolate from mixer L EE L EE R T C T Accumulation mode NMOS 16

17 V CC =3.3 V Building Blocks: IF Amplifier 60 IF OUT 35 x 2/0.18 IF IN 30 ma MOS differential pair biased at 0.2 ma/μm for maximum linearity 3-dB bandwidth is 10 GHz Differential Input P 1dB = +1.7 dbm The limiting linearity block in the receiver chain 17

18 Fully Integrated Receiver 1 First 65-GHz receiver in silicon to integrate VCO Total power is 540 mw LNA + Mixer = 80 mw VCO + Buffer = 360 mw IF Amp = 100 mw Core is 550μm x 440μm Compact passives Tight layout important to reduce parasitics at 65 GHz 18

19 Fully Integrated Receiver 2 Nominal operation Gain = 24 db differential Input P 1dB = -22 dbm NF = 12 db (11.5 db simulated) Dynamic range = 28 db Rx can operate from 2.5V (VCO still at 4V) 450 mw Gain = 15 db, NF = 12.2 db Gain = 14 db P in,1db = -13dBm Gain = -1 db SE to DIFF Gain = 7 db P in,1db = -1 dbm Gain = 4 db P in,1db = 1.7 dbm RF LNA Vdd Gilbert Mixer Buffer IF IF 19

20 State of the Art Comparison Technology (ft / fmax) 0.12μm SiGe (200/290 GHz) 0.13μm CMOS (70/135 GHz) 0.13μm CMOS (80/- GHz) 0.18μm SiGe Bipolar (150/150 GHz) Integration Level LNA, mixer, branch-line coupler, PLL LNA LNA, μ-strip balun, quadrature mixer LNA LNA, mixer, VCO, transformer balun, IF amplifier Freq GHz 60 GHz 60 GHz 65 GHz 65 GHz Gain 40 db 12 db 28 db Voltage gain 14 db 24 db NF 6 db 8.8 db 12.5 db (extracted) 10.5 db (sim) 12 db P 1dB -36 dbm -9 dbm dbm dbm -22 dbm DC Pow er 530 mw (2.7V) 54 mw (1.5V) 9 mw (1.2V) 36 mw (2.5V) 540 mw (3.3V, 4V for VCO) Die area 3.4 x 1.7 mm 1.3 x 1.0 mm 0.3 x 0.4 mm (no 0.37 x x 0.74 mm pads) mm Reference Floyd et al, ISSCC Feb '06 Doan et al, JSSCC Jan '05 B. Razavi, ISSCC 05 This work 20

21 Summary First 65-GHz silicon receiver to integrate a VCO Excellent agreement between simulated and measured results Diligent layout Small parasitics matched performance Current silicon technology is mature enough for mmwave radio SoCs Advancement of monolithic inductor research Demonstrated stacked transformer in a tuned circuit 21

22 Future Goal of Integration On chip antenna Very small wavelength at mm-wave frequency 1400 μm 800 μm 1100 μm [C.-H. Wang et al, ISSCC 2006] 22

23 Acknowledgments Jazz Semiconductor for fabrication CMC for CAD support CFI for laboratory equipment NSERC, Micronet, and CWTA for financial support 23

24 Questions? 24