Research and Development Activities in RF and Analog IC Design. RFIC Building Blocks. Single-Chip Transceiver Systems (I) Howard Luong

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1 Research and Development Activities in RF and Analog IC Design Howard Luong Analog Research Laboratory Department of Electrical and Electronic Engineering Hong Kong University of Science and Technology Outline Activities in RFIC and Systems RFIC Building Blocks Single-Chip Transceiver Systems for Wireless Applications Activities in Analog and Mixed-Signal ICs Analog and Mixed-Signal ICs Mixed-Signal Systems Industrial Support and Collaboration Integrated-Circuit Industrial Consortium (IC2) Contract Projects Intensive Publication Journal of Solid-State Circuits (JSSC) International of Solid-State Circuit Conference (ISSCC) Chip Olympics RFIC Building Blocks Low-Voltage CMOS RFIC Building Blocks (for GSM 900/1800, Bluetooth, WLAN, Cable TV Tuner, UWB, CDR) Fully-Integrated CMOS Frequency Synthesizers Clock-Data Recovery Circuit for Optical Communication 1-V 24-GHz Phase-Locked Loop Wideband LNAs and Mixers On-Chip Image-Rejection and Channel-Selection Filters Sigma-Delta Bandpass Analog-To-Digital Converters CMOS Fully-Integrated Power Amplifiers Single-Chip Transceiver Systems (I) Single-Chip CMOS 900-MHz GSM Wireless Transceiver Integrate ALL Building Blocks On-Chip Design in a 0.5-µm Standard Digital CMOS Process First-Time Demonstration of Single-Chip GSM Transceiver Highest On-Chip Image Rejection and Smallest Chip Area Single-Chip 1-V 2.4-GHz CMOS Bluetooth Receiver Single 1-V Supply (Device Threshold Voltage of 0.7 V, without On-Chip Voltage Multipliers) Total Power of 10 mw Inductorless Frequency Synthesizer with Fast Settling Switched-Capacitor Techniques for Channel-Selection Filter and Sigma-Delta Bandpass ADC

2 Single-Chip Transceiver Systems (II) CMOS 1-V 5.2-GHz Wireless Transceiver for WLAN Applications (IEEE a) System-On-Chip Single 1-V Supply Low Power ( < 50 mw for Both Receiver and Transmitter) Embedded Power-Management Circuitry Single-Chip CMOS TV Tuners (Cable, DVB-T, DVB-H) Frequency Band (54 MHz 880 MHz) Wide Bandwidth (6 MHz) Novel Single-Conversion Architecture without Tracking Filter Integrate On-Chip 44-MHz Channel-Selection Filter Small Chip Area, Low Power, Low Cost Single-Chip Transceiver Systems (III) CMOS Ultra-Wideband (UWB) Transceiver Frequency Band (3.1 GHz 10 GHz) Wide Bandwidth (> 500 MHz) High Data Rate and Low Power Single-Chip Single-Chip UHF RFID Passive Readers and Tags Fully Integrated in A Single Chip Low Cost Low Power UHF: 900 MHz Long Distance: 40 Feet Multiple Standards Analog and Mixed-Signal ICs High-Q High-Dynamic-Range Filters: 70-MHz Gm-C Bandpass Filters with Automatic Tuning (Q =350) 1-V 10.7-MHz Switched-Capacitor Bandpass Filters Novel Switched-Opamp Technique (US Patent) 44-MHz Switched-Capacitor Bandpass Filters for Cable Tuner Applications 70-MHz Switched-Capacitor Bandpass Filters Analog-To-Digital Converters (ADCs) Voltage-Mode / Current-Mode Pipeline ADC 70-MHz Gm-C Bandpass Sigma-Delta ADC 1-V 10.7-MHz Switched-Capacitor Bandpass Sigma-Delta ADC Mixed-Signal Systems Ultra-Low-Power Signal-Conditioning Circuits and Systems for Biomedical Applications (Pacemaker): 1-V 0.2-µW Single-Opamp Switched-Capacitor Bandpass Filters and Sigma-Delta ADC 1-V 0.5-µW Single-Opamp Switched-Capacitor Signal- Conditioning System for Pacemaker

3 A Monolithic 900-MHz CMOS GSM Wireless Transceiver LNA IRF BPF AGC BPSD PA Fractional-N synthesizer with sigma-delta modulation + Gaussian Filter Base-band input Process Sensitivity SNR NF IIP3 Image Rejection Output Power PAE Power Consumption 0.5µm CMOS -90dBm 9dB 22dB -25dBm 79dB 55mW 21% 227mW 2.402GHz 2.48GHz LNA I-Channel Proposed 1-V 10-mW Bluetooth Receiver Image-Reject Mixer GHz GHz Q-Channel Anti-aliasing filter Poly-phase filter Anti-aliasing filter I-Channel 2 nd -order channel-select filter + _ LO Channel-selection pins IF = 0.6 MHz Σ -modulated frequency synthesizer Quadrature SO IF circuitry Sampling rate = 11 MHz Time-sharing of active elements VGC (0dB-24dB) VGC (0dB/6dB) VGC (0dB/6dB) Q-Channel 5 th -order lowpass ladder filter Fref DSP 3 rd -order Σ ADC A 1-V 10-mW 2.4-GHz CMOS Bluetooth Receiver A 1-V 10-mW 2.4-GHz CMOS Bluetooth Receiver LNA Mixer VCO Charge Pump Loop Filter Pre-scalars Dividers Anti-Aliasing Filter PFD 3.4 mm SO Lowpass Filter SO Σ Modulator SO Bandpass Filter Clock Gen. 1.6 mm Technology 0.35-µm double-poly 4-metal CMOS process (V TN : 0.6V, V TP : -0.77V) 1 V Input Frequency 2.402GHz GHz Channel Bandwidth 1 MHz Sensitivity -70 dbm SNR 18 db with -70-dBm Input Signal Noise Figure 26 db Linearity (IIP3) - 22 Max. Gain Image Rejection 28 db Variable-Gain-Control 0dB to 36dB (6dB per step) Power Consumption Receiver: 10 mw Chip Area 3.4 x 1.6 mm 2

4 A 1-V 5.2-GHz CMOS WLAN a Transceiver On-chip ADC I A 1-V 5.2-GHz CMOS WLAN a Transceiver LO2(I) RF LNA LO1 LO2(Q) ADC Q Duplexer DAC I LO2(I) RF PA LO1 LO2(Q) DAC Q Frequency synthesizer LO GHz Div CP+LF Div +Σ PD LO2(I) GHz LO2(Q) A 1-V 5.2-GHz CMOS WLAN a Transceiver Power Consumption Chip Area Including Power- Management Circuitry Including ADC & DAC Process Existing Solutions 1.8V 150 mw (RX) 180 mw (TX) 13 mm 2 No No SiGe, BiCMOS, CMOS Proposed Transceiver 1.0V < 50 mw (RX) < 50 mw (TX) ~ > 10 mm 2 Yes Yes CMOS Proposed 1.8-V 670-mW Single-Chip Single- Conversion CMOS Cable TV Tuner LNA IQ Mixer MHz 44 MHz SYN Channel-Selection Filter VGA 44 MHz VGA

5 Proposed 1.8-V 670-mW Single-Chip Single- Conversion CMOS Cable TV Tuner Testing Structures Proposed 1.8-V 670-mW Single-Chip Single- Conversion CMOS Cable TV Tuner Novel Single-Conversion Architecture with Image Rejection Larger than 60 db (without trimming) Full Integrated in a CMOS Single-Chip Single Frequency Synthesizer with Single Wideband VCO Integrated 44-MHz Switched-Capacitor Channel- Selection Filter Low Power Consumption (~ 670 mw as compared to ~ > 2.0 W for Existing Solutions) Proposed 1.8-V 670-mW Single-Chip Single- Conversion CMOS Cable TV Tuner A 1-V 24-GHz CMOS Phase-Locked Loop Existing Solutions Proposed Tuner PD Process SiGe, BiCMOS, SOI CMOS CMOS Divider 1.8V 1.8V Loop Filter Power Consumption 2000 mw ~ 670 mw Buffer VCO On-Chip Channel- Selection Filter No Yes Chip Area > 12 mm 2 ~ 7.1 mm 2

6 A 1-V 24-GHz CMOS Phase-Locked Loop 1-V 5.2-GHz CMOS Frequency Synthesizer for WLAN Applications (802.11a) Parameter Technology Area Frequency Value 0.18-µm CMOS 6 metal layers 1.03mm GHz Power 1.0 V (as low as 0.85-V) 27.5 Integrated CMOS Frequency Synthesizer for DCS-1800 Wireless Systems Process Carrier Frequency Channel Spacing Architecture Reference Frequency Loop Filter Loop Bandwidth Phase Power 0.5µm CMOS 1.8GHz 200kHz Dual-loop 2 V 800kHz, 100MHz On-chip 120kHz, 42kHz -111dBc/Hz 95mW A 0.9-V 0.5-µW Signal-Conditioning Integrated System for PaceMaker Capacitor Array Capacitor Array Opamp CMFB Comparator DFF On-Chip Clock Generat or Process Filter ADC Technique Sampling Frequency Dynamic Range Peak SNDR Chip Area Power 0.35µm CMOS 3 rd -Order Low-Pass 3 rd -Order Low-Pass Σ Single Switchable- OpAmp 0.9 V 8.33 KHz 45 db 42 db 0.2 mm µw

7 Industrial Collaboration and Support Integrated-Circuit Industrial Consortium ( Patents and Intellectual Properties on IC Modules and Systems Available for Licensing and Technology Transfer Provide IC Design Services and Support: Consultancy Engineer Training Engineer-In-Residence Program Contract Work on IC Technology Transfer and Product Development: 1-V 2.5-GHz PLL (Completed) 488-MHz Synthesizer (Completed) Low-Phase-Noise 4.8-GHz PLL (On-Going) A 1-V 2.5-GHz Phase-Locked Loop A CMOS 488-MHz Frequency Synthesizer OFF 10pF ON A CMOS 488-MHz Frequency Synthesizer Crystal s Output 10pF 8-MHz Crystal Ω PULL-UP RESISTORS ON Channel Selection Frequency Synthesizer Output POWER DOWN POWER UP Synthesizer s Output Crystal Oscillator Output nF A ~5µA 500kΩ

8 A CMOS 488-MHz Frequency Synthesizer A CMOS 488-MHz Frequency Synthesizer 2.7V - 3.3V Number of Channels 63 Frequency Range MHz Frequency Resolution 1MHz Spurious Tone -35.3dBc@1MHz Frequency Accuracy of Crystal ±10kHz w/supply=2.7v-3.3v Power Crystal Oscillator 7mW Consumption Frequency Synthesizer 38mW (w/o crystal oscillator)* Output Power Crystal Oscillator -9.4dBm@50Ω Frequency Synthesizer -12dBm@50Ω Phase Noise Crystal Oscillator -139 dbc@500khz Frequency Synthesizer -93.5dBc@500kHz Books H. C. Luong and G. Leung, Low-Voltage CMOS RF Frequency Synthesizers, Cambridge University Press, August V. Cheung and H. C. Luong, Design of Low-Voltage CMOS Switched-Opamp Switched-Capacitor Systems, Kluwer Academic Publishers, July US Patents L. Leung and H. C. Luong, Integrated Variable Inductors with Wide Frequency Tuning Range, US Patent Application, 10/927,785, filed in August K. C. Kwok and H. C. Luong, "Low-Voltage Low-Phase-Noise Voltage- Controlled Oscillator with Transformer Feedback," US Patent Application, Serial No. 10/650,686, filed in August M. Waight, J. Marsh, and H. C. Luong, "Electronically Tuned Agile Integrated Bandpass Filter," US Patent Application, filed in August 2003 G. Leung and H. C. Luong, "A Double-Data Rate Phase-Locked-Loop with Phase Aligners to Reduce Clock Skew," US Patent Application, Serial No. 10/250,000, filed in May V. Cheung, J. Wong, and H. C. Luong, "Low-Voltage High-Frequency Frequency Divider Circuit," US Patent, No. 6,831,489, granted in December C. W. Lo and H. C. Luong, "Phase-Locked Loop Circuitry with Two Voltage-Controlled Capacitors," US Patent, No. 6,538,519, granted in March V. S. L. Cheung and H. C. Luong, "Switched-Opamp Technique for Low- Voltage Switched-Capacitor Circuits," US Patent, No. 6,344,767, granted in February 2002.

9 Representative Journal Publication (I) K. Chun, and H. C. Luong, Ultra-Low-Voltage High-Performance CMOS VCOs Using Transformer Feedback, IEEE Journal of Solid-State Circuits (JSSC), March 2005 K. Ng, and H. C. Luong, "A 28-MHz Wideband Switched-Capacitor Bandpass Filter with Transmission Zeros for High Attenuation," IEEE Journal of Solid-State Circuits (JSSC), March 2005 K. Ng, V. Cheung, and H. C. Luong, "A 44-MHz Wideband Switched- Capacitor Bandpass Filter Using Double-Sampling Pseudo-Two-Path Techniques," IEEE Journal of Solid-State Circuits (JSSC), March 2005 G. Leung, and H. C. Luong, "A 1-V 5.2-GHz 27.5-mW Fully-Integrated CMOS WLAN Synthesizer," IEEE Journal of Solid-State Circuits (JSSC), , Nov J. Wong, V. Cheung, H. C. Luong, "A 1-V 2.5-mW 5.2-GHz Frequency Divider in a 0.35-um CMOS Process," IEEE Journal of Solid-State Circuits (JSSC), pp , October 2003 V. S. L. Cheung, H. C. Luong, M. Chan, and W. H. Ki, "A 1-V 3.5-mW CMOS Switched-Opamp Quadrature IF Circuitry for Bluetooth Receivers, IEEE Journal of Solid-State Circuits (JSSC), pp , May Representative Journal Publication (II) V. S. L. Cheung, H. C. Luong, and W. H. Ki, "A 1-V 10.7-MHz Switched- Opamp Bandpass Sigma Delta Modulator Using Double-Sampling Finite- Gain-Compensation Technique," IEEE Journal of Solid-State Circuits (JSSC), pp , Oct T. Kan, G. Leung, and H. C. Luong, "A 2-V 1.8-GHz Fully-Integrated CMOS Dual-Loop incidence Synthesizer," IEEE Journal of Solid-State Circuits (JSSC), Vol. 37, No. 8, pp , August C. B. Guo, C. W. Lo, T. Choi, I. Hsu, D. Leung, T. Kan, A. Chan, H. C. Luong, "A 900-MHz Fully-Integrated CMOS Wireless Receiver with On-Chip RF and IF Filters and 79-dB Image Rejection IEEE Journal of Solid-State Circuits (JSSC), Vol. 37, No. 8, pp , August C. W. Lo and H. C. Luong, "A 1.5-V 900-MHz Monolithic CMOS Fast- Switching Frequency Synthesizer for Wireless Applications," IEEE Journal of Solid-State Circuits (JSSC), Vol. 37, No. 4, pp , April W. Yan and H. C. Luong, "A 2-V 900-MHz Monolithic CMOS Dual-Loop Frequency Synthesizer for GSM Wireless Receivers," IEEE Journal of Solid- State Circuits (JSSC), Vol. 36, No. 2, pp , February V. S. L. Cheung, H. C. Luong, and W. H. Ki, "A 1-V Switched-Opamp Switched-Capacitor Pseudo-2-Path Filter," IEEE Journal of Solid-State Circuits (JSSC), Vol. 36, No. 1, pp , January 2001 Representative Conference Publication (I) A. Ng, G. Leung, K. C. Kwok, L. Leung, and H. C. Luong, "A 1-V 24-GHz 17.5-mW Phase-Locked Loop in a 0.18-um CMOS Process," IEEE International Solid-State Circuit Conference 2005 (ISSCC), San Francisco, USA, February 2005 V. S. L. Cheung and H. Luong, "A 3.3-V 240-MS/s CMOS Bandpass Sigma- Delta Modulator Using a Fast-Settling Double-Sampling SC Filter," VLSI Symposium on Circuits, Hawaii, USA, June 2004 K. C. Kwok, and H. C. Luong, "A 0.35-V 1.46-mW Low-Phase-Noise Oscillator with Transformer Feedback in Standard 0.18-um CMOS Process, IEEE Custom Integrated Circuits Conference 2003 (CICC), San Jose, USA, September K. Ng, and H. C. Luong, "A 28-MHz Wide-Band Switched-Capacitor Bandpass Filter with High Attenuation," IEEE Custom Integrated Circuits Conference 2003 (CICC), San Jose, USA, September V. Cheung, and H. C. Luong, "A 1-V 10-mW Monolithic Bluetooth Receiver in a 0.35-um CMOS Process," 2003 European Solid-State Circuits Conference (ESSCIRC), Estoril, Portugal, September G. Leung, and H. C. Luong, "A 1-V 5.2-GHz 27.5-mW Fully-Integrated CMOS WLAN Synthesizer," 2003 European Solid-State Circuits Conference (ESSCIRC), Estoril, Portugal, September Representative Conference Publication (II) G. Leung, and H. C. Luong, "A 1-V 13-mW 2.5-GHz Double-Rate Phase- Locked Loop with Phase Alignment for Zero Delay," 2003 European Solid- State Circuits Conference (ESSCIRC), Estoril, Portugal, September V. Cheung, and H. C. Luong, "A 0.9-V 0.5-uW CMOS Single-Switched- Opamp-Based Signal-Conditioning System for Pacemaker Applications," IEEE International Solid-State Circuit Conference 2003 (ISSCC), San Francisco, USA, February J. Wong, V. Cheung, H. C. Luong, "A 1-V 2.5-mW 5.2-GHz Frequency Divider in a 0.35-um CMOS Process," 2002 Symposium on VLSI Circuits, Hawaii, USA, June V. Cheung, H. C. Luong, M. Chan, W. H. Ki, "A 1-V 3.5-mW CMOS Switched-Opamp Quadrature IF Circuitry for Bluetooth Receivers," 2002 Symposium on VLSI Circuits, Hawaii, USA, June C. B. Guo, C. W. Lo, T. Choi, I. Hsu, D. Leung, T. Kan, A. Chan, H. C. Luong, "A 900-MHz Fully-Integrated CMOS Wireless Receiver with On- Chip RF and IF Filters and 79-dB Image Rejection," Symposium on VLSI Circuits, Kyoto, Japan, June 2001

10 Representative Conference Publication (III) V. S. L. Cheung, H. C. Luong, and W. H. Ki, "A 1-V 10.7-MHz Switched- Opamp Bandpass Sigma Delta Modulator Using Double-Sampling Finite- Gain-Compensation Technique" IEEE International Solid-State Circuit Conference 2001 (ISSCC), San Francisco, USA, February 2001 W. Yan and H. C. Luong, "A 2-V 900-MHz Monolithic CMOS Dual-Loop Frequency Synthesizer for GSM Wireless Receivers," European Solid-State Circuits Conference (ESSCIRC), Stockholm, Sweden, September T. Kan and H. C. Luong, "A 2-V 1.8-GHz Fully-Integrated CMOS Dual- Loop Frequency Synthesizer," Symposium on VLSI Circuits 2000, Hawaii, USA, June 2000, pp C. W. Lo and H. C. Luong, "A 1.5-V 900-MHz Monolithic CMOS Fast- Switching Frequency Synthesizer for Wireless Applications," Symposium on VLSI Circuits 2000, Hawaii, USA, June 2000, pp V. S. L. Cheung, H. C. Luong, and W. H. Ki, "A 1-V Switched-Opamp Switched-Capacitor Pseudo-2-Path Filter," IEEE International Solid-State Circuit Conference, USA, pp , 453, February 2000

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