IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 3, MARCH

Transcription

1 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 3, MARCH A Single-Chip CMOS Transceiver for UHF Mobile RFID Reader Ickjin Kwon, Member, IEEE, Yunseong Eo, Member, IEEE, Heemun Bang, Kyudon Choi, Sangyoon Jeon, Sungjae Jung, Donghyun Lee, and Heungbae Lee Abstract This paper describes a single-antenna low-power single-chip radio frequency identification (RFID) reader for mobile phone applications. The reader integrates an RF transceiver, data converters, a digital baseband modem, an MPU, memory, and host interfaces. The direct conversion RF receiver architecture with the highly linear RF front-end circuit and DC offset cancellation circuit is used to give good immunity to the large transmitter leakage. It is suitable for a mobile phone reader with single-antenna architecture and low-power reader solution. The transmitter is implemented in the direct up-conversion architecture. The frequency synthesizer based on a fractional-n phase-locked-loop topology offering 900 MHz quadrature LO signals is also integrated with the RF transceiver. The reader is fabricated in a 0.18 m CMOS technology, and its die size is 4.5 mm 5.3 mm including electrostatic discharge I/O pads. The reader consumes a total current of 89 ma apart from the external power amplifier with 1.8 V supply voltage. It achieves an 8 dbm P1dB, an 18.5 dbm IIP3, and a maximum transmitter output power of 4 dbm. Index Terms Mobile RFID reader, radio frequency identification (RFID), RFID reader, single-antenna UHF reader, single-chip CMOS reader. I. INTRODUCTION RADIO frequency identification (RFID) application is growing rapidly in many areas, such as supply chain managements, antifraud systems, and object tracking systems [1]. The mobile RFID technology currently integrates the RFID technology with the mobile communication network and it enables one to access the information from the tag with the mobile phone. A mobile RFID reader reads tags attached to the various applications in all places through an RFID reader-embedded mobile phone. The tag data contains a unique service code and the mobile phone acquires the relevant information and contents corresponding to the service code using the mobile network. The mobile RFID technology will enable users to receive real-time information on consumer products or data services through the mobile RFID reader chip embedded in their handsets. Customers can receive information on digital music content by touching the RFID tags at record shops. The mobile Manuscript received April 19, 2007; revised August 21, I. Kwon was with the Samsung Advanced Institute of Technology, Yongin , Korea. He is now with the Division of Electrical and Computer Engineering, College of Information Technology, Ajou University, Suwon , Korea ( ijkwon@ajou.ac.kr; ickjinkwon@gmail.com). H. Bang, K. Choi, S. Jeon, S. Jung, D. Lee, and H. Lee are with the Samsung Advanced Institute of Technology, Yongin , Korea. Y. Eo is with Kwangwoon University, Seoul , Korea. Digital Object Identifier /JSSC RFID service will enable users to obtain traffic information by recognizing RFID tags at bus stops. A user can send the plate number of a taxi he is riding in to his acquaintances, just by touching an RFID-enabled tag in the taxi. RFID applications can be used for travel and tourism information, and for verification of the authenticity of medical products. The RFID systems operating at low frequencies (125 khz or MHz) are limited in their data rates and distances. Due to the great demand for higher data rates, longer reading distance, and small antenna size, much attention has been given to the UHF frequency band RFID system [2] [4]. It is suitable for the mobile phone reader which requires a small form factor. To meet the demands of longer battery life and lower cost of mobile communication devices, the low-cost, low-power, single-chip reader draws great attention and thus the CMOS technology is believed to be the most promising candidate toward the system-on-a-chip (SoC), which integrates all the functions of a RF transceiver, data converters, a digital baseband modem, an MPU, memory, and host interfaces. In this paper, a CMOS RF transceiver for a single-antenna UHF mobile RFID reader operating at 900 MHz is designed and fabrication results in the 0.18 m CMOS process are reported. Section II describes the reader specification, and Section III describes the reader architecture. The detailed circuit designs are discussed in Section IV. Section V reports chip implementation results and Section VI concludes this paper. II. READER SPECIFICATION Mobile RFID reader specification is based on the UHF RFID standard including ISO/IEC Type C and Type B standard [2] [4]. ISO/IEC type C standard is a partially modified standard from the EPCglobal Class-1 Generation 2 [3]. The ISO standard specifies the air interface at the MHz band. The comparison of the mobile UHF RFID and the ISO/IEC type C standard is shown in Table I. The reader operation frequency is determined by the regulation of each region within the MHz band. For Korea, the UHF RFID band ranges from to 914 MHz with 200 khz channel space [4]. The data modulation scheme for the reader to the tag communication are double-sideband ASK (DSB-ASK), single-sideband ASK (SSB-ASK), and phase-reversal ASK (PR-ASK). The maximum data rate is different from the channel bandwidth. The designed reader operates at a maximum tag-to-reader data rate of 240 kb/s due to the bandwidth of the receiver chain of the reader. The tag-to-reader data rate can be extended to 640 kb/s by modifying the receiver bandwidth of the reader. The target maximum read range specification is 1 m. It is a relatively /$ IEEE

2 730 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 3, MARCH 2008 TABLE I SPECIFICATION OF THE ISO/IEC TYPE C AND MOBILE UHF RFID carrier leakage. The focus of the design is on the linearity rather than the noise figure. Typically, passive UHF RFID tags need to have an input power of dbm (100 ) [5]. The minimum output power at the reader antenna should be greater than 20 dbm with the consideration of the link loss in air of 31 db for 1 m communication range, the tag antenna gain of 2 dbi, and the embedded reader antenna gain of 0 dbi. Typically, the output power of the tag modulator is greater than 30 dbm (1 ). With the link budget analysis, the minimum received power is calculated as 60 dbm. Including the loss of the directional coupler, the minimum RF sensitivity of 70 dbm is required in the UHF band mobile RFID application. The receiver noise floor depends on the cascade noise figure as well as on the noise bandwidth. Then the sensitivity can be calculated as follows: Fig. 1. Single-antenna RFID reader operation. short range compared with other fixed UHF RFID reader systems since it is for mobile phone application. In the return link of the RFID operation, the receiver of the reader listens to the response of the tag (transponder) while the transmitter sends a continuous wave (CW) to the tag for power transfer. One of the most critical components is how to reject a leakage signal from the transmitter to the receiver. Conventionally, an RFID reader module contains two antennas with sufficient spacing because the isolation from transmitter to receiver is much better in a two-antenna reader than in a single-antenna reader. However, it is not suitable for the mobile phone reader system, due to the physical dimension and the high cost [1]. Fig. 1 shows the single-antenna RFID reader operation for the return link of the tag to the reader communication. In a single-antenna reader system, the backscattered desired signal returning from the tag is mixed with the transmitter carrier. The amount of the transmitter carrier leakage, which is typically more than 0 dbm at the receiver input, is determined by the antenna reflection coefficient and the isolation of the directional coupler. The transmitter carrier leakage leads to the saturation of receiver block and degradation of the sensitivity. Hence, the P1dB characteristic needs to be high in the receiver front-end to avoid the receiver saturation caused by the large transmitter The noise bandwidth of the receiver under consideration is about 120 khz for 40 kb/s data rate. The required sensitivity is 70 dbm. Assuming that there is a minimum signal-to-noise ratio of 11.6 db for 0.001% BER [4], the receiver noise floor should be less than 81.6 dbm. For the required sensitivity, the maximum allowable noise figure is calculated from (1) as 39 db. For the maximum output power of 27 dbm, the maximum transmitter carrier leakage is calculated as 5 dbm. The transmitter carrier leakage is determined by the antenna reflection coefficient and the isolation of the directional coupler. The transmitter leakage power reflected from the antenna with a reflection of 15 db and coupling loss of 10 db is about 2 dbm at the maximum output power. The CW leakage power due to the limited isolation performance of the directional coupler is about 2 dbm for the 25 db isolation. To cope with large in-band blocker of transmitter leakage signal, the authors specify a required P1dB of 5 dbm. The input IP3 (IIP3) needs to be greater than 15 dbm considering IIP3 is about 10 db higher than input P1dB. The radio specification for mobile RFID reader requires 18 db rejection at the adjacent channel 200 khz and 47 db rejection at the alternate channel 400 khz, respectively, in the condition of dense reader environment [4]. In the condition of multiple reader environments, the 5 db rejection at the adjacent channel and 35 db rejection at the alternate channel are specified. The analog-to-digital converter (ADC) budget finally determines the required receiver selectivity. To limit any interferer to 0 db above the desired channel at the ADC, an adjacent channel 200 khz rejection of 20 db and alternate channel 400 khz rejection of 50 db are specified, including a margin. In a wireless receiver based on the down-conversion scheme, an undesired signal located at adjacent channel will be down-converted to the desired channel due to the close-in phase noise of frequency synthesizer. This phenomenon is called the reciprocal mixing and depends on the phase noise performance of the frequency synthesizer, the adjacent channel spacing, and system noise bandwidth (the amount of the noise

3 KWON et al.: A SINGLE-CHIP CMOS TRANSCEIVER FOR UHF MOBILE RFID READER 731 Fig. 2. Block diagram of the single-chip mobile RFID reader. being integrated at the adjacent channel). In the UHF mobile RFID reader, 20 db adjacent channel selectivity and 50 db alternate channel selectivity are required. This indicates that after down-conversion, an adjacent channel signal of higher than 20 db over the desired signal and an alternate channel signal of higher than 50 db over the desired signal should fall in a power level lower as than that of the desired channel, guaranteeing the required 0.001% BER for signal detection [4]. Assuming and noise bandwidth of 120 khz, the frequency synthesizer phase noise at 200 khz offset (where the adjacent channel is allocated) and 400 khz offset (where the alternate channel is allocated) can be calculated as follows: where is the magnitude of the blocker and is the magnitude of the desired carrier. A phase noise of 83.4 dbc/hz at 200 khz offset and dbc/hz at 400 khz offset are derived for the required channel selectivity. The in-band phase noise at data frequency band is also to be considered. However, the phase noise of the CW leakage is correlated with LO phase noise and it is down-converted to DC. A DC offset cancellation circuit then rejects the DC noise. Therefore, the phase noise overlap with the data frequency band is relaxed. III. TRANSCEIVER ARCHITECTURE Fig. 2 illustrates the block diagram of the single-chip RFID reader, which integrates an RF transceiver, data converters, a digital baseband modem, an MPU, memory, and host interfaces. Baseband modulator and demodulator are implemented in hardware logic. Most of the other digital functionalities are implemented in software to support multi-protocols and flexibility. The external power amplifier and directional coupler are used for high power transmission and isolation. The designed UHF mobile RFID reader supports ISO/IEC type C and type B with software multi-protocol support. Fig. 3 illustrates the receiver architecture of the RF transceiver. Among the various receiver architectures, the direct conversion receiver is adopted due to the backscattering communication solution. In the direct conversion receiver architecture, the transmitter carrier leakage to the receiver input is directly Fig. 3. Receiver architecture. Fig. 4. Transmitter architecture. down-converted to DC. It can be removed by the DC offset cancellation (DCOC) feedback loop. However, the large transmitter carrier leakage leads to the saturation of the receiver RF front-end block. Hence, the low-noise amplifier (LNA) is bypassed in the backscatter detection mode for high P1dB characteristics to cope with very large transmitter carrier leakage. The transmitter is implemented in the direct up-conversion architecture as illustrated in Fig. 4. Baseband signals are transmitted to digital-to-analog converters (DACs) followed by the low-pass filters. Two identical mixers up-convert the baseband quadrature signals directly to the 900 MHz band, which is combined by current summing at the output. The transmitter supports both the SSB and the DSB modulation for the reader-to-tag communications and sends an unmodulated carrier for the tag-to-reader communications. In the DSB-ASK transmission, baseband signal is tied zero. In the SSB-ASK transmission, baseband signal is generated by the Hilbert transformer from the baseband signal. For generating 900 MHz LO signals with 200 and 500 khz channel spacing, a frequency synthesizer based on a fractional-n phase-locked loop (PLL) derived from a 19.2 MHz crystal is implemented. A 1.8 GHz LO signal is generated by an integrated voltage-controlled oscillator (VCO) in the PLL and then the 900 MHz differential LO signals are obtained by a divide-by-two circuit. The conventional digital baseband receiver based on matched filter estimation has certain advantages that lead correlation gain by integrating the received signal over the symbol period while averaging out the zero-mean additive white Gaussian noise (AWGN). It is effective when there is only AWGN in the noise component. When considering other noise components such as DC offset, SNR is seriously decreased if there is correlation gain between an impulse response of the matched filter and DC offset.

4 732 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 3, MARCH 2008 Fig. 6. Receiver RF front-end configuration of the reader. Fig. 5. (a) Digital baseband receiver architecture. (b) Transition filter characteristic compared to matched filter. (c) BER simulation result. The proposed digital baseband receiver is designed based on transition detection with windowing correlation as shown in Fig. 5(a). The receiver consists of three parts: a transition filter, a threshold comparator, and a transition-to-symbol converter. The transition filter estimates a transition component of a received signal and it determines whether transition occurred or not. The transition filter calculates the correlation between the received signal and the transition reference signal as follows: where. The transition filter maximizes the transition component of an input signal and the DC offset component is suppressed as shown in Fig. 5(b). As a result, it is robust to DC offset from transmitter leakage than conventional digital baseband receiver based on matched filter. Fig. 5(c) illustrates BER simulation result. The 1000 bits FM0 coded tag responses were received 100 times. The BER of the matched filter is superior to the transition filter in absence of the DC offset. However, DC offset severely degrades the performance of the matched filter as illustrated in Fig. 5(c) while the transition filter shows good immunity. IV. CIRCUIT DESIGN A. Receiver The RF front-end block supports the listen-before-talk (LBT) function to avoid RFID reader collision. The reader collision (3) Fig. 7. Receiver LNA schematic. phenomenon occurs when more than two mobile RFID readers attempt to use the same frequency channel. During the LBT function, the reader receiver detects the CW signal of the other reader while the transmitter is off. Fig. 6 illustrates the reader RF front-end configuration according to the mode selection. In the normal mode operation, the antenna is connected to the directional coupler followed by quadrature down-conversion mixer with bypassing LNA. To cope with very large transmitter carrier leakage, the LNA can be bypassed in the normal mode operation. In the LBT mode, the antenna is connected to the LNA followed by a down-conversion mixer without the directional coupler. Without the transmitter leakage, the RX LNA can be used to improve noise figure rather than linearity. The cascode feedback LNA with a complementary transconductance stage as illustrated in Fig. 7 is used for better tradeoff between noise performance and linearity at low power consumption. The total current consumption of the LNA is 2.4 ma with 1.8 V supply. The designed LNA has a gain of 15 db, noise figure of 2.9 db, and P1dB of 15 dbm. The linearity of the conventional Gilbert cell mixer is not satisfactory mainly because of the transconductance nonlinearity, which becomes more serious, especially at lower bias current. High linearity of the receiver front-end is achieved by using the CMOS passive switching mixer, as illustrated in Fig. 8. Its linearity is excellent because the passive FET switches are very

5 KWON et al.: A SINGLE-CHIP CMOS TRANSCEIVER FOR UHF MOBILE RFID READER 733 Fig. 8. Receiver down-conversion mixer schematic. Fig. 9. Analog baseband filter-amplifier chain. Fig. 10. (a) PGA schematic. (b) Low-pass filter schematic. linear due to the low impedance and no transconductance nonlinearity. The input P1dB of the mixer is high enough for linear operation of the mixer. The DC offset at the mixer output is cancelled by the DC offset canceller with current cancellation at the input of the next stage. The flicker noise of the CMOS mixer is a critical problem to the direct conversion receiver architecture. The passive switching mixer has very low 1/f noise because there is no DC current through the switching stage [6]. The analog baseband filter-amplifier chain is depicted in Fig. 9, which interleaves low-pass filter stages with programmable gain amplifiers (PGAs). This allows better tradeoffs between noise figure and linearity for each stage. In this design, a sixth-order Butterworth low-pass filter is used. It has variable bandwidth using a 5-bit capacitor bank. The gain of the PGA in decibels changes linearly with a resolution of 1 db and control range of 63 db by the digitally controlled 6-bit switches. The circuit schematics of the PGA and low-pass filter are depicted in Fig. 10(a) and (b), respectively. Active RC implementations of low-pass filters and opamp-based PGAs are used for good linearity performance. The active RC filter is very linear due to the linear passive component and high gain opamps. Thus, it is suitable for this design due to the high linearity performance compared to other approachs such as gm-c filters. The gain control is realized by the digital gain control. Active RC implementations of second-order biquad low-pass filters are also used for the good linearity performance. In the baseband analog parts, the DCOC loop is used as illustrated in Fig. 11. The DC offset is mainly achieved from the DC of the transmitter carrier leakage. The local DC feedback loop is used for the DCOC circuit implemented with the gm-c integrator. A local DC feedback loop for each gain stage has the advantage of high DC offset rejection, compared to the global servo loop. Fig. 11. DC offset cancellation (DCOC) loop. The output of the mixer is applied to the first baseband amplifier-filter stage through input resistor of 40. The DC offset feedback loop senses the DC offset components at the output of the each analog baseband amplifier-filter stage. The output of the DC offset canceller adjusts the current through a feedback resistor of 40 and the DC offset at the input of the amplifier-filter is cancelled by current cancellation. To keep the constant high-pass corner frequency at different gain setting, a programmable gain is used in the feedback integrator. The time constant of the DC offset canceller is smaller than the required transmit-to-receiver (TX-to-RX) turnaround time. During tag reception, the link timing requirement is defined for TX-to-RX turnaround time which is the time from tag response to reader transmission. The reader-to-tag link uses pulse interval encoding (PIE). is the reference time interval for a data-0 in reader-to-tag signaling, and is the duration of a data-0. Readers communicate using values in the range of s. Fora value of s, the maximum specification of the TX-to-RX turnaround time is s. For the designed reader, the TX-to-RX turnaround time is smaller than 125 s including the time constant of the DC offset canceller. From the noise simulation of the analog baseband chain, the

6 734 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 3, MARCH 2008 Fig. 13. Transmitter drive amplifier schematic. Fig. 12. (a) Transmitter DC level shifter schematic. (b) Transmitter up-conversion mixer schematic. input-referred noise voltage is slightly increased at the low-frequency band due to the use of DCOC. Nevertheless, the inputreferred integrated noise voltage in the signal bandwidth is increased from 13.8 to 14.9 and the increment is less than 8% in simulation. B. Transmitter The transmitter chain consists of low-pass filters, a variable gain amplifier, an up-conversion mixer, and a drive amplifier. The DAC output current signals, which have many undesired out-of-band signals appearing near the multiple of the sampling frequency, are low-pass filtered and amplified by the gain stage of the DC level shifter. A Butterworth second-order low-pass filter is adopted to minimize in-band group delay ripple and to satisfy spectrum mask. Fig. 12(a) presents the transmitter DC level shifter schematic. The level shifter functions as the DC level conversion as well as variable gain amplifier. The gain control is realized by switching the resistors of the opamp-based amplifier. The level shifter is used in each quadrature signal input in order to set the correct input common-mode voltage and drive the subsequent up-conversion mixer. The level shifter converts the input common-mode voltage of 0.4 V to output common-mode voltage of 0.9 V. Fig. 12(b) depicts the transmitter up-conversion mixer. In the up-conversion mixer, baseband signals are up-converted to 900 MHz and added together. The source degeneration transconductance cells are used for linearity performance to satisfy the transmitter spectrum mask. An active load is used for the up-conversion mixer output to reduce the chip area. The output is added together by current summing with active output load. For supporting both SSB and DSB modulation, baseband signal can be switched. Fig. 13 depicts the schematic of drive amplifier. The drive amplifier is a cascode type with an external RF inductor load of 10 nh. The cascode configuration is used for better isolation between input and output stage and the reduction of the Miller effect onto the input impedance. The drive amplifier operates as class AB amplifier. The maximum output power of the drive amplifier is 4 dbm and the power can be controlled digitally by switching the transconductance of the parallel array of the input transistor using a 3-bit gate bias control with a control range of 13 db. For the 3 db step gain control, the ratio of the transconductance N1, N2, and N3 is 1, 1.4, and 2, respectively. The external power amplifier is used for maximum output power greater than 20 dbm. C. Frequency Synthesizer A frequency synthesizer based on a fractional-n PLL is designed as depicted in Fig. 14. The synthesizer is implemented for UHF RFID band in Korea and USA, which have 200 khz and 500 khz channel spacing, respectively. The reference oscillator for the frequency synthesizer is built-in on-chip and uses a 19.2 MHz off-chip crystal. The clock is divided by three with a reference divider to create the reference for the phase-frequency detector (PFD). The output signal of the PFD drives a charge pump whose bias current is regulated with a bandgap reference. The charge pump output is filtered by loop filter and applied to the VCO. An 8/9 dual modulus prescaler, PS counters, and the third-order sigma-delta modulator are used in the feedback path in the PLL. A 1.8 GHz LO signal is generated by an integrated VCO in the PLL and then the 900 MHz differential LO signals are obtained by a divide-by-two circuit. Fig. 15(a) illustrates the VCO schematic. In the VCO, pmos and nmos cross-coupled pairs are used for symmetry with a differential on-chip inductor in the tank circuit [7]. In order to reduce up-conversion of the flicker noise, a pmos transistor is used for the tail current source and a large capacitor is used

7 KWON et al.: A SINGLE-CHIP CMOS TRANSCEIVER FOR UHF MOBILE RFID READER 735 Fig. 14. Frequency synthesizer architecture. Fig. 16. Chip microphotograph. Fig. 15. (a) VCO schematic. (b) LO buffer schematic. in shunt with the current source transistor. The 3-bit capacitor array switch is used for tuning the oscillation frequency. The schematic in Fig. 15(b) illustrates the LO buffer used to drive the down-conversion and up-conversion mixers. The differential CMOS inverter-type LO buffer with the self-biasing by feedback resistor and common current source is proposed. It has the advantages of low output impedance and large differential LO signal swing due to push-pull operation. A divide-by-two circuit consists of two D-latches in a negative feedback loop. The D-latch is designed by using current-mode logic suitable for high-frequency operation with low power consumption. The resistive output loads are used in the divide-by-two circuit. The loop bandwidth of the PLL is set by adjusting external resistors and capacitors. The loop bandwidth of the PLL loop is set to around 30 khz with 188 pf, 6.6 k, 3.9 pf, 13 k, and 5.7 pf. V. EXPERIMENTAL RESULTS Fig. 16 depicts the microphotograph of the single-chip RFID reader IC, fabricated in the 0.18 m six-metal CMOS process. The single-chip reader integrates a RF transceiver, data converters, a digital baseband modem, an MPU, memory, and host interfaces. The die area of the single-chip transceiver is 4.5 mm 5.3 mm with the RF transceiver area of 2.5 mm 4.0 mm including electrostatic discharge (ESD) I/O pads. The measured input return loss of the receiver in both LBT and normal mode is presented in Fig. 17(a). The input matching in the normal mode is worse than LBT mode because the matching gain need to be decreased to increase input P1dB performance. The noise figure of the receiver chain versus output frequency is depicted in Fig. 17(b). The measured noise figure of the receiver chain is about 39 db at the normal mode operation and 29 db at the LBT mode operation, respectively. The receiver has almost 1/f noise-free characteristics as illustrated in Fig. 17(b) due to the use of passive switching mixer for down-conversion. The receiver sensitivity at the 0.001% BER is about 70 dbm for the 40 kb/s data rate with FM0 modulation. The receiver front-end P1dB of 8 dbm is measured at the normal mode operation. The receiver front-end P1dB of dbm is measured at the LBT mode operation. The measured IIP3 and IIP2 of the receiver front-end are 18.5 dbm and 43 dbm, respectively. Linearity is significantly improved by using the passive switching mixer. The linearity performance is sufficient for the mobile RFID reader application. The frequency response characteristic of the receiver chain is illustrated in Fig. 18(a). The 3 db bandwidth can be controlled by the bandwidth mode setting for different channel bandwidth. The measured bandwidth is khz controlled by a 5-bit capacitor bank control. The filter frequency characteristics imply that the adjacent and alternate channel rejection is achieved as 40 and 76 db, respectively. Fig. 18(b) depicts the measured receiver gain and high-pass cutoff frequency with the digital gain control. The gain of the receiver changes linearly with a resolution of 1 db and control range of 63 db by the digitally controlled 6-bit switch. The high-

8 736 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 3, MARCH 2008 Fig. 17. (a) Measured receiver input return loss (S ). (b) Measured noise figure of the receiver chain. Fig. 18. (a) Measured frequency response of receiver chain. (b) Measured receiver chain gain and high-pass cutoff frequency with the gain control. pass corner frequency is almost constant with the receiver PGA gain control. The measured TX-to-RX turnaround time is 108 s for s. This is smaller than the required TX-to-RX turnaround time. Fig. 19 presents the phase noise of the frequency synthesizer measured at the transmitter output. The frequency synthesizer achieves the phase noise of 100 dbc/hz at 200 khz offset and 120 dbc/hz at 1 MHz offset. The loop bandwidth of the PLL loop is set to around 30 khz and the settling time of the synthesizer is less than 40 s. Fig. 20 illustrates the measured output spectrum of the transmitter with the input signal of DSB-ASK modulation and s. The output power from the drive amplifier is 4 dbm and the output of the external power amplifier is 26 dbm. The spectrum at the transmitter output satisfies the required spectrum mask in the multiple-reader environment condition of the ISO type C standard as shown in Fig. 19. The measured transmitter output power control range is from 9 to 4 dbm with 1 db steps and the maximum output power is 4 dbm at 31 ma current consumption. The measured sideband image rejection ratio with the SSB modulation is 32 dbc. Fig. 21 depicts the measured reading distance with the transmitter output power. The reading distance denotes the communication range between reader and tag and that the reader can read the tag data with the required SNR. In this measurement, it is limited by the reader sensitivity. For the measurement, ISO type C tag and a single antenna of 0.5 dbi gain Fig. 19. Measured frequency synthesizer phase noise. are used. External power amplifier is integrated on the application board for the transmitter output power. The reading distance of 1 m at the output power of 26 dbm is achieved as presented in Fig. 21. The measured performances of the fabricated reader are summarized in Table II. The RF transceiver consumes 4 ma in the receiver chain, 31 ma in the transmitter chain, and 26 ma in the frequency synthesizer with 1.8 V supply. The external

9 KWON et al.: A SINGLE-CHIP CMOS TRANSCEIVER FOR UHF MOBILE RFID READER 737 VI. CONCLUSION A single-chip UHF RFID reader for mobile phone applications has been implemented in a 0.18 m CMOS technology. It integrates an RF transceiver, data converters, a digital baseband modem, an MPU, memory, and host interfaces and its die area is 4.5 mm 5.3 mm including ESD I/O pads. The reader consumes a total current of 89 ma except external power amplifier with the 1.8 V supply voltage. The direct conversion RF transceiver architecture with the highly linear RF front-end circuit and DCOC circuit is used. It is suitable for the mobile phone reader with single-antenna architecture and low-power reader solution. Fig. 20. Fig. 21. Measured transmitter output spectrum. Measured reading distance with ISO type C tag. TABLE II MEASURED PERFORMANCE SUMMARY ACKNOWLEDGMENT The authors would like to thank W. Kang, J. Koo, and S. Koo for their contributions. REFERENCES [1] K. Finkenzeller, RFID Handbook, Radio-Frequency Identification Fundamentals and Applications, 2nd ed. New York: Wiley, [2] Radio-Frequency Identification for Item Management Part 6: Parameters for Air Interface Communications at 860 MHz to 960 MHz. ISO/IEC :2004/FPDAM 1, [3] Class 1 Generation 2 UHF Air Interface Protocol Standard Version EPCglobal Inc., 2005 [Online]. Available: [4] Standard on Radio Specification for Mobile RFID Reader, MRFS-5-01-R1 [Online]. Available: http// [5] U. Karthaus and M. Fischer, Fully integrated passive UHF RFID transponder IC with 16.7 m minimum RF input power, IEEE J. Solid-State Circuits, vol. 38, no. 10, pp , Oct [6] S. Zhou and M. F. Chang, A CMOS passive mixer with low flicker noise for low-power direct-conversion receiver, IEEE J. Solid-State Circuits, vol. 40, no. 5, pp , May [7] S. Levantino, C. Samori, A. Bonfanti, S. L. J. Gierkink, A. L. Lacaita, and V. Boccuzzi, Frequency dependence on bias current in 5-GHz CMOS VCOs: Impact on tuning range and flicker noise upconversion, IEEE J. Solid-State Circuits, vol. 37, no. 8, pp , Aug [8] I. Kwon, H. Bang, K. Choi, S. Jeon, S. Jung, D. Lee, Y. Eo, H. Lee, and B. Chung, A single-chip CMOS transceiver for UHF mobile RFID reader, in IEEE ISSCC Dig. Tech. Papers, 2007, pp Ickjin Kwon (S 00 M 05) received the B.S., M.S., and Ph.D. degrees in electrical engineering and computer science from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 1998, 2000, and 2004, respectively. From 2004 to 2008, he was a Senior Research Engineer with Samsung Advanced Institute of Technology (SAIT), Yongin, Korea, where his research focus was on CMOS RF/Analog integrated circuit and RF transceiver design for wireless communication. In 2008, he joined the Division of Electrical and Computer Engineering, College of Information Technology, Ajou University, Suwon, Korea, whereheiscurrentlyanassistant Professor. Hisresearchinterests include CMOS RF/analog/mixed-signal integrated circuit and transceiver design. power amplifier delivering 27 dbm consumes 355 ma with 3.5 V supply and has power-added efficiency (PAE) of 40%. Yunseong Eo received the B.S., M.S., and Ph.D. degrees from Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 1993, 1995, and 2001, respectively. From 2000, he was with LG Electronics Institute of Technology, Seoul, Korea, where he was involved in designing the RFICs such as VCO, LNA, and PA using InGaP HBT devices. He also worked on the development of 6 18 GHz wideband switch and power modules for EW application. In 2002, he joined Samsung Advanced Institute of Technology, Yongin, Korea, where he has worked on designing the 5 GHz CMOS power amplifiers and transmitter circuits. Since 2005, he has been an Assistant Professor of electronics engineering at Kwangwoon University, Seoul, Korea,

10 738 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 3, MARCH 2008 where his research focus is on CMOS RFIC and transceivers. His research interests include high linear and efficient CMOS power amplifiers, linear transmitter circuit design, and fully integrated RF CMOS transceivers. Heemun Bang was born in Seoul, Korea, in He received the B.S. and M.S. degrees in electronics engineering from Sogang University, Seoul, Korea, in 1999 and 2001, respectively, focusing high-speed circuits in optical electronics. In 2001, he joined Samsung Advanced Institute of Technology, Yongin, Korea, where he has been working on mixed-signal analog circuit design for wireless application. Kyudon Choi received the B.S. degree from Korea University, Seoul, Korea, in 2003, and the M.S. degree in electrical engineering and computer science from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in He is currently an RF and Mixed Signal Circuit Designer with the Samsung Advanced Institute of Technology, Gyeonggi, Korea. His research interests include CMOS RF/mixed-mode IC and RF system design for communication. Sangyoon Jeon received the B.S. and M.S. degrees in electronic material and device engineering from Inha University, Incheon, Korea, in 1998 and 2000, respectively. His research was mainly focused on the modeling of high-frequency devices. Currently, he is with Samsung Advanced Institute of Technology, Yongin, Korea, where he works on CMOS analog/rf integrated circuit design. Sungjae Jung was born in Jeonju, Korea, in He received the B.S. and M.S. degrees in electronics engineering from Chung-Ang University, Seoul, Korea, in 2000 and 2002, respectively. After graduation, he joined the RFIC R&D Group at the Samsung Advanced Institute of Technology (SAIT), Yongin, Korea. His current research interests include the design of analog baseband circuits in communication systems, especially for wireless communications. Donghyun Lee (M 05) received the B.S. and M.S. degrees in electrical and electronic engineering from Ajou University, Suwon, Korea, in 2003 and 2005, respectively. Since 2005, he has been with Samsung Advanced Institute of Technology, Yongin, Korea. His research interests are wireless CMOS Analog/RF/MM-wave integrated circuit design. Heungbae Lee received the B.S. degree in electronic and communication engineering from Hanyang University, Seoul, Korea, in 1988, and the M.S. degree in electronics engineering from Korea University, Seoul, Korea, in From 1988 to 2001, he worked at Samsung Electronics, Suwon, Korea, on analog/rf integrated circuit design. He joined Samsung Advanced Institute of Technology, Yongin, Korea, in His current research includes CMOS analog/rf integrated circuit design and high-speed links.