FA 8.1: A 115mW CMOS GPS Receiver

Transcription

1 FA 8.1: A 115mW CMOS GPS Receiver D. Shaeffer, A. Shahani, S.S. Mohan, H. Samavati, H. Rategh M. Hershenson, M. Xu, C.P. Yue, D. Eddleman, and T.H. Lee Stanford University

2 OVERVIEW GPS Overview Architecture Circuits Experimental Results Summary

3 GPS OVERVIEW: TYPICAL RECEIVER ARCHITECTURES Dual-Conversion Distinguishing Features: 2 Typical on-chip P D is 100mW 500mW Off-Chip PLL - OR - 1 Off-chip LNA or active antenna Single-Conversion Off-chip IF filtering 2 1 or 2 bit quantization PLL Off-Chip

4 GPS OVERVIEW: SIGNAL STRUCTURE C/A code is a BPSK, D.S. spread-spectrum signal. T c = 1çs, T b = 20ms. ç ç Tb G Large = 10 log processing gain. T p c = 43dB Important fact: SNR ç 0 db at antenna! (P R ç -130dBm) Thermal Noise Floor Subsequent image rejection suppresses this sideband MHz MHz -8 MHz -2 MHz 2 MHz 8 MHz 12 MHz IF Downconvert Channel Filter ~ 20dB (Tr = 290K) GPS C/A Code GPS P-Code RF MHz MHz GHz

5 ARCHITECTURE: LOW-IF RECEIVER Primary Goal: Make choices to minimize P D, maximize integration. Low-IF è On-chip active channel filter GHz 2.036MHz I[n] Image in GPS band è Relaxed I/Q matching. Eliminate PLL prescaler Saves power / noise. è Band Gap PLL π/2 APD Q[n] Signal Path M*f0 (M=17) 1-bit quantization for simplicity. N*M*f0 = GHz APD f0=4.024mhz N*f0 (N=23)

6 A: ç IQ ètè = sgn ësinè2!tèë ARCHITECTURE: WEAVER IMAGE REJECTION Question: Can we use 1-bit quantization in an image-reject architecture? Key: Show that summing the two output channels yields 3dB improvement. I A B I n(t) + - B: ç IQ ètè = 0 I/Q channels are de-correlated after the lowpass filter! Q Q Answer: Yes, if the noise has equal sidebands and SNR ç 0 db. (As in GPS.)

7 CIRCUITS: LNA/MIXER LNA Mixer Measured LNA Noise Figure LOp LOm 3.0 Vb IFA Noise Figure (db) NF = 1575MHz Ibias = 4.9mA RFp RFm 2.2 Ibias Frequency (MHz) Shahani, Shaeffer and Lee, A 12mW Wide Dynamic Range CMOS GPS Receiver, ISSCC 1997

8 CIRCUITS: IFA Low input capacitance, high linearity. Simulated IFA Voltage Gain Load resistors terminate the active filter input. Ibias Ibias Outp M2 M1 Inp Inm Outm Voltage Gain (db) M4 M DC Input Voltage (V)

9 CIRCUITS: GM-C FILTER (ARCHITECTURE) Design based on a 5th-order L-C elliptical prototype. The dynamic-range limiting block in the system. IFA Gm-C Filter (LC Ladder Prototype) Gm Gy Gy Gy Gy Replica Bias Circuit Gyrators (2 Transconductors, ea.)

10 CIRCUITS: GM-C FILTER (DESIGN APPROACH) The filter is the most critical signal path element, and therefore requires the most attention to detail. Some relevant ideas: Interesting fact: F min = 2 è1 + Nè. Independent of filter Z 0! This implies a fixed amount of power gain to suppress filter noise. Fixed G P è A V è p Z 0. Need to Z minimize 0 to maximize dynamic-range. Seek linearization techniques that maximize G m =I bias. One sub-optimal approach would be linearization by degeneration. Use Class-AB techniques, if possible, to maximize power efficiency. In short: It all depends on the transconductor!

11 CIRCUITS: GM-C FILTER (TRANSCONDUCTOR) Use two square-law transconductors to build a linear, class-ab transconductor. A little positive feedback (M10) compensates for mobility degradation in M1. M Simulated Gyrator Transconductance M5 Ibias 1.05 With Positive FB (M10) Without Positive FB +/- 10% M10 Variation Outp Inp M1 M2 M6 Inm Outm Relative Gm DC Input Voltage (V)

12 CIRCUITS: PLL OVERVIEW A research goal: Explore techniques that reduce PLL power consumption. Maximize Q of spiral inductors in RF section. Use patterned ground shields (PGS). (Also aids isolation.) è C.Yue and S. Wong, On-chip spiral inductors with patterned ground shields for Si-based RF IC s, VLSI Symposium, 1997 Prescaler consumes a large amount of power, and generates noise. Eliminate prescaler by only doing phase comparisons during periodic è apertures positioned around reference edges. This saves power and reduces switching noise. Accomplished with an Aperture Phase Detector (APD).

13 CIRCUITS: APERTURE PHASE DETECTOR (APD) Aperture opens when pre-charge period ends. FFE1 LOin ApertureTiming Diagram Delay Aperture closes when the first edge arrives, discharging the circuit. REFin FFE2 LOin D Aperture Closes (Implicitly) t FFE3 Delay U Aperture Opens Phase Error Delayed Reference Problem: Loop can lock to any harmonic of reference!

14 CIRCUITS: PLL ARCHITECTURE An interesting idea: With dual APDs, the loop should lock to the least-common harmonic of the two references. PLL Architecture Works in theory, if APD detects frequency. Problem in practice: APD only detects phase. Acquisition problem. è f1=n*f0 f2=m*f0 Example: N=5, M=3 N*M*f0 I Q Better solution: Use acquisition aid plus APD. frf=15*f0 f1=5*f0 f2=3*f0 1 period of f0 Apertures

15 EXPERIMENTAL RESULTS: FREQUENCY RESPONSE Signal Path Frequency Response Frequency Response (db) Passband Detail I Channel Q Channel Simulated Frequency (MHz)

16 EXPERIMENTAL RESULTS: NOISE FIGURE 12.0 Coherent Receiver Spot Noise Figure (Pre-Limiter) Fine Quantization 1-bit Quantization Noise Figure (db) IF Frequency (MHz)

17 EXPERIMENTAL RESULTS: LINEARITY 40 Signal Path 3rd Order Intermodulation Output Voltage (dbvrms) Slope= Input Power (dbm)

18 EXPERIMENTAL RESULTS: BLOCKING PERFORMANCE -20 Receiver 1-dB Blocking De-Sensitization (No Front-End RF Filter) Blocking Source Power (dbm) INMARSAT Uplink Band Offset Frequency (MHz)

19 EXPERIMENTAL RESULTS: PLL SPURIOUS 10 0 PLL Spurious Relative Power (dbc) f1 f2 f1-f2 INMARSAT Uplink Frequency (MHz)

20 EXPERIMENTAL RESULTS: PLL PHASE NOISE -90 PLL Phase Noise Noise Power Density (dbc/hz) HP8664A PLL HP8780A Offset Frequency (Hz)

21 EXPERIMENTAL RESULTS: OUTPUT SPECTRUM 0 Receiver Output Spectrum (Pre-Correlation) Magnitude (dbfs) HP8664A Spur Frequency (MHz)

22 EXPERIMENTAL RESULTS: CODE CORRELATION Normalized Cross-Correlation Magnitude Non-Coherent Receiver Output Gold Code Cross-Correlation SNR = 15dB Code Phase

23 PERFORMANCE SUMMARY Signal Path Performance PLL Performance ç ç ( P s LNA Noise Figure 2.4dB Loop Bandwidth 5MHz LNA S11-15dB Spurious Tones -42dBc Coherent Receiver NF 4.1dB VCO Tuning Range 240MHz 7.6%) IIP3 (Filter-limited) -43dBm VCO Gain Constant 240MHz/V é Peak SFDR 57dB LO LNA -53dBm Filter Cutoff Freq. 3.5MHz ç Filter PB Peaking 1dB Power/Technology Filter SB Atten. 8MHz Signal Path 79mW 10MHz PLL / VCO 36mW G p v A p 11.2mm G 2 v A ç Pre-Filter 19dB Supply Voltage 2.5V Pre-Filter 32dB Total 82dB Die Area Total 107dB Technology 0.5çm CMOS Non-Coherent Output SNR 15dB

24 ACKNOWLEDGMENTS Rockwell International Dr. Christopher Hull Dr. Paramjit Singh Tektronix, Inc. Ernie McReynolds Defense Advanced Research Projects Agency