Analog and RF circuit techniques in nanometer CMOS

Transcription

1 Analog and RF circuit techniques in nanometer CMOS Bram Nauta University of Twente The Netherlands UNIVERSITY OF TWENTE.

2 Outline Introduction Balun-LNA-Mixer (BLIXER) Interferer robust SDR RX analog part Interferer robust SDR RX digital part Summary

3 Preferred: one wide band frontend IC: Software Defined ω LO ω LO Keep minimal 3

4 4 RF system trend (I) Challenges wide band circuits: Minimal pre-filtering: No high Q tanks: high linearity low noise Bandwidth will be ok for low GHz Towards Software Defined Radio

5 Outline Introduction Balun-LNA-Mixer (BLIXER) Interferer robust SDR RX analog part Interferer robust SDR RX digital part Summary

6 BLIXER Balun + LNA + Mixer [Blaakmeer, ISSCC2008] 6

7 BLIXER=Wide band receiver ω LO ω LO 7

8 Balun-LNA R S v s + v in - CG + v out - I Bias CS Simultaneous: Single-to-Differential Balanced Gain Broadband input match ( ~1/g mcg ) Noise Canceling Distortion Canceling [Blaakmeer et al. ESSCIRC `07] 8

9 Noise Canceling 200Ω 50Ω 50Ω v s 20mS + v in - I bias i n 80mS 9

10 Bandwidth problem: 200Ω 50Ω C < 80fF for BW=10GHz 20mS 50Ω v s + v in - I bias 80mS 10

11 So, Don t make voltage RF 200Ω 50Ω 20mS 50Ω v s + v in - I bias 80mS 11

12 Use a MIXER 200Ω 50Ω 20mS 50Ω v s + v in - I bias 80mS 12

13 4 Z Z Now Low frequency LO g m Low-Z 4 g m RF: no high-z nodes R S v s I Bias 13

14 Mixer stacked on CG-CS stage 4 Z IF+ LO+ W Z 4 W R 3 R 3 C C IF- LO- v s R S + v rf - CG g m v rf CS 4 g m v rf [Blaakmeer, ISSCC 08] 14

15 Chip Micrograph and PCB detail OSC OSC IN IF Out L bias 1.4 mm IN LO gen + buf Core + IF-buf Biasing IF I+ IF I- IF Q+ Baseline 65nm CMOS 1.2V supply IF Q- Active area < 0.02 mm 2 Supply & Biasing 15

16 Conversion Gain, NF and S G C [db] 0-10 NF S 11 f IF = 50 MHz 1 7GHZ 10 RX-frequency [GHz] 16

17 Other BLIXER Performance Linearity: RF: -3 dbm RF: +20 dbm Quadrature accuracy: Phase error < 3 Gain error < 1dB LO leakage < -50 dbm Dissipation 33mW (LO=500MHz) 57mW (LO=7GHz) 17

18 Outline Introduction Balun-LNA-Mixer (BLIXER) Interferer robust SDR RX analog part Interferer robust SDR RX digital part Summary

19 A Software-Defined Radio Receiver Architecture Robust to Out-of-Band Interference [Ru, ISSCC 2009]

20 ω LO ω LO 20

21 Conventional Multi-Band Receiver Antenna Switches 850M 900M 1800M 1900M LNA LNA LNA LPF LPF IFA IFA LNA! 0/90 LO Chip RF filters for out-of-band interference, but bulky, costly, lossy, inflexible Our goal: Software Defined Radio with relaxed RF filtering 21

22 Wideband Interfering: Nonlinearity Wideband Gain=20dB A B C LNA 0.8G 2.4G dBm -40dBm -70dBm +10dBm -20dBm -50dBm 0.8G 1.6G 2.4G Wanted Interference 0.8G 1.6G 2.4G 3.2G Intermodulation & blocking Wideband LNA: also amplifies interference à nonlinearity 22

23 Wideband Interfering: Harmonic Mixing Wideband Gain=20dB A B C LNA 0.8G 2.4G dBm -40dBm -50dBm -20dBm -30dBm -50dBm 0.8G 2.4G Wanted 3 rd harmonic 0.8G 2.4G DC Switching mixer: square-wave LO à harmonic mixing 23

24 Concept: Use LP Filtering for Selectivity Low Gain, Low Pain. LNA 1 st node with voltage gain LPF RF A B C V-I I-V 50Ω LO Baseband (BB) Voltage gain only at BB after low-pass filter (LPF) to filter blockers à Keep low impedance over a wide band at node B 24

25 Realization: Wideband LNTA + Mixer + TIA V-I LPF & I-V Impedance A B D C RF LNTA OTA 50Ω LO +R mixer LO f DC f BB LNTA: high G m & high R out à low noise small voltage swing at node B à good linearity Similar to [1], but now wideband and with blocker filtering [1] Redman-White & Leenaerts, ESSCIRC07 25

26 Harmonic Rejection (HR) Mixer: Remove 3LO and 5LO RF LO1 BB Þ LO1 LO2 x1 x 2 1 st or 7 th : add up! harmonic LO2 LO3 x1 1 Û 1 45 LO3 Þ 3 rd or 5 th harmonic : cancel! 1 RF 1 BB Effective LO Amplitude weighting + phase shifting à emulate sine-lo [2] Weldon et. al., ISSCC01 26

27 Problem: Amplitude and Phase Errors 3 rd or 5 th harmonic vector diagram Amplitude Error residue 2(1+α) Δφ Phase Error residue 2 Amplitude and phase errors à unwanted harmonic residue à degrade HR ratio How to make irrational ratio, e.g. 2, on chip? 27

28 2-Stage Polyphase HR: Concept st Stage 2 nd Stage x2 2 x3 3 x5 x x2 x3 x x x2 x3 x x5 41/29=1.4138, 2= à ε=0.03% 28

29 2-Stage Polyphase HR: Realization 50Ω RF Ω LNTA 2G m 3G m 2G m I - + Q - RF LNTA for 1 st -stage weighting (2:3:2) BB resistor for 2 nd -stage weighting (5:7:5) Nominally 2, what about influence of mismatch? 29

30 Reduced Effect of Amplitude Mismatch 1 st harmonic (desired signal) 3 rd or 5 th harmonic 1 st stage (error α in 2) (1+α) 2α 2(2+α) ratio α 2 2(1+α) 2 nd stage (error β in 2) 2(2+α) (2+α) 1 2α (2+α) 2(1+β) 2αβ 2(2+α)(2+β) ratio α 2 β 2 2α 2(1+β) 2α 1 2-stage polyphase à product of relative errors E.g. 2:3:2 à α=6% à 1 st -stage only: HR3=40dB 5:7:5 à β=1% à 2-stage total: HR3=86dB 30

31 RF Filtering is Relaxed! RF 50Ω 2:3:2 HR Mixer 7 LNTA OTA 5 7 OTA BB PXF (db) RF to BB Periodic Transfer Funciton (PXF) 17dB DC LO 3LO 5LO 7LO f LP blocker filtering: attenuates interference around LO 2-stage polyphase HR: robustly attenuates 3LO and 5LO 31

32 Zero-IF Receiver Prototype Chip TIA1 R-net 7 50Ω RF Ω LNTA 2G m 3G m 2G m Mixer TIA I - + Q - CLK Ω 8 8 Clock

33 Chip Photo 1mm2 in 65nm CMOS VDD: 1.2V Current consumption: Analog 33mA Digital 17mA 33

34 Measured HR: 40 Chips HR 0.8G LO HR Ratio (db) th 3rd Min. HR5=64dB Min. HR3=60dB Sample # No trimming & calibration, no RF filtering 34

35 Measured Performance Summary LO Frequency Gain DSB NF S 11 < -10dB 0.4~0.9GHz 34.4±0.2dB 4dB±0.5dB 80M~5.5GHz In/Out-of-band IIP3 1 +3dBm / +18dBm In/Out-of-band +46dBm / IIP dBm IF Bandwidth 12MHz 1/f noise 30kHz corner VDD 1.2V Current Consumption Analog: 33mA Digital (clock): 0.4GHz 0.9GHz Harmonic Rejection 0.8GHz LO 3 rd -order > 60dB (40 chips) 5 th -order > 64dB (40 chips) 2 nd, 4 th, 6 th > 62dB (20 chips) 1 Out-of-band IIP3: two tones = 1.61G & 2.40GHz, LO = 819MHz 2 Out-of-band IIP2: two tones = 1.80G & 2.40GHz, LO = 601MHz 35

36 Conclusion: A SDR Receiver Architecture Robust to Out-of-Band Interference Only voltage BB after low-pass filtering In-band IIP3 +3dBm & out-of-band IIP3 +18dBm 2-stage polyphase harmonic rejection technique Robust: error = product of errors Accurate multiphase clock Minimum HR 60dB over 40 chips without calibration / trimming / RF filters 36

37 Outline Introduction Balun-LNA-Mixer (BLIXER) Interferer robust SDR RX analog part Interferer robust SDR RX digital part Summary

38 The Digital approach: Harmonic Rejection Exploiting Adaptive Interference Cancellation [Moseley, ISSCC 2009] 38

39 Harmonic Rejection RX: This work Chip ADC x 0 50Ω RF Ω 2Gm 3Gm ADC ADC x 45 x 90 To Digital Harmonic Rejection Algorithm (Baseband processor) 2Gm CLK Ω ADC x

40 The Basic Idea Subtract interference (residual harmonic image responses) from received signal. Desired Signal + Interference Interference Estimate d(n) v(n) - e(n) Desired Signal Need interference estimate signal. 40

41 Adaptive Interference Cancelling (AIC) Desired Signal + Interference Interference Estimate r(n) v(n) Digital Filter y(n) - e(n) Desired Signal Filter Coefficients w(n) Learning Algorithm Adaptive filter aligns phase & amplitude. Minimizes cross-correlation v(n) and e(n). 41

42 Two I/Q signals Chip ADC x 0 r(n) = x 0 + j x 90 2Gm 50Ω ADC x 45 RF + - 3Gm 50Ω ADC x 90 2Gm CLK Ω ADC x 135 IQ 2 (n) = x 45 + j x

43 Desired signal Interference estimate r(n) IQ2 IQ 2 v(n)=r(n)-iq 2 3 rd harmonic response r(n) IQ2 IQ 2 v(n)=r(n)-iq 2 5 th harmonic response r(n) IQ2 IQ 2 v(n)=r(n)-iq 2 43

44 AIC Algorithm 1/5 RF Input A N AL O G F R O NT x 0 x 45 x 90 ADC ADC ADC j IQ1-45 IQ2 v(n) r(n) - - (.)* e(n) To Rest of Baseband Processing E N D x 135 ADC j w 1 * w 2 * LMS update Adaptive Interference Canceller Master Clock 44

45 AIC Algorithm 2/5 RF Input A N AL O G F R O NT x 0 x 45 x 90 ADC ADC ADC j IQ1-45 IQ2 v(n) r(n) - - (.)* e(n) To Rest of Baseband Processing E N D x 135 ADC j w 1 * w 2 * LMS update Adaptive Interference Canceller Master Clock 45

46 AIC Algorithm 3/5 RF Input A N AL O G F R O NT x 0 x 45 x 90 ADC ADC ADC j IQ1-45 IQ2 v(n) r(n) - - (.)* e(n) To Rest of Baseband Processing E N D x 135 ADC j w 1 * w 2 * LMS update Adaptive Interference Canceller Master Clock 46

47 AIC Algorithm 4/5 RF Input A N AL O G F R O NT x 0 x 45 x 90 ADC ADC ADC j IQ1-45 IQ2 v(n) r(n) - - (.)* e(n) To Rest of Baseband Processing E N D x 135 ADC j w 1 * w 2 * LMS update Adaptive Interference Canceller Master Clock 47

48 AIC Algorithm 5/5 RF Input A N AL O G F R O NT x 0 x 45 x 90 ADC ADC ADC j IQ1-45 IQ2 v(n) r(n) - - (.)* e(n) To Rest of Baseband Processing E N D x 135 ADC j w 1 * w 2 * LMS update Adaptive Interference Canceller Master Clock 48

49 Demonstration 49

50 Demonstration 50

51 Demonstration 51

52 Demonstration 52

53 Demonstration 53

54 Comparison This work Z. Ru ISSCC Rej. strongest >80 db (1) >60 db Rej. other odd >36 db >60 db Rej. even >64 db >62 db Power frontend V (excl. ADCs) V (excl. ADCs) Power DSP < V N/A (100 Msps) (simulated) # ADCs 4 / 2 if AIC off 2 (1) If one harmonic interference image band is dominating. 54

55 Adaptive Interference Cancellation: Conclusions Dual-domain Harmonic Rejection Mixer (HRM) proposed: Analog HRM + 4 ADCs + Digital AIC. Strongest correlating harmonic image is removed X-correlation -> independent of signal shape. Stronger interferer -> more rejection Measurements: First stage (analog) HR > 36 db. Dual domain HR3 or HR5 > 80 db. Limitation: even-order HR > 64 db. 55

56 Outline Introduction Balun-LNA-Mixer (BLIXER) Interferer robust SDR RX analog part Interferer robust SDR RX digital part Summary

57 57 Summary BLIXER Noise cancelling no voltage RF Interferer robust RX No voltage RF Filter before voltage gain HR: error of errors

58 58 Summary Digital Harmonic Rejection RX Adaptively kills the biggest harmonic interferer