Digitally Assisted Radio Evolution DARE
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1 Digitally Assisted Radio Evolution DARE Pietro Andreani Department of Electrical and Information Technology Lund University, Sweden
2 The DARE Concept Focus on 4G radio receiver and frequency generation
3 Notable Results - LNAs and front-ends - Channel-select filters - A/D converters - VCOs, TDCs, PLLs - Digital base-band - Channel estimation - MIMO decoder - Linearity enhancement
4 Research Team,
5 LTE Receiver Front-End I Anders Nejdel A Noise Cancelling GHz Resistive-Feedback Receiver Front-End in 65 nm CMOS Feedback phase can be tuned for complex Z s Programmable g m RFIC 2014 JSSC 2015
6 LTE Receiver Front-End II Anders Nejdel Mixer-first receiver front-end with positive feedback Increase input impedance at f LO R f used to control loop gain to match input RFIC 2015
7 Frequency Compensation Technique for OTAs Mohammed Abdulaziz 5 th order active-rc Chebyshev filter requires very fast OTAs RFIC 2013 TCAS-II 2014
8 RX Front-End with Blocker Sensing Mohammed Abdulaziz Noinse Canceling LNTA + RF LNA -Gm2 NC-LNTA ON/OFF -Gm1 LO_I LO_Q 2 + LO - TIA TIA -f Low Resolution Baseband Spectrum Analyzer f I+ I- Q+ Q- Architecture of the Spectrum Analyzer -f f R 1 R 2 ( ) OTA OTA + High Q Tunable Fourth order Complex Band Pass filter Power Detector Low Pass Filter Rlarge 2xRlarge Fine tuning in resistors R 1, R 2 Second order Low pass filter RFIC 2016
9 Mohammed Abdulaziz A Blocker-Tolerant Front-End Improved gain compression and NF vs. blocker unpublished
10 Digitally-Assisted Linearity Improvement in CSF Rakesh Gangarajaiah Mohammed Abdulaziz Xilinx FPGA TCAS-II 2016
11 LTE Receiver Front-End III Xiaodong Liu Anders Nejdel RX front-end with A/D-converting CSF ESSCIRC 2015 JSSC 2016 Front-end A/D-converting channel-select filter
12 Demonstrator of Complete RX Xiaodong Liu Rakesh G. Michal Stala Anders Nejdel From antenna to constellation!
13 A Power-Reconfigurable DCO Luca Fanori Ibias 4 N-only ON Vdd P-N ON Ibias M3 Vdd N-only ON Vdd Vdd M4 N-only ON P-N ON N-only ON -90 Fine Tuning DCO Calibration Coarse Tuning <0:11> M1 Vout C fine M2 Phase Noise (dbc/hz) <0:2> C cal -160 f LO = 3.92GHz Configuration P-N (Ibias = 6mA ) Configuration N-only (Ibias = 24mA) FoM = 185.6dBc/Hz FoM = 185dBc/Hz dBc/Hz dBc/Hz Notch due to measurement setup 1,00E+05 1,00E+06 1,00E+07 Frequency Offset (Hz) ISSCC 2012
14 A GHz CMOS Class-D VCO Luca Fanori STM 65nm CMOS ISSCC 2013 JSSC 2014
15 GHz double-core VCO Luca Fanori STM 65nm CMOS ISSCC 2014
16 GHz reconfigurable VCO Luca Fanori Ahmed Mahmoud Phase noise DS-mode, I DC = 4 ma Phase noise SS-mode, I DC = 8 ma DS SS SS SS DS SS STM 28nm UTBB FD-SOI CMOS RFIC 2015 Springer 2016
17 A 90nm CMOS Gated-Ring- Oscillator-Based Vernier TDC Ping Lu Combines Vernier TDC and gated-ring-oscillator TDC High Vernier time resolution + First-order noise shaping ESSCIRC 2011 JSSC 2012
18 2 A 2.2ps 2-D Gated-Vernier TDC Ping Lu (τ2=(k-1)δ=17δ) FGRO 2 2 DIGITAL DECODER start stop PD EN_Y EN_X y 51Δ 34Δ 17Δ -33Δ -15Δ -16Δ Δ 2Δ 19Δ SGRO 3Δ 20Δ 37Δ 18Δ 36Δ 54Δ (τ 1 =kδ=18δ) x DIGITAL DELAY CALIBRATION /2 CLK (960ns) /2 EN counter EN counter 1 st order shaping of delay quantization ENB Σ Σ IN EN OUT 2C <0> <1> <7> 128C addr + 1 addr + 1 0? y y 0? n n LUP addr - 1 addr ? y y 255? n n Keep addr Keep addr default addr STM 65nm CMOS RFIC 2013 TCAS-II 2016
19 2 Digital PLL with 2-D TDC Ping Lu Ahmed Mahmoud p1 p6 p2 p y 9-stage 153Δ 51Δ 34Δ 17Δ 2-D GVTDC -99Δ 9Δ -33Δ -15Δ 3Δ 111Δ -16Δ 2Δ 20Δ 128Δ Δ 19Δ 37Δ 145Δ Cancellation α β Digital Loop Filter IIR λ DCO outp M I M osc core outm M I M 18Δ 36Δ 54Δ 162Δ x EN_F EN_S REF Divider /2 or /4 50MHz N frac MASH-3 ΔΣ Modulator 3.5GHz~5GHz Decode Class-D DCO STM 65nm CMOS Springer 2016
20 To DTC Digital PLL with DTC Ahmed Mahmoud Federico Pepe ndco REF 40MHz D Q e Bandwidth Regulation Digital Filter DCO dco outp M I M osc core outm M I M Digital Algorithms Digital DTC div Integer Divider N/N+1 Predistorter q Nint 3GHz~4GHz Decode γ Coeff0 Nfrac e γ γ γ Coeff124 0 Coeff380 Coeff Coeffi Predistorter Nfrac s Quantizer Ndiv + Nint X s g0 g124 g256 g380 g511 g i=coeff i+1-coeff i Coeff0 Coeff124 0 Coeff380 Coeff511 Class-D DCO STM 65nm CMOS under fabrication
21 Improved phase noise analysis of harmonic oscillators Federico Pepe Asymmetry between inductive and capacitive losses Phase noise caused by capacitive losses may be much higher TCAS-II 2016
22 General phase noise analysis of harmonic oscillators Federico Pepe General phase noise equation TCAS-I 2017
23 Rakesh Gangarajaiah Adaptive QR Matrix Decomposition for LTE-A MIMO STM 28nm UTBB FD-SOI CMOS with forward body bias (FBB) unpublished
24 Tunable LDPC Decoder Algorithm Muris Sarajlić LDPC = low-density parity-check 5 12 % additional complexity savings with adaptation to channel conditions PIMRC 2014 PIMRC 2015
25 IP2 Improvement Muris Sarajlić On-the-fly algorithm for IP2 calibration in frequency mixer Ongoing work: comparison of calibration vs compensation in digital baseband unpublished
26 DFT-Based Channel Estimators for OFDM Michal Stala original DFT channel estimator Reduced #bits new DFT channel estimator only the difference is processed SiPS 2014
27 CSF Reconfiguration in Analog BB Michal Stala Two CSFs: high-performance and low-performance CSF lo CSF hi ADC H Blocker Detection Control Block H (digital) compensates the phase distortion occurring when switching between the two CSFs unpublished
28 Company spin-off: MISTBASE Michal Stala MISTBASE founded in June 2015 by: Michal Stala (DARE PhD Student) Magnus Midholt Lund University Innovation Systems (LUIS) Modem development for cellular IoT NB-IoT LTH/EIT collaboration through internships and Master s theses Currently: 10 employees 6 Master s thesis students Partners: ARM and NextG-Com (more coming soon!)
29 Conclusions DARE has produced a large amount of excellent results
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