Digital PWM IC Control Technology and Issues

Transcription

1 Digital PWM IC Control Technology and Issues Prof. Seth R. Sanders Angel V. Peterchev Jinwen Xiao Jianhui Zhang Department of EECS University of California, Berkeley

2 Digital Control Advantages implement advanced control schemes multi-mode control (high/low power modes) adaptive algorithms spread-spectrum switching for EMI reduction flexibility and programmability integrate supervisory functions - fault detection, management, and reporting communicate with other digital devices - voltage scaling immunity to analog component variations and noise largely automated digital design flow 2

3 Analog PWM Controller Block Diagram V ref PID control power train z 2 Σ z 1 V D comp + V x V in V x V out = DV in 0 DT T 3 + V ramp T V D V ramp +

4 Digital PWM Controller Block Diagram online parameter optimization V x D c discrete values V in V x V out = DV in 4 0 DT T

5 Quantization Resolution Issues Microprocessor VRM example V in V out ΔV dpwm N dpwm 12 V 1 V 5 mv 11 bits IC Digital PWM (DPWM) implementation with f sw = 1 MHz requires 2 11 x 1 MHz = 2 GHz clk in counter-comp. scheme 2 11 = 2048 stages in a ring-oscillator-mux scheme Analogous requirement on A/D sampling process 5

6 Voltage Regulation Loop ΔV adc = V in / 2 Nadc ΔV dpwm = V in / 2 Ndpwm Two quantizers in feedback loop: ADC & DPWM Possible limit cycling (steady state oscillations < f sw ) 6

7 Limit cycling Limit cycling undesirable hard to predict amplitude and frequency V out noise electro-magnetic interference (EMI) Look for conditions preventing limit cycles 7

8 Resolution (ADC) > Resolution (DPWM) V out 1 LSB error bin limit cycling in steady state 0 error bin transient DPWM levels ADC levels -1 LSB error bin 8

9 Resolution (DPWM) > Resolution (ADC) (integral term is used in control law) no limit cycling in steady state V out 1 LSB error bin 0 error bin transient -1 LSB error bin DPWM levels ADC levels 9

10 Integral Control and Limit Cycling Simulation results PD control PID control V in = 5 V, V ref = 1.5 V, f sw = 250 khz, N dpwm = 10 bit, N adc = 9 bit 10

11 Closed-loop Stability resolution (DPWM) > resolution (ADC) assume ADC quantization non-linearity dominant Nyquist Stability Criterion: 1 + N(A)L(jω) 0 ADC describing function 1.27 loop transmission (low-pass) Gain peaking can cause sustained limit cycle 11

12 No-Limit-Cycle Guidelines 1. Resolution (DPWM) > Resolution (ADC) 2. Integral control is used 3. Closed-loop system is asymptotically stable in usual sense 4. Limit cycles ruled out by describing function analysis 12

13 Digital Dither - Motivation Microprocessor VRM example V in V out ΔV dpwm N dpwm 12 V 1 V 5 mv 11 bits IC DPWM implementation with f sw = 1 MHz requires 2 11 x 1 MHz = 2 GHz clk in counter-comp. scheme 2 11 = 2048 stages in a ring-oscillator-mux scheme Digital dither can increase effective resolution of DPWM module by M bits by periodically modulating duty cycle over 2 M switching cycles and using filtering action of power train 13

14 Digital Dither (1-bit) 14

15 Digital Dither (2-bit) 15

16 Dither Generation from Control Law to DPWM module 16

17 Dither Ripple Dither produces V out ripple at f < f sw Large dither ripple undesirable poor V out regulation electro-magnetic interference (EMI) can couple to feedback loop > limit cycling 17

18 Dither Bit Limit Estimate of number of dither bits (M) which can be used w/o incurring limit cycling for f c < f dith < f z for f c < f z < f dith Microprocessor VRM example N adc 10 bits N dpwm,eff 11 bits f sw 1 MHz f c 7.3 khz f z 200 khz M 4-5 bits 2 5 IC clock speed or area savings e.g mm 2 vs mm 2 ring-osc-mux DPWM 18

19 Dither and Limit Cycling Experimental results time (ms) N dpwm = 7 bit hardware N adc = 9 bit time (ms) N dpwm = 7 bit + 3 bit dither N adc = 9 bit V in = 5 V, V ref = 1.5 V, f sw = 250 khz 19 Vout (V)

20 Extension: Multi-phase Dither Multi-phase buck converter 4 phases switched 360 º / 4 = 90 º out of phase 20

21 Multi-phase Dither DPWM resolution increase of log 2 N φ bits in N φ - phase converter Further lower DPWM hardware resolution requirement 21

22 Prototype VRM Step Response Simulation Experiment I out = 11 A I out = 1 A I out = 11 A I out = 1 A V in V ref N Φ f sw N adc N dpwm 5 V 1.5 V khz 9 bits 7 bits + 3 bits dither 22

23 CMOS Hardware Ckt Cell: DPWM I bias VDD 32-tap Differential Ring DT s T s D 5-bit MUX PWM 5 Ring-MUX scheme 5-bit DPWM hardware + 5-bit digital dither 1 μa at 600 khz PFM sampling frequency 23

24 Ring Oscillator with Subthreshold Bias Linear dependency of ring-oscillator frequency on bias current VDD I bias 7.0E E E E+06 Frequency (Hz) 3.0E+06 4.E-07 5.E-07 6.E-07 7.E-07 8.E-07 9.E-07 Current-starved 4- stage differential ring oscillator Bias Current (A) 24

25 ADC Considerations differential ADC > quantizes error signal (V out -V ref ) ADC bin size ~ 5 mv (for microprocessor VRM) only a few bins (~ 10) around V ref need be quantized low latency < 100 ns (fast VRM response) 25

26 PWM Mode Ring-ADC Architecture V o VDD Analog Block V ref M Counter Counter Σ Digital Block D e M Counter Σ f 1 f 2 VSS ΔV ΔI Δf De Windowed quantization range Insensitive to switching noise Digital block synthesizable Counter Automatic monotonicity Wide Vo operating range 16 mv/step, 80 mv window, 0.15mm 2 on 0.25 μm CMOS, μa at 500KHz 26

27 Online Parameter Optimization Digital controllers can perform complex computations Ideal for adaptive control applications Online optimization can improve performance by adjusting controller parameters to minimize a cost function (power loss, input current, temperature, etc.) 27

28 Multi-parameter Extremum Seeking Control gradient estim. gradient descent x1 f / x 1 f / x n x n perturbations u 1 Σ u n Σ x 1 x n f (x 1,,x n ) cost function converter 28

29 Buck Converter Switch Timing control switch synchronous rectifier PID control T eff T on 29

30 Continuous Conduction Mode at Light Load Efficient operation over wide load range critical to battery life in mobile applications Below about 10 A microprocessor current, instantaneous inductor current may assume negative values control switch synch. rectifier inductor current microproc. current 0 Contributes power loss 30

31 Discontinuous Conduction Mode at Light Load Turn synch. rectifier off when inductor current crosses zero Higher efficiency control switch synch. rectifier inductor current microproc. current 0 31

32 Discontinuous Conduction Mode at Light Load Existing adaptive methods for synch. rect. control use highbandwidth sensing of power MOSFET gate and drain voltage [Stratakos 1994, Acker 1995, Lau 1997] We propose synch. rect. control based on low-bandwidth loss-minimizing algorithm Directly minimizes power loss Suitable for digital implementation Does not require A-to-D sampling rate > switch. freq. 32

33 control switch PID control synchronous rectifier T eff T on adaptive powerminimization control Multi-mode Control variable switching frequency control switch synchronous rectifier Discontinuous Conduction Mode Continuous 33

34 Synchronous Rectifier Timing Adaptation Synch. rect. timing as function of load current is adjusted to minimize power loss 34

35 Synch. Rect. Turn-on Timing 35

36 Synch. Rect. Turn-off Timing (heavy load) 36

37 Synch. Rect. Turn-off Timing (light load) 37

38 Synch. Rect. Turn-off Timing (light load) cont. cond. mode discont. cond. mode local minimum due to resonant switching 38

39 Synch. Rect. Turn-off Timing (light load) cont. cond. mode discont. cond. mode synch. rect. on local minimum due to resonant switching force synch. rect. off 39 synch. rect. off

40 Dither Bit Limit Dither produces undesirable ripple on V out Limit ripple to less than ΔV adc Microprocessor VRM example N adc 10 bits N dpwm,eff 11 bits f sw 1 MHz f c 7.3 khz f z 200 khz M 5 bits 2 5 IC clock speed or area savings e.g mm 2 vs mm 2 ring-osc-mux DPWM 40

41 Prototype VRM Step Response Simulation I out = 11 A I out = 1 A Experiment I out = 11 A I out = 1 A V in V ref N Φ f sw N adc N dpwm 5 V 1.5 V khz 9 bits 7 bits + 3 bits dither 41