3. DAC Architectures and CMOS Circuits

Transcription

1 1/30 3. DAC Architectures and CMOS Circuits Francesc Serra Graells Departament de Microelectrònica i Sistemes Electrònics Universitat Autònoma de Barcelona paco.serra@imb-cnm.csic.es Integrated Circuits and Systems IMB-CNM(CSIC)

2 2/30 1 DAC Classification 2 Flash Techniques 3 Pulse-Width Modulation Techniques 4 Delta-Sigma Modulation Techniques

3 3/30 1 DAC Classification 2 Flash Techniques 3 Pulse-Width Modulation Techniques 4 Delta-Sigma Modulation Techniques

4 4/30 DAC Families Classification based on architecture approach: High speed Digital signal Analog signal Parallel Flash code DAC voltage/current amplitude Digital timebase Algorithmic Predictive PWM Delta-Sigma Distinctive characteristics: Feedforward vs feedback control Single vs multiple stages Amplitude vs time domains...and many more! Typically mixed solutions... High dynamic range

5 5/30 DAC vs ADC Design Asymmetrical system architecture and signal purpose: sensor e.g. microphone pre amp AGC/ limiter anti alias ADC core decimator information action clock generator DSP M DAC core interpolator actuator e.g. motor power amp reconstruction...typically ADC is more performance demanding!

6 6/30 1 DAC Classification 2 Flash Techniques 3 Pulse-Width Modulation Techniques 4 Delta-Sigma Modulation Techniques

7 7/30 Basic Flash Architecture DAC All parallel and segmented (unitary) resistive ladder: e.g. 32x32-1 e.g. single-ended 10-bit flash DAC

8 8/30 Basic Flash Architecture DAC All parallel and segmented (unitary) resistive ladder: e.g. 32x32-1 e.g. single-ended 10-bit flash DAC

9 9/30 Basic Flash Architecture DAC All parallel and segmented (unitary) resistive ladder: natural binary code 10 (MSB) 5 5 (LSB) 5-to-32 Digital decoder e.g. 32x32-1 e.g. single-ended 10-bit flash DAC 5-to-32 Non-constant output impedance

10 10/30 Basic Flash Architecture DAC All parallel and segmented (unitary) resistive ladder: natural binary code 10 (MSB) 5 5 (LSB) 5-to-32 Digital decoder e.g. 32x32-1 e.g. single-ended 10-bit flash DAC 5-to-32 Distortion due to switch on-resistance variability

11 11/30 Switch Optimization DAC Thermometric switched-resistor flash DAC: natural binary code Thermometric encoder current source/sink like

12 12/30 Switch Optimization DAC Thermometric switched-resistor flash DAC: natural binary code Thermometric encoder current source/sink like Switch non-linearity minimized thanks to its signal independent bias point Poor scalability with ENOB

13 13/30 CMOS Circuits Thermometric switched-current (SI) fully differential flash DAC: natural binary code Thermometric encoder continuous-time waveform! Always-on Si cell to reduce output voltage glitches Return-to-zero (RTZ) digital signaling minimizes inter-symbol interference waveform asymmetry time time

14 14/30 CMOS Circuits Thermometric switched-current (SI) fully differential flash DAC: natural binary code Thermometric encoder continuous-time waveform! Always-on Si cell to reduce output voltage glitches Return-to-zero (RTZ) digital signaling minimizes inter-symbol interference Poor scalability with ENOB Power and area overheads (x2) time Full-scale reduction due to RTZ duty cycle

15 15/30 CMOS Circuits Thermometric SI fully differential flash DAC: SI CMOS modular cell: Thermometric encoder M5i M6i M7i M8i M3i M4i M2i MOSFET noise contributions! Good linearity thanks to... OpAmp virtual ground + M1i cascode topologies

16 16/30 Coarse-Fine Architectures Mixed segmented (coarse) and binary weighted (fine) solutions: e.g. 8-bit coarse-fine single-ended SI flash DAC compact layout and simple digital control 5-bit (LSB) 3-bit (MSB) Therm. encoder 7 Unlike in ADC counterparts, it is still single step! Good ENOB scalability smooth transitions

17 17/30 1 DAC Classification 2 Flash Techniques 3 Pulse-Width Modulation Techniques 4 Delta-Sigma Modulation Techniques

18 18/30 Digital Pulse Width Modulation DAC Discrete amplitude and continuous-time domains: input buffer Register ALU continuous-time reconstruction filter >=? Counter Power driver time

19 19/30 Digital Pulse Width Modulation DAC Discrete amplitude and continuous-time domains: input buffer Register ALU continuous-time reconstruction filter >=? Counter Power driver Ouptut actuator can be reused as reconstruction filter: Overclocking Output filter selectivity Energy close to f s time e.g. Class-D audio driver

20 20/30 Digital Pulse Width Modulation Discrete amplitude and continuous-time domains: input buffer Register ALU continuous-time reconstruction filter >=? Counter Power driver Overclocking Relaxing output filter selectivity by employing non-monotonic counters (e.g. LFSR, flipped...) Energy close to f s time Energy close to f clk time

21 21/30 Dual-Ramp Analog Integration Continuous-amplitude and continuous-time domains: Register Coarse PDM MSB 8 >=? Counter LSB 8 Register >=? Fine PDM e.g. 16-bit dual ramp DAC time

22 22/30 Dual-Ramp Analog Integration Continuous-amplitude and continuous-time domains: Register Coarse PDM MSB 8 >=? Counter LSB 8 Register >=? Fine PDM Relaxing output filter selectivity Strong reduction of clock speed requirements Coarse-fine matching e.g. 16-bit dual ramp DAC time

23 23/30 1 DAC Classification 2 Flash Techniques 3 Pulse-Width Modulation Techniques 4 Delta-Sigma Modulation Techniques

24 24/30 Analog vs Digital DSM gain coefficient integrator quantizer S/H high-pass filter (quantization noise shaping)

25 25/30 Analog vs Digital DSM DAC gain coefficient integrator quantizer S/H high-pass filter (quantization noise shaping) bit-shifting (2 +/-k gain coefficient) full-adder truncation register register flash output DAC discrete time domain already Flash output DAC with reduced number of levels Possibility of loop instability for N>2

26 26/30 Multi-Stage Noise Shaping (MASH) flash output DAC Cancellation filter Cascade of 1st-order DSM Forward digital cancellation Intrinsically stable

27 27/30 Multi-Stage Noise Shaping (MASH) Cancellation filter Differentiator Delay

28 28/30 Multi-Stage Noise Shaping (MASH) Cancellation filter Differentiator Each DSM cancels quantization errors of previous one Delay Not suitable for ADC DSM due to possible cancellation mismatching N-order noise shaping

29 29/30 Multi-Stage Noise Shaping (MASH) Example for 1-bit quantization 1st-order DSM stage: Compact solution: Adder Carry Register

30 30/30 Multi-Stage Noise Shaping (MASH) Example for 1-bit quantization 1st-order DSM stage: Compact solution: Carry Adder Register Register Register Register Register Register Cancellation filter