Lecture-44. EE5325 Power Management Integrated Circuits

Transcription

1 ecture-44 EE5325 Power Management Integrated Circuits Dr. Qadeer Ahmad Khan Integrated Circuits and Systems Group Department of Electrical Engineering IIT Madras DC-DC Converter Wish ist High Power Density Higher efficiency to reduce heat dissipation Smaller passive components to reduce board space Shrinking die size by innovative controller and integrating more features on single PMIC Source:Vishay Stable Supply High performance controller design Output Voltage oad Current ± 5% Time 2

2 Technology Trends in PMIC Scaling semiconductor process technology Higher speed Power FETs Smaller Size 0.5µm 0.35µm 0.8µm ow parasitic packaging technologies (WP, BGA) Smaller Parasitic DIP SOP QFN WP 3 PMIC vs Passive Size PMIC Power Management Module Passive Components (Inductors and Capacitors) Source: TechInsights Inc. Samsung Galaxy S8 External Passive components ( and C) occupy 2/3 rd of the total power module size 4 2

3 Passive Size Reduction Output ripple is a function of inductor (), capacitor (C) and switching frequency (FSW) Doubling switching frequency reduces passive components by 4x for the same output ripple VSW VO ΔVO I VO CO Output Ripple: VO Source: Micrel FSW=MHz FSW=4MHz PMIC PMIC 2 FSW PMIC FSW=8MHz Increasing FSW 5 imitations of Analog Controller PID Compensator Analog PWM VRAMP Area/power inefficient VIN Voltage-to-Time Conversion MP VPWM Gate Driver VSW Error Amplifier (EA) VO CO MN C VCTR R CD EA RD VREF Type-III (PID) Compensator Bandwidth limits transient response Ramp Generator imits switching frequency PWM Comparator Delay limits output range 6 3

4 imitations of Analog Controller Voltage-to-Time Conversion V RAMP Analog PWM V CTR C Gate Driver R EA V SW MP MN C D R D Type-III (PID) Compensator PID Compensator Area/power inefficient Error Amplifier (EA) Bandwidth limits transient response Ramp Generator imits switching frequency PWM Comparator Delay limits output range Significant power penalty at high F SW 7 Digital Controller Design Challenges Digital-to-Time Conversion DC[M:0] DPWM CK Digital PWM - z - Gate Driver Kp Ki Kd MP V SW MN DE[N:0] ADC V e + - Small controller area at low Fsw Non-linear loop dynamics Steady state is a bounded limit cycle large ripple ADC res. > reg. accuracy 0.% accuracy 0bit DPWM res. inverter delay arge area and power - -z PID Compensator F CK >> F SW 8 4

5 Digital Controller Design Challenges Digital-to-Time Conversion DC[M:0] DPWM CK Digital PWM - z - Gate Driver Kp Ki Kd MP V SW MN DE[N:0] ADC V e + - Small controller area at low Fsw Non-linear loop dynamics Steady state is a bounded limit cycle large ripple ADC res. > reg. accuracy 0.% accuracy 0bit DPWM res. inverter delay arge area and power - -z PID Compensator F CK >> F SW Significant power & area penalty at high F SW 9 Time Based Controlled DC-DC Converter Vin - V e Time Domain Voltage-to-Time Processing Conversion + f PWM Gate Driver V SW SP SN Voltage is directly converted into Time Processing is done in Time Domain Since resultant output is Time, it doesn t require any PWM modulator Preserves benefits of both analog (low power, high accuracy) and digital (process scaling, low voltage operation, area efficient) without using any A/D or error amplifier Implicit PWM generation Eliminates PWM modulator hence minimum delay 0 5

6 Time Based Controlled DC-DC Converter Power and area efficient Vin - V e Time Domain Voltage-to-Time Processing Conversion + f PWM Gate Driver V SW SP SN Voltage is directly converted into Time Processing is done in Time Domain Since resultant output is Time, it doesn t require any PWM modulator Preserves benefits of both analog (low power, high accuracy) and digital (process scaling, low voltage operation, area efficient) without using any A/D or error amplifier Implicit PWM generation Eliminates PWM modulator hence minimum delay VCO as Time-based Integrator OUT H VCO (s) ω OUT = K VCO VCO ω OUT = d OUT dt ω UGB = K VCO K VCO H VCO s = OUT(s) s = K VCO s Frequency VCO acts as an ideal V-to-Φ integrator 2 6

7 VCO Behavior in Time Domain V-to- CK VCO -to-d D OUT VCO CK REF DOUT CKREF = K VCO 0 t τ dτ D OUT = D OUT CKREF 2π D OUT = K VCO 2π 0 t τ dτ CK REF CK VCO D OUT 3 Example of Phase Accumulation f o =0MHz (free running frequency of VCO) Or ω o = 2π 0MHz K VCO =2πMrad/s/V V-to- CKVCO -to-d D OUT Then phase difference will become 2π every 0 th cycle of the clock VCO CK REF Phase difference becomes 2π 4 7

8 Opamp-RC vs Time Based Integrator Voltage Based Integrator Input voltage is integrated as voltage Integral Gain = /RC Time Based Integrator Input voltage is integrated as phase (time) by VCO Integral Gain = K VCO R C UT VCO VCO CKCTR CKREF PWM ow-pass Filter UT VIN VREF CKCTR f > f REF ; f 2 < f REF f f 2 f UT CKREF PWM f REF VOUT 5 Buck w/ Time-based Type-I Controller FVCO CTR REF REF CTR T ON T OFF T ON RVCO 2π 6 8

9 Time Based PID Controller Need 3 functions to realize time based PID compensator:. Time based Integrator VCO 2. Time based Proportional (Gain)? 3. Time based Differentiator? 7 Time-based Proportional Control CK REF VCD OUT H VCD (s) K VCD Frequency VCD acts as an ideal V-to-Φ converter 8 9

10 Time-based Differentiator C D V D R D OUT H DIFF (s) CK REF VCD K VCD R D C D Frequency H.P. filter + VCD acts as an ideal V-to-Φ differentiator 9 Buck Converter with T-PID Controller C D R D FVCO VCD VCD2 Φ I Φ I +Φ P Φ I +Φ P +Φ D I P D Φ CTR Φ REF RVCO Integral gain K VCO of FVCO Proportional gain K VCD of VCD Derivative gain R D C D and K VCD of VCD

11 Mapping V-PID to T-PID () C 2 C R 2 R V C T R E A V R E F C 3 R 3 V F B PID Compensator Ignoring w p and simplifying 2 Mapping V-PID to T-PID () C 2 C R 2 R V C T R E A V R E F C 3 R 3 V F B PID Compensator Ignoring w p and simplifying Proportional Integral Derivative 22

12 Mapping V-PID to T-PID (2) V FB VCO C D R D VCD VCD 2 CTR 23 T-PID Transfer Function + - V e + H TPID(s) TPID Compensator K VCD K VCO s K R C s ɸ VCD2 D D D (s) R C s D D ɸ P (s) P ɸ I (s) I D ɸ CTR (s) 2 Phase Detector Driver V SW V H C (s) O C Filter H TPID (s) -20dB/dec Gain +20dB/dec 0dB wp PM RD CD 0 Phase -90 w UGB w Zw Z2 w P w(rad/s) ; ; KVCO K I K VCD K I wz wz2 K VCD2 R C D D w z w z2 24 2

13 Circuit Implementation R FB R FB2 i D V FB i P V FB i I R D G MD G MP G MI C D V D D P I MP MN DEAD TIME OGIC Q S R CTR+ CTR- VCD+ VCO- VCD- VCO+ Phase detector is implemented with SR latch Fully differential control eliminates reference clock Shared VCD for proportional and derivative control 25 Prototype Buck Converter in 80nm CMOS Controller 2mm Gate Driver & Power FETs 250µm CCO and CCD 2.5mm PMOS 450µm Gm Cells V FB UT GND NMOS 50µm 400µm A 0 25 MHz, 600 ma buck converter using time-based PID compensator with 2µA/MHz quiescent current, 94% peak efficiency, and MHz BW, Symposium on VSI Circuits (VSIC), June 204. "High frequency buck converter design using time-based control techniques," IEEE JSSC, Apr

14 Steady-State Waveforms ( = V) =V 2π D= T ON T OFF =58.2% T SW T ON T OFF V VCO+ V VCO- 27 oad Transient Response V UN =60mV V =65mV T S =3.5µs 00mV 20µs I OAD 600mA V ripple =3.5mV 2mV 50ns 00mA 28 4

15 Oscillator Frequency Spectra F SW = MHz Open oop F VCO+ Open oop F VCO- Closed oop F VCO+ Closed oop F VCO- 29 Efficiency vs. Output Current Efficiency [%] Fsw=MHz@Vo=V Fsw=MHz@Vo=0.6V 70 Fsw=MHz@Vo=.4V Fsw=5MHz@Vo=V 65 Fsw=20MHz@Vo=V Fsw=25MHz@Vo=V Output Current [ma] 30 5

16 Performance Summary Publication ISSCC 204 This Work Control oop Voltage mode PID Time based PID Process 0.3µm CMOS 0.8µm CMOS Supply Voltage 3.3V.8V Output Voltage 0.37V 2.85V 0.6V.5V F SW 0MHz(30MHz) -5MHz / C 330nH/3.3µF(uF) 220nH/4.7µF Max. oad Current.5A@ =2.4V 600mA Settling Time n/a 3.5µs Output Ripple n/a 3.5mV Controller Current n/a 23µA@MHz Peak Efficiency 9.8%(86.6%) 94%@ =V Active Area n/a 0.24mm 2 3 Application in Multi-Phase Since VCOs come inherently with multiple phases, different phases from VCOs can be tapped All phases use common integrator (VCO) but separate VCDs ɸ 4 ɸ 3 RVCO ɸ 2 ɸ 0 ɸ ɸ REF4 ɸ REF3 ɸ REF2 ɸ REF ɸ REF0 ɸ REF4 ɸ CTR4 ɸ REF3 ɸ CTR3 ɸ REF2 ɸ CTR2 ɸ REF ɸ CTR ɸ CTR4 ɸ CTR3 ɸ CTR2 ɸ I4 ɸ I3 ɸ I2 FVCO ɸ 0 ɸ 4 ɸ CTR ɸ CTR0 VCD2 R D C D VCD ɸ I ɸ I0 ɸ ɸ 2 ɸ 3 MUTI-PHASE TPID Controller 32 6

17 mm 30-70MHz 4-Phase Time-Based Buck -4 R4 VPWM4 MPG R3 PGVPWM3 VO F4 R2 PG F4 VPWM2 F3 R H EN4 R PG F3 VPWM 3 F2 H EN3 F2 PG C 2 2 R~4 F H EN2 F 0 H EN RFB R 3 F~4 D H EN~4 Phase RFB2 2 2 F CSD 0 Controller 0 2 VREF VREF CD F B2T GMI GM RD DAC Z - VREF CCDF CCOF D-to-I 8 F CCDR CCOR R FD Compensator mm Gate Cascoded Diver Output Driver F Gate Cascoded Diver Output Driver Type-III Compensator Gate Cascoded MPG, CSD Diver Output Driver Gate Cascoded Phase Ctrl Diver Output Driver Process Control Synchronization Number of Phases Input Supply [V].8.2/ Output Voltage [V] / FSW[MHz] Inductance [nh] oad Current [A] /0.4 Controller Current Peak Efficiency [%] This Work 65nm CMOS T-PID PWM 90µA@30MHz 87@VO=V JSSC `05 Hazucha 90nm CMOS Hysteretic N/A 83.2/84.5 JSSC `09 P. i 0.5µm CMOS Hysteretic N/A 83@VO=3.3V Power Density [W/mm 2 ] /3.4.2 VSI`4 Harish 22nm CMOS Digital PWM MPG Injection D DPWM Capacitance [nf] N/A N/A 68@VO=V A.8V 30-to-70MHz 87% Peak Efficiency 0.32mm2 4-Phase Time-Based Buck Converter Consuming 3uA/MHz Quiescent Current in 65nm CMOS, ISSCC-205. A 4-phase MHz switching frequency buck converter using a time-based compensator," IEEE JSSC, Dec. 205 N/A 33 7