Mobile 용 PMIC 설계 년도 AIPRC Power IC 설계기술 Workshop 2010 년 12 월 9 일. 서울시립대학교 최중호 1/ AIPRC Power IC 설계기술 Workshop

Transcription

1 /35 Mobile 용 PMIC 설계 200 년도 AIPRC Power IC 설계기술 Workshop 200 년 2 월 9 일 서울시립대학교 최중호 jchoi@uos.ac.kr

2 Power Sources for Mobile Devices 2/35 Typical Battery Characteristics 3.6V.2V One Cell Enough Regulation Required Multiple Cells Required Various Power Supply Voltages for ICs Supply Voltage Values (Even Negative Polarity) oad Current Amount to be Used Noise Immunity Sensitivity to oad and ine Variations For Different Functional Blocks

3 PMIC for Mobile Applications 3/35 Small Form-Factor External Inductors, Capacitors, Resistors Increased Operating Frequency & Bandwidth Reducing The Number of External Off-Chip Components Proper Topology to be Adopted New Techniques to be Studied Integration of Various Power Sources into Single Chip Complexity & Interference Proper IC Fabrication Technology Difficulties in IP Integration onger Battery Time : ow-power Design Multi-Channel Application : Matching Important Multi-Functions Available Through Digital Control

4 Apple iphone 3G Example 4/35

5 Apple iphone 4 Example 5/35

6 DA9502 (Dialog-Semi) Example 6/35

7 MAX8662 (Maxim) Example 7/35 Two 95%-Efficient MHz DC-DC Buck Converters Main: 0.98V to VIN at 200mA Core: 0.98V to VIN at 900mA MHz Boost WED Driver Up to 7 White EDs at 30mA (max) PWM and Analog Dimming Control Four ow-dropout inear Regulators.7V to 5.5V Input Range 5μA Quiescent Current Single-Cell i+ Charger Adapter or USB Input Thermal-Overload Protection Smart Power Selector (SPS) AC Adapter/USB or Battery Source Charger-Current and System-oad Sharing

8 TPS650 (TI) Example 8/35 inear Charger Management for Single i-ion or i-polymer Cells Dual Input Ports for Charging From USB or Wall Plug, (00/500-mA USB Req.) -A, 95% Efficient Step-Down Converter for I/O and Peripheral Components (VMAIN) 400-mA, 90% Efficient Step-Down Converter for Processor Core 2x 200-mA DOs for I/O and Peripheral Components Serial Interface Compatible w/ I 2 C 00-kHz, 400-kHz Operation 70-μA Quiescent Current % Reference Voltage Thermal Shutdown Protection

9 Typical Power Source Options 9/35 Applications Efficiency Cost Noise DO* inear Regulator < V IN C A A Charge Pump Converter** >< V IN B C C DC-DC Boost Converter > V IN A C- C- DC-DC Buck Converter < V IN A C- C- DC-DC Buck/Boost Converter >< V IN A- C- C- * DO : ow-drop Out ** imited Output Voltage Values & oad Current Optimum Power Management Required

10 0/35 DO inear Regulator

11 inear Regulator Basic Principle /35 V IN V IN + _ I OAD _ + I OAD R 2 R 2 REF REF V FB V FB R R Error Amplifier, Pass Transistor (Output Transistor), Voltage Reference, Feedback Network V GS of Pass Transistor Controlled by Error Amplifier for Defined V DS Output Voltage Regulated w.r.t. Varying V IN and I OAD Stable Operation Required Efficiency h (ideal) = (V IN - )/V IN

12 ow-drop Out Design Restriction 2/35 PUT NMOSFET PUT PMOSFET V IN V IN V REF +_ V REF _ + R R 2 R R 2 I OAD C I OAD C More Stable Operation Difficult for DO Design Easy for DO Design ess Stable Operation

13 Static Performance 3/35 V REF _ + A ERR V IN M Feedback Gain R R R 2 oop Gain R R 2 I OAD A G A ERR A M Transfer Function V ERR M V REF A A A G R R 2 oad Regulation V I R rout M A G A ERR g m M ine Regulation V V IN g m M R g m M rout M A G A ERR

14 Poles of DO Regulator 4/35 V IN V REF _ + C GS C GD R O R R 2 C I OAD C R ESR Error Amp Output Related w/ arge C GS & C GD Output Node Related w/ Varied R O & Very arge C Other Parasitic Capacitance Related Poles (High-Frequency) For Easiest Frequency Compensation, Use the Capacitor ESR (Equivalent Series Resistance) ZERO R ESR C

15 imited Usage of ESR 5/35 A G () A G () A G () Stable but Reduced Bandwidth Unstable As R ESR Smaller (Zero Increased) Unstable imited Value of R ESR for Fixed C As R ESR Increased arger Perturbation during Transient

16 3-Stage DO Regulator 6/35 V REF Error Amp _ Buffer C GS V DD + C IB R OB C GD R R 2 C I R ESR Error Amp Output /(r oerr C IB ) > /(r oerr C M ) Helpful for arge Zero (Smaller R ESR ) Buffer Output /(R OB C M ) arge Enough DO Output /(R C ) Parasitic Pole

17 7/35 Compensation w/ Differentiator IEEE TCAS-I, pp , 2004 (Texas A&M Univ.) 2 Z C R 2 2 ds P R R C C R R R r gdpass 2 ds mpass par par P2 C R R R r g C R

18 Design Considerations 8/35 Non-Idealities imited oop Gain for Stability Accuracy of Reference Voltage Offset Voltage of Error Amplifier Severe for ow V REF Temperature Variation High-Performance Required Reduced Standby Current Consumption Fast Transient Operation Improved ine/oad Regulation arge Output Transistor for Higher Current Capability Handling of arge Dynamic Switching oad Current Possible ack of External Capacitor

19 9/35 DC-DC Converter

20 DC-DC Converter Basic 20/35 Buck (Step-Down) Converter V BAT S ON S OFF C I = D V BAT = T ON T V BAT Boost (Step-Up) Converter V BAT S OFF S ON C I T = V BAT = V BAT -D T OFF Buck/Boost Converter Buck + Boost = V BAT = V BAT D -D T ON T OFF

21 Boost Converter Basic 2/35 V IN I S ON S OFF I C C I On-Time : DT I ON DT V t dt V IN DT Store Energy in Inductor I (V IN - )/ Off-Time : (-D)T I V IN / I I OFF D T V t dt V IN V DT DT (-D)T T Provide I I C I C Maintain Steady Stage V D V IN

22 Buck Steady State 22/35 On-Time Off-Time V IN I V C I IN I OAD C I V IN - V out T ON T T OFF I DT T - V out (V IN V T V V V ) T IN tdt 0 ON T T on 0 V T 0 D OFF I I DT T 2I V IN V I V T IN ON V 2 V IN V DT DT

23 + Architecture 23/35 Reverse Y Y Y R 2 V BAT C I M P R Bias Timing Control Driver Driver X X C I X V BAT M N Start-Up Reverse Buck Converter Boost Converter arge MOSFET Switches R ON << 00mW Timing Control Circuit for Frequency / Duty-Cycle Programming Negative Feedback Circuit to Maintain a Output Voltage Frequency Compensation for Stable Operation Driver Circuits for Driving arge MOSFET Switches Protection & Start Up Circuitry

24 Efficiency h 24/35 Efficiency h : P output / P battery = (P battery -P loss ) / P battery Power oss Conduction oss oad Current Dependent On-Switch Resistance, DCR of Inductor, ESR of Capacitor arge MOSFET Switches, Good External Components Switching oss Frequency Dependent Switching Active Devices, Charging Capacitors ow-frequency Desirable (imited by I PEAK ) Fixed oss Bias Current, eakage Current ow-power Design

25 PWM vs. PFM 25/35 I t ON t OFF ight oad I t ON t OFF ight oad I AVG I AVG t t PER t t PER t ON t OFF I Heavy oad I Heavy oad I AVG I AVG2 t PER2 t t PER t PFM PWM Average Current Switching Frequency Duty Ratio (On-Time) Peak Current Constant Variable Switching oss ight oad Condition < Conduction Nearly Constant Heavy oad Condition > Conduction Nearly Constant Output Ripple Possibly arge Small Noise Spectrum Variable Constant External, C Values Choose to Difficult Easier Preferred Approach of Combining Both Modulations

26 Switching Frequency 26/35 I V IN I S ON S OFF I C C (V IN - )/ I Inductor Current Ripple I V IN DT V IN V For CCM Operation I R I 2 2 f DT D D I I C DT V IN / T I Output Voltage Ripple V D D V 8C 2 f 0 Higher Switching Frequency Smaller & C Needed Preferred for Mobile High-Speed Switching FETs?

27 Voltage-Mode PWM Controller () 27/35 V IN I S ON S ON C I V RAMP (fixed) V C2 (t) V C (t) PWM PWM PWM 2 Output Voltage Used for Generating PWM Signal Advantage : Simplicity Control-to-Output Transfer Function (Boost) s 2 V D R HC s D D s 2 D R C Unstable When Used in Feedback Elaborate Frequency Compensation Required 2 2 s

28 Voltage-Mode PWM Controller (2) 28/35 PID Frequency Compensation DC gain G C s G CM Phase Margin s s s High-Freq Ripple z s s p p2 All R, C Elements Off-Chip

29 Current-Mode PWM Controller () 29/35 V IN I S ON S ON C I I C (fixed) I SEN (t) I SEN2 (t) PWM PWM PWM 2 Inductor Current Used for Generating PWM Signal Control-to-Output Transfer Function (Boost) H C s DR D 2 s 2 R RC s 2 Simple Compensation Useful for Mobile Application V CNT V FB g m off-chip H COMP s g m src sc

30 Current-Mode PWM Controller (2) 30/35 I V IN S ON V SEN R SEN Simple Degraded Efficiency Off-Chip Resistor Current-Mirroring On-Chip Current Sensing Mismatch Problem? IEEE JSSC, 2004 Inductor Current Simulation On-Chip Current Sensing Tuning & Calibration? IEEE JSSC, 2007

31 Integrated Power Switch Transistors 3/35 Conduction Power oss P = I 2 R If Possible, Synchronous Two Switches to be Integrated R ON : Transistor ON Resistance arge Size : W>00,000mm for Several 0mW Preferred Structure : High Width-to-Area Ratio

32 PMIC + a 32/35 DA9057 TPS65950 DC/USB Chrg, 4 Bucks, 0 DOs, w-ed, 6-b Stereo CODEC, 5-band EQ DC/USB Chrg, 3 Bucks, 0 DOs, w-ed, Voice/inear CODECs, 6-b ADC/DAC, Audio I/O, USB Tx/Rx

33 Digital PWM Controller Approach 33/35 Analog Control Digital Control VBAT SWON VBAT SWON SWOFF RDCR C R SWOFF RDCR C R I I RESR R2 RESR R2 BUFFER BUFFER BUFFER BUFFER Window ADC DEAD TIME CONTRO QB R S + Error AMP. + VREF=0.98V DEAD TIME CONTRO QB 0b D(n) DPWM CK(MHz) UT 2b E(n) + + VREF VREFH SAWGEN. REFGEN. Digital Controller to Simulate Analog Frequency Compensator External R & C Components to be Removed Hardware Minimization 2-bit ADC, ook-up Table Approach Digital PWM w/ Error Feedback oop Digital Versatility?

34 Digital PMIC Example 34/35 UCD9240 of TI Digital Power Control/Management Digital Power Control Reference Setting Compensation Algorithm DPWM Control DPWM w/ Various Operating Modes V/I/Temp Sensing w/ ADCs V/I/Temp Protection PMBus for External Interfacing

35 35/35 감사합니다. Q & A