Low Dropout Voltage Regulator Operation and Performance Review

Transcription

1 Low Drop Voltage Regulator peration and Performance Review Eric Chen & Alex Leng ntroduction n today s power management systems, high power efficiency becomes necessary to maximize the lifetime of the battery. Low drop linear regulators (LD) have been wildly used in power management due to the characteristics, such as simplicity, low cost, high current density, and small space. This report presents some characteristics of LD, such as the basic operation, efficiency, line/load regulation, efficiency, etc. nput-to-utput Drop Voltage Drop voltage is the difference between input and put terminal. Fig. 1 shows an example of an n-channel LD. N-channel MSFET is used to simplify the operation introduction; however, n-channel MSFET devices are not widely used in LD design. Vi Pass Element V Control R1 R2 Fig.1. LD Using N-Channel Pass Element N-channel MSFET could operate in two operation region-linear and saturation region. While operating in the saturation region, MSFET is a voltage control current source, and LD usually operates in this region. While operating in linear region, MSFET operates like a resistor. Fig. 2 shows the -V curve of n-channel MSFET. 1

2 D V DS = V GS V TH V GS 4 V GS V 3 V GS 2 GS 1 V DS Fig. 2. -V Curve of N-Channel MSFET Pass Element Pass Element K(Vgs-Vt) Vi V Vi Rds V Rds Ro Ro (a) (b) Fig. 3. (a) LD Equivalent Circuit in The Saturation Region (b) LD Equivalent Circuit in The Linear Region Fig.3 shows the equivalent circuit of MSFET in the linear and saturation region. The saturation current of MSFET is given by D ( V V ) 2 1 W = µ ncox gs t (1) 2 L where μn is the electron mobility, C ox is the parasitic capacitor, and W/L is the width and length ratio of MSFET. For simplifying, K, so the current of MSFET is given by 1 W µ n C ox 2 L is defined as current gain 2

3 D 2 = K( Vgs Vt ) (2) Under varying load conditions, Vgs voltage controls LD to keep the put condition in the demand value. Fig. 4 shows the MSFET operation region as put current increases. When the load current increases form D1 to D2, the operation point moves from P1 to P2, and if the load current continuously increases, the operation point moves from P2 to P3 locating in the linear region. Fig. 5 shows the MSFET operation region as input voltage changes. When the input voltage changes from V DS1 to V DS2, the operation region is still in the saturation region. f the input voltage decreases from V DS1 to V DS3, the operation region changes from saturation region to linear region. Fig. 6 shows the typical LD operation region. LD usually operates in three regions: off region, drop region, and regulation region. f Vin is too small, LD operates in the off region. f Vin increases but not large enough, LD can not regulate to the demanded V. n this region, it is usually called drop region, and the input voltage is a function of the control loop. When the input voltage still increases, the LD operates in the saturation region which LD circuits usually operate in. n this region, the LD circuit can regulate the put voltage in the demanded value. The drop voltage is defined as the formula Vin-V, and it is the minimum difference between input and put voltage where the circuit ceases to regulate. So the drop voltage can be expressed in term of a MSFET resistance. D V DS Linear = V GS V TH Saturation D4 D3 D2 D1 P3 P2 P1 V GS 4 V GS 3 V GS V 2 GS 1 V DS Fig. 4 LD Using N-Channel MSFET as utput Current ncreases 3

4 D V DS Linear = V GS V TH Saturation D4 V GS 4 D3 D2 D1 P3 V DS 3 P1 P2 V DS 1 V DS 2 V GS 3 V GS V 2 GS 1 V DS Fig. 5. LD Using N-Channel MSFET as nput Voltage Changes Fig. 6. LD peration Region Ground Current The ground current is defined as the different between the input current and the current. Fig.7 shows the ground current of LD. The ground current consists of the bias current (the band-gap reference, the error amplifier, and the sampling resistors) and the pass element driving current. The ground current is given by ground = (3) in 4

5 f the pass element is BJT transistors, the driving current is larger than the driving current using MSFETs as pass elements. The driving current of MSFETs is approximately zero, and the driving current of BJTs is given by C B = (4) β where B is the base current of a BJT, C is the collect current of a BJT, and β is the current gain of a BJT. Fig. 8. shows the ground current of a BJT and MSFET varies with put current. For a BJT, the ground current increases with the put current because a BJT is a current-driven element which is shown in formula (4). For a MSFET, the ground current is almost constant value while the put current is changed because a MSFET is a voltage-driven element. Fig. 7. Ground Current in LD ground BJT Standby Current MSFET load Fig. 8. Ground Current and utput Current 5

6 Pass Element Topologies Fig. 9. shows the five basic pass elements, namely, NPN-Darlington, NPN, PNP, PMS, and NMS. The choice of topologies is depend on the process and the application of LD. The bipolar devices are able to deliver the highest put currents for a given supply. The current capability of MS transistors is depend on the gate-to-source voltage and the aspect ratio. However, the advantage of MS transistors is the lowest quiescent current. Fig. 9. Pass Element Topologies The Darlington topology needs at least 1.6V (0.2V+0.7V+0.7V) to regulate to the put voltage; however, the LD typically operates with 500mV drop voltage. But this topology has large put current capability. The drop voltage of this topology is given by V + ( drop ) = Vsat + Vbe Vbe for Darlington (5) The NPN pass element topology is comprised of an n-channel BJT and a p-channel BJT. The drive current of a NPN pass element topology is very small. Because the put current is driven by the base current of the n-channel BJT, and the n-channel BJT is driven by the base current of the p-channel BJT. So the driving current of the NPN topology is very small. The drop voltage occurs when the p-channel BJT operates in the saturation region. The drop voltage can be given by V + ( drop ) = Vsat Vbe for NPN Pass Element (6) 6

7 The big advantage of the PNP pass element topology is the very low drop voltage, but the driving current of this topology depend on the put current is very large. The drop voltage is given by V = ( drop ) V sat for PNP Pass Element (7) For an NMS pass element, unless a charge-pump is utilized to boost the gate voltage to be larger than input voltage, the drop voltage is given by V + ( drop ) = Vsat Vgs for NMS Pass Element (8) A PMS pass element is typically the best choice yielding a low drop voltage and low quiescent current. The drop voltage is given by V ( drop ) = RN for PMS Pass Element (9) Table 1. shows the comparison between the different pass elements on the different features. Table. 1. Comparison of Pass Element Efficiency The LD s efficiency can be defined as a ratio of put power and input power, and it can be given by V Efficiency = 100 ( + ) V (10) ground N f neglects ground current, the efficiency is given by Efficiency = V V N 100 = V V + ( V N V ) (11) 7

8 From formula (10) and (11), to get high efficiency, ground current and the drop voltage should as small as possible. Load Regulation Load regulation is a measure of the ability of a LD to keep to the demanded voltage under varying load conditions. Load regulation is given by Load _ Re gulation = (12) Fig. 10 shows a load regulation of LD. When there is a small change of load current, this change will cause put voltage vary. The variable value of put voltage can be given by V = R (13) where Req is the equivalent put resistor seeing from put node (Req=(R1+R2) Rload Rload). The load regulation can be given by eq 1 = g g R1 R ( R + m a 2 2 ) (14) All the frequency components are neglected, and the load regulation is a steady-stage parameter. The load regulation is limited by the open loop current gain of the LD system as shown in the formula (14). Fig. 10. Load Regulation of LD 8

9 Line Regulation Line regulation is a measure of the ability of a LD to keep to the demanded voltage under varying input voltage conditions. Line regulation is given by Line _ Re gulation = (12) Fig. 11 shows a line regulation of LD. When there is a small change of input voltage, this change will cause put voltage vary. The variable value of put voltage can be given by Rload R2 = ga gm Rload R + R R1 + R2 (13) DS load + R2 [1 gm ga Rload R1 + R2 ] = R Rload + R load DS (14) in R1 + R2 1 R2 gm ga ( R DS + R load ) (15) The load regulation and the line regulation are steady state parameters, and the frequency components are neglected. The line regulation can by improved if dc open loop gain increases. Fig. 11. Line Regulation of LD 9

10 Transient Response The transient response is the maximum allowable put voltage variation for a load current step change. The transient response is influenced by the bandwidth of LD, put capacitor, loading current, and the ESR of the put capacitor. Fig. 12 shows the LD transient response and some time and voltage labels. t1 t3 V 3 4 tr-max t2 2 t4 load Time[S] Fig. 12. LD Transient Response The worst-case time required for the loop to respond specified by tr-max, the maximum permissible put voltage variation, which is a function of the put capacitor, the electrical series resistor of the put capacitor, the bypass capacitor, and the maximum loading current, and it is given by load _ max tr max t1 + C + C b (16) C + Cb t1 [ tr max load _ max ] (17) where is the variation resulting from the ESR of the put capacitor. The ESR effects can be reduced by the bypass capacitors. n typical implementations, the t1 is influenced by the bandwidth and the internal slew-rate associated with the parasitic capacitor of pass element, as shown in Fig

11 Fig. 13. LD with Parasitic Elements The resulting time can be given as t1 BW 1 close _ loop + t sr = BW 1 close _ loop + sr Cpar (18) where BW close_loop is the closed-loop bandwidth of the system, tsr is the slew-rate time of the internal operation amplifier, sr is the slew-rate limit current, and ΔV is the voltage variation at Cpar. f the slew-rate current is large enough, the t1 is approximate to the function of the closed-loop bandwidth of the system. nce the slew-rate condition is terminal, the put voltage recovers and settles to the final value as shown in the formula (19). = R 2 _ reg load _ max (19) where R _reg is the closed-loop put resistor. The settling time( t2) is depend on that the time required for the pass element to fully charge the put capacitor, and the phase margin of the open-loop frequency response. When the loading current pulls down, the put voltage variation peaks at 4, whose voltage magnitude is dominated by the put capacitor charged, and the ESR of the put capacitor. This value can be given by 4 C load _ max load _ max 1 t3 + + Cb C + Cb BWclose _ loop + (20) 11

12 When the pass element is finally to shut off the variation settles down to 3, the put voltage takes time t4 to discharge to its final value. Δt4 is given by C t4 pull + Cb ( C + Cb ) R2 3 = 3 down Vref (21) f the put current is zero, the put capacitor is discharged by the feedback resistor network only. Frequency Response To analysis the LD frequency response, the closed loop network is broken. Fig. 14 shows the LD small signal equivalent circuit. The error amplifier is modeled by a transconductance (ga), the put equivalent capacitor (Cpar), and the put equivalent resistor (Rpar). Fig. 14. The Small Signal Equivalent Circuit of LD The impedance seeing from Zo is given by Z = S = R 2 R 12P 12P R ( R C C 1 + SC b R 12P (1 + SR + S[( R ) 12P 1 SC C + R b ) ) C + R 12P C ] + 1 b (22) 12

13 Where R 12P =Rds (R1 + R2) Rds The put capacitor is usually larger than the bypass capacitor. So, the impedance seeing form Zo can be approximated to Z [1 + S Rds(1 + SR ( Rds + R ) C ] [1 + S( Rds R ) C ] ESR C ) b (23) The open-loop gain can be described as Vfb Vs gmaragmz R2 = [ 1+ SR Cpar] R1 + R2 A (24) From the fo4mula (24), the overall open-loop gain of the system is obtained, and the locations of zero and pole are found. The approximated poles and zero can be given by 1 load P1 2πRdsC 2πV C (25) A P 1 2 2π R C b (26) P 1 3 2πR Cpar (27) A Z 1 1 2π R C (28) Where Rds=V A / load, V A is channel length modulation parameter. The locations of poles and zero depend on the architecture of the error amplifier used by the LD and the type of the put capacitors. Fig. 15 shows the LD frequency response. Assume the put capacitor (C ) is larger than the bypass capacitor (C b ), so the location of P 1 is very small than the location of P 2. To maintain the stability of the LD circuit, the location of Z 1 is used to cancel the effect of P 3, and the location of P 2 is placed to be larger than the unit-gain bandwidth. 13

14 P1 P3 Z1 Frequency P2 Fig. 15 Frequency Response of LD Range of stable ESR (Tunnel of Death) A typical LD regulator requires an put capacitor with an equivalent series resistor (ESR) to maintain in the stabilization. A LD typically has two poles before unity gain bandwidth, and these poles with compensation could cause oscillation as shown in Fig. 16. Gain-dB P1 P2 Frequency Fig. 16 LD Frequency Response with Compensation 14

15 The equivalent series resistance of the put capacitor is used for generating a zero. This zero produced by the ESR is placed before the unity gain frequency (UGF) so that the phase shift will be compensated. Therefore, the linear regulator is stable because there is only one effect pole in the left side of UGF as shown in Fig. 17. Gain-dB P1 P3 Z1 UGF P2 Frequency Fig.17 Frequency Response with Compensation The ESR value must be maintained in the range that determines the loop stability. Fig. 18 and Fig. 19 show that the zero compensated by ESR is of the range. f the value of ESR is too low, the compensated zero will be placed at the high frequency, and there are still two poles in the left side of UNF as shown in Fig. 18. Fig. 18 Unstable Condition While the Zero in the High Frequency 15

16 f the value of ESR is too large, the compensated zero will be placed at the low frequency, and another pole (P3) appears in the left side of UGF, and even there is a zero, there are still two effect poles in the left side of UNF as shown in Fig. 19. P1 P3 Z1 P2 Frequency UGF Fig. 19 Unstable Condition While the Zero in the Low Frequency Because ESR can cause instability, a range must be provided to show the stable values of ESR. Fig. 20 shows a typical range of ESR values with respect to the put currents. Fig. 20 Range of Stable ESR Value 16

17 Reference [1] Gabriel Alfonso Rincon-Mora, Current Efficient, Low Voltage, Low Drop-ut Regulators, Ph.D Thesis, Georgia nstitute of Technology, November [2] Texas nstruments, Technical Review of Low Drop Voltage Regulator peration and Performance, Application Report, August