A 4 µa-quiescent-current Dual- Mode Digitally-Controlled Buck Converter IC for Cellular Phone Applications

Transcription

1 A 4 µa-quiescent-current Dual- Mode Digitally-Controlled Buck Converter IC for Cellular Phone Applications Jinwen Xiao Angel Peterchev Jianhui Zhang Prof. Seth Sanders Power Electronics Group Dept. of EECS U. C. Berkeley

2 Outline Application requirements Dual-mode controller Analog and digital interface Internal power management Experimental results Summary 2

3 Motivation Low quiescent current to extend standby time Integrate with digital systems on same die Easy interface with digital systems fast response with digital feed forward Computation capability for advanced control schemes (e.g. adaptive control) Immunity to analog component variations and noise Benefit from technology scaling, easier to migrate to new technology 3

4 Buck Converter Requirements In Cell Phones Convert battery voltage to high quality DC voltage High efficiency over wide load range Pulse Width Modulation (PWM) for heavy load Pulse Frequency Modulation (PFM) for light load Low quiescent current in PFM 4

5 Typical Handset Power Management Diagram V in : V Buck converter system V x L V o V o : V, tolerance 2-3% I o : ma Battery C Cellular phone chip set Ctrl Controller V ref I o Ctrl (PWM) Ctrl (PFM) 5

6 DC-DC Converter Modes of Operation V ctrl V x L V o V in I L C 0 I L, cnt t I o V ctrl Controller V ref 0 I L t t on t off I L, disc Continuous conduction 0 t on I o t Discontinuous conduction T s = 1/f s 6

7 DC-DC Converter Losses Conduction loss Switching loss Controller quiescent power Misc: output inductor core loss, stray inductance loss, etc V in L S C g V ref Controller V x R L L V o C x R ESR C 7

8 PWM and PFM Control PWM PFM Switching freq. Constant Proportional to load current Losses Conduction loss and switching loss Conduction loss and switching loss scale with load, controller quiescent current significant at light load V in V ref controller V x L V o C 8

9 PWM and PFM Losses Losses Conduction loss Controller quiescent power Switching loss PFM, standby mode PWM, talk mode I o (ma) 9

10 Dual-mode System Diagram V in Buck converter IC V ref V o Comparator Ring ADC D e PFM control Logic PID Digital dither PWM control D DPWM MUX Ring osc. system clock Simplfied Power train V x L C V o MODE GND Dual mode controller Digital Pulse Width Modulator (DPWM) Power switches 10

11 PFM Mode Diagram & Switching Behavior V ref D PF M 0 Ctrl V in V x L V o Sample DPWM C Sample V o V ref Ctrl Converter discontinuous conduction Fixed on-time control Zero-DC-bias comparator for low power 11

12 PFM Mode Comparator clk M 8 M 3 M 4 M 9 clk V on V op clk M 10 M 5 M 6 M 11 X Y clk V ip M 1 M P 2 V in clk M 7 Y.-T. Wang and B. Razavi An 8-bit 150MHz CMOS A/D Converter 12

13 PWM Mode MHz switching frequency V in Buck converter IC V ref V o Comparator Ring ADC D e PFM mode PFM logic PID PWM mode Digital dither D DPWM MUX Ring osc. Simplified power train V x L C V o system clock MODE GND 13

14 PWM Mode ADC Considerations Windowed quantization range Tolerance to switching noise and switching ripple V x 2 V/div Digital implementation V o 20 mv/div 14

15 Ring Oscillator with Subthreshold Bias Linear dependency of ring-oscillator frequency on bias current VDD I bias Frequency (Hz) 7.0E E E E E+06 4.E-07 5.E-07 6.E-07 7.E-07 8.E-07 9.E-07 Current-starved differential ring oscillator Bias Current (A) 15

16 PWM Mode Ring-ADC Architecture V o VDD Analog Block V ref Counter Counter Σ Digital Block D e M M Counter Σ f 1 f 2 VSS V I f De Windowed quantization range Insensitive to switching noise bulk part synthesizable Counter Automatic monotonicity Wide Vo operating range 16 mv/step, 80 mv window, 0.15mm 2 on 0.25 µm CMOS 16

17 PWM Mode Compensator I Fully on From ring-adc De PD en Dither Fully off D Go to DPWM Comb Logic Clamp en Pin: EN en Soft start counter Soft_start 17

18 DPWM VDD I bias 32-tap Differential Ring T s DT s D 5 5-bit MUX PWM Ring-MUX scheme 5-bit DPWM hardware + 5-bit digital dither 1 1 µa at 600 khz 1. A. Peterchev Quantization resolution and limit cycling in digitally controlled PWM converters 18

19 Power Train and Internal Power Management V in Gate drive M P1 I p M P2 Internal linear regulator V m =V in /2 C m I r I p -I n I ctr PWM, PFM controller Gate drive I n= I p /2 M N2 M N1 SW Cascode power train with gate drives Low break down voltage Cascoded power switches & internal linear regulator Scavenges I p from high-side gate drive discharge 19

20 Experimental Results Load transient responses Steady state response Efficiency Chip micrograph 20

21 Load Transient Response PWM Mode, 500µs/div I o 150mA 50mA Vin= 3.2 V, Vo= 1.2 V. Load step 100 ma V o, 20mV/div, AC coupled PFM Mode, 10µs/div 100mA I o V o, 20mV/div, AC coupled 12mV 0.1mA PWM mode: both steady-state voltages in ADC zero-error bin PFM mode: voltage ripple ma 21

22 Steady-state Response: PWM Mode Vin= 3.2 V, Vo= 1.2 V, fs = 500 khz. Load=100mA Switching node, 2V/div Vo, 20mV/div, AC coupled 500ns/div 22

23 Efficiency: PWM and PFM Modes Efficiency Output current Io (ma) PWM efficiency drops off at low I o PWM PFM V in = 4.5 V V o = 1.5 V. PFM efficiency high at low I o Composite efficiency high over wide I o range 23

24 Summary of Chip Performance Technology Input voltage range Output voltage range External LC filter Maximum output current PFM mode sampling frequency PFM mode quiescent current PWM mode switching frequency PWM mode DC output voltage precision PWM mode output voltage ripple Active chip area 0.25-µm CMOS (Max. supply 2.75 V) V V L=10 µh, C=47 µf 400 ma 600 khz 4 µa MHz ±0.8% 2 mv 2 mm 2 24

25 Chip Micrograph Active area 2 mm mm Power train Controller 2.6 mm 25

26 Summary Efficient digital control for mass market power management More than 3-fold quiescent current reduction Low-power and robust analog-digital interface Controller + Power train on low-voltage CMOS process 26

27 Acknowledgement Funding provided by Linear Technology, Fairchild Semiconductor, National Semiconductor, and California Micro Program 27

28 PWM Mode: Quantization Resolutions Problem: Steady state oscillation limit cycles 1 error bin 0 error bin -1 error bin ADC LSB s DPWM LSB s Solution: Multiple DPWM bins in ADC zero error bin 1 error bin 0 error bin -1 error bin 28