A Multi-phase VCO Quantizer based Adaptive Digital LDO in 65nm CMOS Technology
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1 A Multi-phase VCO Quantizer based Adaptive Digital LDO in 65nm CMOS Technology Somnath Kundu and Chris H. Kim University of Minnesota Dept. of ECE 1
2 Presentation Outline Analog vs. digital Low DropOut (LDO) regulators Digital LDO examples Proposed VCO-based digital LDO Stability analysis 65nm simulation results Conclusion 2
3 Integrated Voltage Regulators <1% area overhead 22nm Intel Haswell processor N. Kurd, et al., ISSCC, nm IBM POWER8 processor Z. Toprak-Deniz, et al., ISSCC, 2014 On-chip distributed voltage regulators Wide operating conditions with fast transients 3
4 Analog vs. Digital LDO Analog LDO Digital LDO Ref: S. Gangopadhyay, JSSC 14 Digital LDOs: Good scalability with technology Low voltage operation Loop parameters can be controlled digitally 4
5 Digital LDO Examples 1-bit ADC Multi-bit ADC Y. Okuma, CICC 10 T-J Oh, TVLSI 14 Simple design Requires many clock cycles to settle Slow response Complex design Requires fewer clock cycles Fast response 5
6 Digital LDO Examples VREGC UREGs V IN V REF S/H 3b Flash ADC IDAC + CP PWM SA CK S V OUT C L I L Toprak-Deniz, IBM, ISSCC, 2014 Multi-bit ADC based distributed digital LDO Shared voltage regulator controller (VREGC) and distributed micro-regulators (UREGs) VREGC utilizes a 3-bit flash ADC 6
7 Motivation of This Work Trade-off between response time and efficiency o Higher sampling clock provides faster settling o Lower sampling clock improves efficiency Adaptive sampling clock frequency High resolution ADC solutions o Higher ADC resolution provides settling in fewer clock cycles o Increasing ADC resolution requires more power and area VCO based digital intensive ADC 7
8 Presentation Outline Analog vs. digital Low DropOut (LDO) regulators Digital LDO examples Proposed VCO-based digital LDO Stability analysis 65nm simulation results Conclusion 8
9 Proposed VCO-based Digital LDO VCO quantizer based ADC V REF + + Multi-ph Time Quant. - N CK S Controller Σ > 10b V IN V OUT EN_HS Droop/ overshoot Detector I LOAD C L VCO based quantizer provides multi bit resolution Droop/overshoot detector generates adaptive sampling clock (CK s ) 9
10 Multi-phase VCO-based Quantizer V REF V OUT CK REF VCO<1:m> Multi-ph Time Quant. Count=Kf VCO /f REF VCO<1> VCO<2> Counter Counter + 10b VCO<1> /K VCO<m> Counter VCO<2> CK S CK CK REF S RST RST Multiple VCO phases are utilized to increase resolution VCO phase quantization provides 1 st order quantization noise shaping 10
11 Adaptive Sampling Clock Generator V REF /K CK S V ctr Fixed Current EN_HS ENB CK IN+ CK V OUT EN_HS CK IN- VCO<1:m> V REF +ΔV V OUT V REF -ΔV Droop/overshoot Detector EN_HS I LOAD V REF +ΔV V REF V REF -ΔV CK S High Freq High Freq High Freq Low Freq V OUT EN Low Freq Droop/overshoot detector detects sudden change in load current by observing V OUT VCO high frequency mode is activated to reduce ripple and faster recovery High Freq 11
12 Presentation Outline Analog vs. digital Low DropOut (LDO) regulators Digital LDO examples Proposed VCO-based digital LDO Stability analysis 65nm simulation results Conclusion 12
13 Discrete-time Small Signal Model Two poles in the system due to digital integrator and output load Ref: S. B. Nasir, TPE,
14 Root Locus and Stability Higher sampling clock frequency, lighter load moves z p2 towards unity circle Proposed LDO is stable for I LOAD > 3.2mA Ref: S. B. Nasir, TPE,
15 Presentation Outline Analog vs. digital Low DropOut (LDO) regulators Digital LDO examples Proposed VCO-based digital LDO Stability analysis 65nm simulation results Conclusion 15
16 Transient Step Response C L =40pF, V IN =1, V OUT =0.9V, 65nm CMOS 16
17 Baseline Digital LDO V REF CK REF VCO<1> Single-ph Time Quant. + N - + Controller Σ V IN V OUT VCO<1> > Counter xm I LOAD C L CK REF /K CK S RST Single phase VCO quantizer with fixed sampling frequency Baseline design is used for performance comparison 17
18 Transient Step Response C L =40pF, V IN =1, V OUT =0.9V, 65nm CMOS Multi-phase VCO quantization error during steady state is only 0.5mV 18
19 Voltage Droop and Settling Time C L =40pF, V IN =1, V OUT =0.9V, 65nm CMOS Adaptive sampling reduces voltage droop by 40 60% and times faster settling 19
20 Current and Power Efficiency Maximum current efficiency 99.3% and power efficiency 92.8% Total quiescent current: 660µA (VCOs: 530μA, Switching: 110μA and droop/overshoot detector: 20μA) Overhead of droop/overshoot detector is negligible 20
21 Performance Comparison This Work TPE 13 [5] ISSCC 15 [3] TVLSI 15 [6] Technology 65nm Multi-bit ADC type VCO V IN range (V) nm Multi-bit SAR nm 1-bit Comp nm Multi-bit VTC+TDC V OUT range (V) I LOAD (ma) * I Q (µa) 660* Max. Current Efficiency (%) 99.3* C L (nf) Steady-state f s (MHz) ΔV OUT (mv) Settling Time (µs) 50** 0.7** FOM # (ps) 0.53** 8.4* Schematic Simulation results # FOM=C L ΔV OUT I Q /(ΔI LOAD ) 2 *At V IN =1V and V OUT =0.9V **I LOAD step from 30-80mA in 1µs
22 Conclusion Multi-phase VCO quantizer based ADC operating over wide range of load current and input/output voltage in 65nm CMOS technology Dynamically adaptive sampling clock depending on the load transients reduces the output voltage ripple and provides faster settling Schematic simulations show a maximum current efficiency of 99.3% and an FOM of 0.53ps 22
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