Modulator with Op- Amp Gain Compensation for Nanometer CMOS Technologies

Size: px
Start display at page:

Download "Modulator with Op- Amp Gain Compensation for Nanometer CMOS Technologies"

Transcription

1 A. Pena Perez, V.R. Gonzalez- Diaz, and F. Maloberti, ΣΔ Modulator with Op- Amp Gain Compensation for Nanometer CMOS Technologies, IEEE Proceeding of Latin American Symposium on Circuits and Systems, Feb xx IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.

2 Σ Modulator with Op-Amp Gain Compensation for Nanometer CMOS Technologies Aldo Peña Perez, Victor R. Gonzalez-Diaz and Franco Maloberti Department of Electronics, University of Pavia. Via Ferrata, Pavia - ITALY [aldo.perez, franco.maloberti]@unipv.it Electronics Faculty, BUAP Puebla. Av. San Claudio y 18 sur. Puebla - MEXICO vrgdiaz@ece.buap.mx Abstract A gain compensated op-amp for discrete-time Σ modulators is described. The method greatly reduces the integrator s phase error caused by low DC gain on amplifiers. The scheme uses an additional unity gain buffer to correct the error caused by gains as low as 20 db, thus enabling high-performance Σ modulators in nanometer-scale CMOS technologies. Design strategies for op-amps and buffer designed with a 65 nm technology to be used with the method are considered. The effectiveness of the approach is verified with a second-order Σ modulator simulated at behavioral level with MATLAB and Verilog-A descriptions. The low sensitivity to buffer gain s variations is also verified. Index Terms Amplifiers, compensation, operational amplifiers. C 1 V _ IN V CM DRIVING PHASES nt nt+t + Op-Amp I. INTRODUCTION Speed, compactness and high complexity at low cost are key advantages of nanometer technologies for making successful many new products based on digital processing. However, the use of ultra sub-micron technologies in designing highperformance data converters faces limits caused by the degradation of analog performance with scaling. The intrinsic gain of nanometer transistors drops significantly [1] making more and more difficult the design of op-amps with large gain as required by many data converter architectures [2]. The benefit of modern technology is that the operation frequency, f T, of transistors goes up to many tens or even hundred GHz. Therefore, it is possible to design single-stage op-amps with low gain and very high bandwidth. The need for high gain could be satisfied with multiple cascode configurations [3]. However, cascode arrangements are problematic because the low-voltage supply makes the output dynamic range very low. Hence, the only viable possibility is using the cascade of several gain stages. However, compensation becomes difficult and such to significantly reduce the op-amp bandwidth benefit [4]. This work studies the limits on the use of low gain op-amps in discrete-time Σ modulators and discusses a method that avoids the limitations even with gain stages made by a single stage amplifier. Simulation results at behavioral level verify the effectiveness of the proposed method and show the possibility to design high-performance sampled-data Σ modulators with a 65 nm technology and very high sampling rate: 960 MHz with a signal bandwidth of 10 MHz the oversampling ratio, OSR, is as high as 48. Fig. 1. Sampled-data implementation of the integrator. This paper is organized as follows. Section II discusses the main limits of the integrators in discrete-time Σ modulators due to the low gain of amplifiers. Section III illustrates the technique used to compensated for the phase error on integrators. The description of the basic building blocks of the modulator as well as the possible schematic circuits of the opamps and a fully differential unity gain buffer are discussed in Section IV. Section V shows the effectiveness of the proposed technique with simulation results at behavioral level while Section VI concludes the paper. II. FINITE GAIN AND BANDWIDTH LIMIT The basic cell of Σ modulators is the integrator. Its schematic circuit, for sampled-data implementation, is shown in Fig. 1. The analysis of the scheme in time domain leads to [nt + T ] = [nt ] { +C 1 [nt ] V } OUT [nt + T ] that in the z-domain becomes = C C 1 / 1 z C 1/ z showing that the finite gain causes a gain error and a phase error given, respectively, by:

3 X 1st Integrator 1/2 z _ 1-z -1 _ 2nd Integrator z -1 1-z -1 2 ε q ADC FLASH Y C 1 _ DAC1 Fig. 2. DAC2 Conventional second-order Σ architecture. V CM DRIVING PHASES α UGB + Op-Amp G E = +1+ C1 3 P E = C1. 4 For Σ modulators, gain error is not a true limit unless the OSR is very large. On the other hand, phase error causes a Signal to Noise Ratio SNR degradation since the resulting phase-shift moves the zeros of the NTF inside the unit circle. Fig. 2 shows a conventional second-order architecture used here as a test vehicle. The model was implemented and simulated in Matlab Simulink. Fig. 3 compares the obtained output spectra with ideal behavior, considering only gain errors and the overall effect of finite op-amp s gain i.e. including phase and gain errors, as in eq. 2. The simulation shows that with a gain equal to 20 db = 10 for both integrators, the SNR diminishes by just 4 db in the case with only gain error gain. Accounting for the overall error and same gain gives rise to a much larger loss: 11.3 db. The op-amp s speed limits involves both bandwidth, ω T, and slew-rate, SR. The two parameters are related one each other unless the stage uses special techniques to enhance the slew-rate [5]. The link between these parameters for a twostage amplifier, is PSD [db] Fig. 3. Phase and Gain Error Gain Error SR = V GS V T H ω T 5-3 db FS Ideal Behavior SNR = db OSR = 48 Signal Bandwidth = 10 MHz Op-amp Gain = 20 db Frequency [MHz] Output spectrum comparison with Matlab Simulink FFT points. nt Fig. 5. nt+t Proposed gain compensated integrator. where V GS V T H is the overdrive voltage of the input differential pair. Accrodingly, increasing bandwidth also improves the slew-rate performance. The study of the slew-rate and bandwidth limits on the overall Σ performance has been done with behavioral simulations. Results show that for a given clock frequency, f ck, the SNR degradation is negligible if ω T = 3πf ck and SR > 0.6πf ck the overdrive voltage is V GS V T H = 200 mv, the capacitive load C L = 0.5 pf. Therefore, for using very high clock frequencies it is necessary to focus on the op-amp bandwidth and slew-rate. III. GAIN COMPENSATED INTEGRATOR The gain and phase error in a discrete-time integrator as described by equations 3 and 4 occur because during the sampling and the integrating phases the op-amp s analog ground is different from the common mode reference V CM. Since the limit, that depends on the finite gain, is a shift of the inverting input voltage by /A, the resulting error can be compensated for if it is measured and stored for a successive action. This is done in the scheme of Fig. 5 thanks to the use of a unity gain buffer with α gain in the figure, which makes available the voltage from the inverting input during the sampling period of the input voltage, Φ 1. The input capacitor pre-charged to the input voltage minus the error injects its signal into the virtual ground during the next phase. The precharge of the input capacitor is,n + α,n /A 0. At the end of phase Φ 2 it becomes,n+1 /A 0. In the time domain it results { [nt ] [nt ]} = 6 } C 1 { [nt ] + α [nt ] [nt ] which, in the z-domain becomes z = C 1 z z 1 + C11 αz 1 If the gain of the buffer is α = 1, it results

4 V DD V DD R SW M 5 M 3 M 4 M 6 M 3 M 4 M V 7 CMF M 8 RC C C C C RC V IP V IP M 1 M 2 M 1 M 2 V CMF I B M 9 V B1 I V M BN B1 10 a b Fig. 4. Op-amp architectures. a Differential inverter with n-channel and p-channel differential pair. b Conventional two-stage amplifier. z = C 1 z 1 1 z C1 8 that completely cancels the phase error and just leaves the gain error. That is what is needed to eliminate the major source of error. Possibly, the gain error can be compensated for with another additional circuit. The method is not discussed here because the benefit of few db does not worth a further complication of the scheme. Notice that a possible offset of the unity gain buffer corresponds to an additional term of offset of the op-amp. Its effect is irrelevant for the second integrator and can be corrected by digital calibration or with a proper shift of the DACs refences. IV. BUILDING BLOCKS The gain-compensated second-order Σ modulator of Fig. 2 requires two op-amps and two unity gain buffers. Behavioral simulations show that with a clock frequency of 960 MHz it is necessary to ensure a bandwidth, f T, of 3 GHz for the first op-amp and buffer and 2 GHz for the building blocks of the second stage. In order to satisfy very high f T a very simple differential gain stage is necessary. Typically a differential inverter with active load; a scheme that provides limited output dynamic V DD M 5 M 6 range. This is not a serious problem for the first integrator if the Σ modulator uses an analog feedforward at the input of the second stage and multi-bit quantization [6]. The output swing of the first integrator becomes about the quantization noise. On the contrary, since the output swing of the second op-amp is the input amplitude plus the quantization noise, it is necessary to use after the differential pair an output stage made by an inverter with active load, which swing equals the supply voltage minus two overdrives. Fig. 4 shows the simplified op-amp schematics used in the fully differential modulator s implementation. The first amplifier Fig. 4a is a differential inverter with both n- channel and p-channel differential pairs. The resistance R SW shifts the bias voltage of the p-channel sources near the input common mode level V DD /2. A common mode circuit controls the current bias. The scheme of the second op-amp, shown in Fig. 4b, is a conventional two-stage amplifier whit diode connected load in the first stage. The common mode feedback controls the current generator in parallel to the p-channel load of the first stage. For implementing the unity gain buffer there are many solutions published in the literature. The one used by this design is the fully differential scheme of Fig. 6 [7]. The circuit uses class AB output stages to maintain a good drive capability with low output impedance outputs. The control of the currents in the level shifts M 5, M 11 and M 6, M 12 varies the gain of the buffer and, under certain conditions, makes it equal to 1. The common mode circuit controls the current bias of the two input differential pairs. V B2 M 9 M 7 M 8 M 10 V. SIMULATION RESULTS M 13 V B1 M 1 M 2 M 3 M 4 V IP IB V CMF I B M M Fig. 6. Fully differential unity gain buffer. V B1 M 14 The Σ modulator of Fig. 2 has been simulated at behavioral level by using Simulink and a Verilog-A description. For both simulations the models of amplifier and buffer take into account the main features. The DC gain for both, first and second op-amp is equal to 20 db = 10. The bandwidth for the first amplifier and two buffers is 3 GHz while for the second amplifier we use 2 GHz. The modulator runs at a clock frequency of 960 MHz for an expected signal bandwidth of

5 db FS OSR = 48 Signal Bandwidth = 10 MHz SNR [db] SNR ENoB [Bits] PSD [db] DC Gain = 20 db α = SNR = db Ideal DC Gain SNR = db ENoB Gain Buffer α Frequency [MHz] Fig. 7. SNR and ENoB versus the unity gain buffer α. Fig. 8. Output spectra comparison with Cadence FFT points. TABLE I SIMULATED MODULATOR PERFORMANCE Parameter Symbol [Unit] Value Signal Bandwidth B W [MHz] 10 Clock Frequency f ck [MHz] 960 Oversampling Ratio OSR [ ] 48 Bit Quantizer ADC [bit] 3 DC Gain [ ]db st. Op-amp & Buffer BW f T [GHz] 3 2nd. Op-amp Bandwidth f T [GHz] 2 Ideal α=1.0 α=0.975 Signal-to-Noise-Ratio SNR [db] db F S α=0.90 α=0.85 α= MHz OSR = 48. The quantizer of the modulator employs a 3-bit flash converter. Since the buffer s gain, α, is the most critical parameter for the overall performance, the simulations are focused on process, voltage and temperature variations on the buffer s gain. The result show that in the worst case the gain drops at The effect of an inaccurate buffer gain has been analyzed with Simulink for a value of α ranging from 0.8 to 1. Fig. 7 illustrates the SNR and the corresponding Effective Number of Bits ENoB as a function of α. The simulation shows that the SNR loss is about 3 db with α = Cadence simulations give rise to Fig. 8 that compares the output spectra in the ideal and the 20 db case with the proposed op-amp gain compensation technique. The latter also includes the speed limits indicated in Table I. The gain of the buffer is α = With OSR = 48 the ideal expected SNR at -3 db F S of the input signal is 88 db more than 14- bits. The achieved SNR with the real 20 db gain op-amp is just 4.76 db 0.49-bits lower than the ideal behavior, a result that also verifies the Matlab Simulink simulations. Table I summarizes the performance of the modulator for the different cases studied here. VI. CONCLUSIONS A second-order Σ modulator with op-amp gain compensation technique is presented. The proposed solution employs a buffer that reads the gain error caused by the DC gain limit of amplifiers and compensates for the phase error of the SC integrator. The technique allows to use single stages amplifiers with low DC gain and to maximize the bandwidth of the amplifier. Two possible operational amplifiers and a fully differential unity gain buffer circuit has been described. Behavioral simulation results show that a conventional secondorder Σ modulator made by op-amps with just 20 db of gain and op-amp gain compensation technique, attains approximately db bits with α = 0.975; loosing about 0.49-bits respect to the ideal behavior. REFERENCES [1] L. Yao and M. Steyaert and W. Sansen, Low-Power Low-Voltage Sigma- Delta Modulators in Nanometer CMOS. Springer, [2] Franco Maloberti, Data Convertes, Springer, Dordrecht, The Netherlands, [3] J. Raman, P. Rombouts and L. Weyten, Folded-Cascode Amplifier with Efficient Feedforward Gain-Boosting, Electronics Letters, vol. 46, no. 21, pp , October [4] K. N. Leung and P. K. T. Mok, Analysis of Multistage Amplifier- Frequency Compensation, IEEE Transactions on Circuits and Systems-I, vol. 48, no. 9, pp , September [5] A. Pena Perez, Y. B. N. Kumar, E. Bonizzoni and F. Maloberti, Slew- Rate and Gain Enhancement in Two Stage Operational Amplifiers, Proceedings of the IEEE International Symposium on Circuits and Systems ISCAS, pp , May [6] A. Gharbiya and D. A. Johns, On the Implementation of Input- Feedforward Delta-Sigma Modulators, IEEE Transactions on Circuits and Systems-II, vol. 53, no. 6, pp , June [7] A. Soliman and A. Mahmoud and I. A. Awad, Fully Differential CMOS Current Feedback Operational Amplifier, Analog Integrated Circuits and Signal Processing, vol. 43, no.1, pp , April 2005.

Performance Enhanced Op- Amp for 65nm CMOS Technologies and Below

Performance Enhanced Op- Amp for 65nm CMOS Technologies and Below Aldo Pena Perez and F. Maloberti, Performance Enhanced Op- Amp for 65nm CMOS Technologies and Below, IEEE Proceeding of the International Symposium on Circuits and Systems, pp. 21 24, May 212. 2xx IEEE.

More information

Band- Pass ΣΔ Architectures with Single and Two Parallel Paths

Band- Pass ΣΔ Architectures with Single and Two Parallel Paths H. Caracciolo, I. Galdi, E. Bonizzoni, F. Maloberti: "Band-Pass ΣΔ Architectures with Single and Two Parallel Paths"; IEEE Int. Symposium on Circuits and Systems, ISCAS 8, Seattle, 18-21 May 8, pp. 1656-1659.

More information

Integrated Microsystems Laboratory. Franco Maloberti

Integrated Microsystems Laboratory. Franco Maloberti University of Pavia Integrated Microsystems Laboratory Power Efficient Data Convertes Franco Maloberti franco.maloberti@unipv.it OUTLINE Introduction Managing the noise power budget Challenges of State-of-the-art

More information

Two- Path Band- Pass Σ- Δ Modulator with 40- MHz IF 72- db DR at 1- MHz Bandwidth Consuming 16 mw

Two- Path Band- Pass Σ- Δ Modulator with 40- MHz IF 72- db DR at 1- MHz Bandwidth Consuming 16 mw I. Galdi, E. Bonizzoni, F. Maloberti, G. Manganaro, P. Malcovati: "Two-Path Band- Pass Σ-Δ Modulator with 40-MHz IF 72-dB DR at 1-MHz Bandwidth Consuming 16 mw"; 33rd European Solid State Circuits Conf.,

More information

Low- Power Third- Order ΣΔ Modulator with Cross Couple Paths for WCDMA Applications

Low- Power Third- Order ΣΔ Modulator with Cross Couple Paths for WCDMA Applications C. Della Fiore, F. Maloberti, P. Malcovati: "Low-Power Third-Order ΣΔ Modulator with Cross Couple Paths for WCDMA Applications"; Ph. D. Research in Microelectronics and Electronics, PRIME 2006, Otranto,

More information

Architectures and Design Methodologies for Very Low Power and Power Effective A/D Sigma-Delta Converters

Architectures and Design Methodologies for Very Low Power and Power Effective A/D Sigma-Delta Converters 0 Architectures and Design Methodologies for Very Low Power and Power Effective A/D Sigma-Delta Converters F. Maloberti University of Pavia - Italy franco.maloberti@unipv.it 1 Introduction Summary Sigma-Delta

More information

ECE 627 Project: Design of a High-Speed Delta-Sigma A/D Converter

ECE 627 Project: Design of a High-Speed Delta-Sigma A/D Converter ECE 627 Project: Design of a High-Speed Delta-Sigma A/D Converter Brian L. Young youngbr@eecs.oregonstate.edu Oregon State University June 6, 28 I. INTRODUCTION The goal of the Spring 28, ECE 627 project

More information

Fractional- N PLL with 90 Phase Shift Lock and Active Switched- Capacitor Loop Filter

Fractional- N PLL with 90 Phase Shift Lock and Active Switched- Capacitor Loop Filter J. Park, F. Maloberti: "Fractional-N PLL with 90 Phase Shift Lock and Active Switched-Capacitor Loop Filter"; Proc. of the IEEE Custom Integrated Circuits Conference, CICC 2005, San Josè, 21 September

More information

Data Converters. Springer FRANCO MALOBERTI. Pavia University, Italy

Data Converters. Springer FRANCO MALOBERTI. Pavia University, Italy Data Converters by FRANCO MALOBERTI Pavia University, Italy Springer Contents Dedicat ion Preface 1. BACKGROUND ELEMENTS 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 The Ideal Data Converter Sampling 1.2.1 Undersampling

More information

Time- interleaved sigma- delta modulator using output prediction scheme

Time- interleaved sigma- delta modulator using output prediction scheme K.- S. Lee, F. Maloberti: "Time-interleaved sigma-delta modulator using output prediction scheme"; IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 51, Issue 10, Oct. 2004, pp. 537-541.

More information

Publication [P3] By choosing to view this document, you agree to all provisions of the copyright laws protecting it.

Publication [P3] By choosing to view this document, you agree to all provisions of the copyright laws protecting it. Publication [P3] Copyright c 2006 IEEE. Reprinted, with permission, from Proceedings of IEEE International Solid-State Circuits Conference, Digest of Technical Papers, 5-9 Feb. 2006, pp. 488 489. This

More information

An 11 Bit Sub- Ranging SAR ADC with Input Signal Range of Twice Supply Voltage

An 11 Bit Sub- Ranging SAR ADC with Input Signal Range of Twice Supply Voltage D. Aksin, M.A. Al- Shyoukh, F. Maloberti: "An 11 Bit Sub-Ranging SAR ADC with Input Signal Range of Twice Supply Voltage"; IEEE International Symposium on Circuits and Systems, ISCAS 2007, New Orleans,

More information

3 rd order Sigma-delta modulator with delayed feed-forward path for low-power applications

3 rd order Sigma-delta modulator with delayed feed-forward path for low-power applications 3 rd order Sigma-delta modulator with delayed feed-forward path for low-power applications Min-woong Lee, Seong-ik Cho Electronic Engineering Chonbuk National University 567 Baekje-daero, deokjin-gu, Jeonju-si,

More information

Design of Continuous Time Multibit Sigma Delta ADC for Next Generation Wireless Applications

Design of Continuous Time Multibit Sigma Delta ADC for Next Generation Wireless Applications RESEARCH ARTICLE OPEN ACCESS Design of Continuous Time Multibit Sigma Delta ADC for Next Generation Wireless Applications Sharon Theresa George*, J. Mangaiyarkarasi** *(Department of Information and Communication

More information

Two- Path Delay Line Based Quadrature Band- Pass ΣΔ Modulator

Two- Path Delay Line Based Quadrature Band- Pass ΣΔ Modulator Y.B. Nithin Kumar, E. Bonizzoni, A. Patra, F. Maloberti: "TwoPath Delay Line Based Quadrature BandPass ΣΔ Modulator"; IEEJ International Analog VLSI Workshop, Bali, 2 4 November 211, pp. 65 69. 2xx IEEE.

More information

Second-Order Sigma-Delta Modulator in Standard CMOS Technology

Second-Order Sigma-Delta Modulator in Standard CMOS Technology SERBIAN JOURNAL OF ELECTRICAL ENGINEERING Vol. 1, No. 3, November 2004, 37-44 Second-Order Sigma-Delta Modulator in Standard CMOS Technology Dragiša Milovanović 1, Milan Savić 1, Miljan Nikolić 1 Abstract:

More information

A new class AB folded-cascode operational amplifier

A new class AB folded-cascode operational amplifier A new class AB folded-cascode operational amplifier Mohammad Yavari a) Integrated Circuits Design Laboratory, Department of Electrical Engineering, Amirkabir University of Technology, Tehran, Iran a) myavari@aut.ac.ir

More information

MASH 2-1 MULTI-BIT SIGMA-DELTA MODULATOR FOR WLAN L 2 ( ) ( ) 1( 1 1 1

MASH 2-1 MULTI-BIT SIGMA-DELTA MODULATOR FOR WLAN L 2 ( ) ( ) 1( 1 1 1 MASH 2- MULTI-BIT SIGMA-DELTA MODULATOR FOR WLAN Yu hang, Ning Xie, Hui Wang and Yejun He College of Information Engineering, Shenzhen University, Shenzhen, Guangdong 58060, China kensouren@yahoo.com.cn

More information

Design and Implementation of a Sigma Delta ADC By: Moslem Rashidi, March 2009

Design and Implementation of a Sigma Delta ADC By: Moslem Rashidi, March 2009 Design and Implementation of a Sigma Delta ADC By: Moslem Rashidi, March 2009 Introduction The first thing in design an ADC is select architecture of ADC that is depend on parameters like bandwidth, resolution,

More information

CHAPTER. delta-sigma modulators 1.0

CHAPTER. delta-sigma modulators 1.0 CHAPTER 1 CHAPTER Conventional delta-sigma modulators 1.0 This Chapter presents the traditional first- and second-order DSM. The main sources for non-ideal operation are described together with some commonly

More information

On the Design of Single- Inductor Multiple- Output DC- DC Buck Converters

On the Design of Single- Inductor Multiple- Output DC- DC Buck Converters M. Belloni, E. Bonizzoni, F. Maloberti: "On the Design of Single-Inductor Multiple-Output DC-DC Buck Converters"; IEEE Int. Symposium on Circuits and Systems, ISCAS 2008, Seattle, 18-21 May 2008, pp. 3049-3052.

More information

A 35 fj 10b 160 MS/s Pipelined- SAR ADC with Decoupled Flip- Around MDAC and Self- Embedded Offset Cancellation

A 35 fj 10b 160 MS/s Pipelined- SAR ADC with Decoupled Flip- Around MDAC and Self- Embedded Offset Cancellation Y. Zu, C.- H. Chan, S.- W. Sin, S.- P. U, R.P. Martins, F. Maloberti: "A 35 fj 10b 160 MS/s Pipelined-SAR ADC with Decoupled Flip-Around MDAC and Self- Embedded Offset Cancellation"; IEEE Asian Solid-

More information

A Two- Bit- per- Cycle Successive- Approximation ADC with Background Offset Calibration

A Two- Bit- per- Cycle Successive- Approximation ADC with Background Offset Calibration M. Casubolo, M. Grassi, A. Lombardi, F. Maloberti, P. Malcovati: "A Two-Bit-per- Cycle Successive-Approximation ADC with Background Calibration"; 15th IEEE Int. Conf. on Electronics, Circuits and Systems,

More information

A PSEUDO-CLASS-AB TELESCOPIC-CASCODE OPERATIONAL AMPLIFIER

A PSEUDO-CLASS-AB TELESCOPIC-CASCODE OPERATIONAL AMPLIFIER A PSEUDO-CLASS-AB TELESCOPIC-CASCODE OPERATIONAL AMPLIFIER M. Taherzadeh-Sani, R. Lotfi, and O. Shoaei ABSTRACT A novel class-ab architecture for single-stage operational amplifiers is presented. The structure

More information

RELAXED TIMING ISSUE IN GLOBAL FEEDBACK PATHS OF UNITY- STF SMASH SIGMA DELTA MODULATOR ARCHITECTURE

RELAXED TIMING ISSUE IN GLOBAL FEEDBACK PATHS OF UNITY- STF SMASH SIGMA DELTA MODULATOR ARCHITECTURE RELAXED TIMING ISSUE IN GLOBAL FEEDBACK PATHS OF UNITY- STF SMASH SIGMA DELTA MODULATOR ARCHITECTURE Mehdi Taghizadeh and Sirus Sadughi Department of Electrical Engineering, Science and Research Branch,

More information

Sigma-Delta ADC Tutorial and Latest Development in 90 nm CMOS for SoC

Sigma-Delta ADC Tutorial and Latest Development in 90 nm CMOS for SoC Sigma-Delta ADC Tutorial and Latest Development in 90 nm CMOS for SoC Jinseok Koh Wireless Analog Technology Center Texas Instruments Inc. Dallas, TX Outline Fundamentals for ADCs Over-sampling and Noise

More information

Design of Pipeline Analog to Digital Converter

Design of Pipeline Analog to Digital Converter Design of Pipeline Analog to Digital Converter Vivek Tripathi, Chandrajit Debnath, Rakesh Malik STMicroelectronics The pipeline analog-to-digital converter (ADC) architecture is the most popular topology

More information

Low-Voltage Low-Power Switched-Current Circuits and Systems

Low-Voltage Low-Power Switched-Current Circuits and Systems Low-Voltage Low-Power Switched-Current Circuits and Systems Nianxiong Tan and Sven Eriksson Dept. of Electrical Engineering Linköping University S-581 83 Linköping, Sweden Abstract This paper presents

More information

ECE626 Project Switched Capacitor Filter Design

ECE626 Project Switched Capacitor Filter Design ECE626 Project Switched Capacitor Filter Design Hari Prasath Venkatram Contents I Introduction 2 II Choice of Topology 2 III Poles and Zeros 2 III-ABilinear Transform......................................

More information

Advanced Operational Amplifiers

Advanced Operational Amplifiers IsLab Analog Integrated Circuit Design OPA2-47 Advanced Operational Amplifiers כ Kyungpook National University IsLab Analog Integrated Circuit Design OPA2-1 Advanced Current Mirrors and Opamps Two-stage

More information

Design for MOSIS Education Program

Design for MOSIS Education Program Design for MOSIS Education Program (Research) T46C-AE Project Title Low Voltage Analog Building Block Prepared by: C. Durisety, S. Chen, B. Blalock, S. Islam Institution: Department of Electrical and Computer

More information

Data Conversion Techniques (DAT115)

Data Conversion Techniques (DAT115) Data Conversion Techniques (DAT115) Hand in Report Second Order Sigma Delta Modulator with Interleaving Scheme Group 14N Remzi Yagiz Mungan, Christoffer Holmström [ 1 20 ] Contents 1. Task Description...

More information

A Compact 2.4V Power-efficient Rail-to-rail Operational Amplifier. Strong inversion operation stops a proposed compact 3V power-efficient

A Compact 2.4V Power-efficient Rail-to-rail Operational Amplifier. Strong inversion operation stops a proposed compact 3V power-efficient A Compact 2.4V Power-efficient Rail-to-rail Operational Amplifier Abstract Strong inversion operation stops a proposed compact 3V power-efficient rail-to-rail Op-Amp from a lower total supply voltage.

More information

Very low- power Sampled- data Σ- Δ Architectures for wireline and wireless applications

Very low- power Sampled- data Σ- Δ Architectures for wireline and wireless applications F. Maloberti: "Very lowpower ampleddata Δ Architectures for wireline and wireless applications"; Proc. of nd IEEE International ymposium on Communications, Control and ignal Processing, ICCP 006, Marrakech,

More information

A Low- Power Multi- bit ΣΔ Modulator in 90- nm Digital CMOS without DEM

A Low- Power Multi- bit ΣΔ Modulator in 90- nm Digital CMOS without DEM J. Yu, F. Maloberti: "A Low-Power Multi-bit ΣΔ Modulator in 90-nm Digital CMOS without DEM"; IEEE Journal of Solid State Circuits, Vol. 40, Issue 12, December 2005, pp. 2428-2436. 20xx IEEE. Personal use

More information

EE247 Lecture 24. EE247 Lecture 24

EE247 Lecture 24. EE247 Lecture 24 EE247 Lecture 24 Administrative EE247 Final exam: Date: Wed. Dec. 15 th Time: -12:30pm-3:30pm- Location: 289 Cory Closed book/course notes No calculators/cell phones/pdas/computers Bring one 8x11 paper

More information

A Novel Continuous-Time Common-Mode Feedback for Low-Voltage Switched-OPAMP

A Novel Continuous-Time Common-Mode Feedback for Low-Voltage Switched-OPAMP 10.4 A Novel Continuous-Time Common-Mode Feedback for Low-oltage Switched-OPAMP M. Ali-Bakhshian Electrical Engineering Dept. Sharif University of Tech. Azadi Ave., Tehran, IRAN alibakhshian@ee.sharif.edu

More information

[Kumar, 2(9): September, 2013] ISSN: Impact Factor: 1.852

[Kumar, 2(9): September, 2013] ISSN: Impact Factor: 1.852 IJESRT INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY Design and Performance analysis of Low power CMOS Op-Amp Anand Kumar Singh *1, Anuradha 2, Dr. Vijay Nath 3 *1,2 Department of

More information

EE247 Lecture 26. This lecture is taped on Wed. Nov. 28 th due to conflict of regular class hours with a meeting

EE247 Lecture 26. This lecture is taped on Wed. Nov. 28 th due to conflict of regular class hours with a meeting EE47 Lecture 6 This lecture is taped on Wed. Nov. 8 th due to conflict of regular class hours with a meeting Any questions regarding this lecture could be discussed during regular office hours or in class

More information

Low-Power Pipelined ADC Design for Wireless LANs

Low-Power Pipelined ADC Design for Wireless LANs Low-Power Pipelined ADC Design for Wireless LANs J. Arias, D. Bisbal, J. San Pablo, L. Quintanilla, L. Enriquez, J. Vicente, J. Barbolla Dept. de Electricidad y Electrónica, E.T.S.I. de Telecomunicación,

More information

Design of Rail-to-Rail Op-Amp in 90nm Technology

Design of Rail-to-Rail Op-Amp in 90nm Technology IJSTE - International Journal of Science Technology & Engineering Volume 1 Issue 2 August 2014 ISSN(online) : 2349-784X Design of Rail-to-Rail Op-Amp in 90nm Technology P R Pournima M.Tech Electronics

More information

A Novel Implementation of Dithered Digital Delta-Sigma Modulators via Bus-Splitting

A Novel Implementation of Dithered Digital Delta-Sigma Modulators via Bus-Splitting B. Fitzgibbon, M.P. Kennedy, F. Maloberti: "A Novel Implementation of Dithered Digital Delta- Sigma Modulators via Bus- Splitting"; IEEE International Symposium on Circuits, ISCAS 211, Rio de Janeiro,

More information

The Baker ADC An Overview Kaijun Li, Vishal Saxena, and Jake Baker

The Baker ADC An Overview Kaijun Li, Vishal Saxena, and Jake Baker The Baker ADC An Overview Kaijun Li, Vishal Saxena, and Jake Baker An ADC made using the K-Delta-1-Sigma modulator, invented by R. Jacob Baker in 2008, and a digital filter is called a Baker ADC or Baker

More information

d. Can you find intrinsic gain more easily by examining the equation for current? Explain.

d. Can you find intrinsic gain more easily by examining the equation for current? Explain. EECS140 Final Spring 2017 Name SID 1. [8] In a vacuum tube, the plate (or anode) current is a function of the plate voltage (output) and the grid voltage (input). I P = k(v P + µv G ) 3/2 where µ is a

More information

Performance Analysis of Low Power, High Gain Operational Amplifier Using CMOS VLSI Design

Performance Analysis of Low Power, High Gain Operational Amplifier Using CMOS VLSI Design RESEARCH ARTICLE OPEN ACCESS Performance Analysis of Low Power, High Gain Operational Amplifier Using CMOS VLSI Design Ankush S. Patharkar*, Dr. Shirish M. Deshmukh** *(Department of Electronics and Telecommunication,

More information

Combining Multipath and Single-Path Time-Interleaved Delta-Sigma Modulators Ahmed Gharbiya and David A. Johns

Combining Multipath and Single-Path Time-Interleaved Delta-Sigma Modulators Ahmed Gharbiya and David A. Johns 1224 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 55, NO. 12, DECEMBER 2008 Combining Multipath and Single-Path Time-Interleaved Delta-Sigma Modulators Ahmed Gharbiya and David A.

More information

Oversampling Converters

Oversampling Converters Oversampling Converters Behzad Razavi Electrical Engineering Department University of California, Los Angeles Outline Basic Concepts First- and Second-Order Loops Effect of Circuit Nonidealities Cascaded

More information

DESIGN OF MULTI-BIT DELTA-SIGMA A/D CONVERTERS

DESIGN OF MULTI-BIT DELTA-SIGMA A/D CONVERTERS DESIGN OF MULTI-BIT DELTA-SIGMA A/D CONVERTERS DESIGN OF MULTI-BIT DELTA-SIGMA A/D CONVERTERS by Yves Geerts Alcatel Microelectronics, Belgium Michiel Steyaert KU Leuven, Belgium and Willy Sansen KU Leuven,

More information

DESIGN OF A NOVEL CURRENT MIRROR BASED DIFFERENTIAL AMPLIFIER DESIGN WITH LATCH NETWORK. Thota Keerthi* 1, Ch. Anil Kumar 2

DESIGN OF A NOVEL CURRENT MIRROR BASED DIFFERENTIAL AMPLIFIER DESIGN WITH LATCH NETWORK. Thota Keerthi* 1, Ch. Anil Kumar 2 ISSN 2277-2685 IJESR/October 2014/ Vol-4/Issue-10/682-687 Thota Keerthi et al./ International Journal of Engineering & Science Research DESIGN OF A NOVEL CURRENT MIRROR BASED DIFFERENTIAL AMPLIFIER DESIGN

More information

A New Design Technique of CMOS Current Feed Back Operational Amplifier (CFOA)

A New Design Technique of CMOS Current Feed Back Operational Amplifier (CFOA) Circuits and Systems, 2013, 4, 11-15 http://dx.doi.org/10.4236/cs.2013.41003 Published Online January 2013 (http://www.scirp.org/journal/cs) A New Design Technique of CMOS Current Feed Back Operational

More information

Rail-To-Rail Output Op-Amp Design with Negative Miller Capacitance Compensation

Rail-To-Rail Output Op-Amp Design with Negative Miller Capacitance Compensation Rail-To-Rail Op-Amp Design with Negative Miller Capacitance Compensation Muhaned Zaidi, Ian Grout, Abu Khari bin A ain Abstract In this paper, a two-stage op-amp design is considered using both Miller

More information

LOW-POWER CHARGE-PUMP BASED SWITCHED-CAPACITOR CIRCUITS. Alireza Nilchi

LOW-POWER CHARGE-PUMP BASED SWITCHED-CAPACITOR CIRCUITS. Alireza Nilchi LOW-POWER CHARGE-PUMP BASED SWITCHED-CAPACITOR CIRCUITS by Alireza Nilchi A thesis submitted in conformity with the requirements for the degree of Doctor of Philosophy Graduate Department of Electrical

More information

AN increasing number of video and communication applications

AN increasing number of video and communication applications 1470 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 9, SEPTEMBER 1997 A Low-Power, High-Speed, Current-Feedback Op-Amp with a Novel Class AB High Current Output Stage Jim Bales Abstract A complementary

More information

Cascaded Noise-Shaping Modulators for Oversampled Data Conversion

Cascaded Noise-Shaping Modulators for Oversampled Data Conversion Cascaded Noise-Shaping Modulators for Oversampled Data Conversion Bruce A. Wooley Stanford University B. Wooley, Stanford, 2004 1 Outline Oversampling modulators for A/D conversion Cascaded noise-shaping

More information

VIRTUAL TEST BENCH FOR DESIGN AND SIMULATION OF DATA CONVERTERS

VIRTUAL TEST BENCH FOR DESIGN AND SIMULATION OF DATA CONVERTERS VIRTUAL TEST BENCH FOR DESIGN AND SIMULATION OF DATA CONVERTERS P. Est~ada, F. Malobed 1.. Texas A&M University, College Station, Texas, USA. 2. University of Pavia, Pavia, Italy and University of Texas

More information

System Level Design of a Continuous-Time Delta-Sigma Modulator for Portable Ultrasound Scanners

System Level Design of a Continuous-Time Delta-Sigma Modulator for Portable Ultrasound Scanners Downloaded from orbit.dtu.dk on: Jul 23, 2018 System Level Design of a Continuous-Time Delta-Sigma Modulator for Portable Ultrasound Scanners Llimos Muntal, Pere; Færch, Kjartan; Jørgensen, Ivan Harald

More information

A K-Delta-1-Sigma Modulator for Wideband Analog-to-Digital Conversion

A K-Delta-1-Sigma Modulator for Wideband Analog-to-Digital Conversion A K-Delta-1-Sigma Modulator for Wideband Analog-to-Digital Conversion Abstract : R. Jacob Baker and Vishal Saxena Department of Electrical and Computer Engineering Boise State University jbaker@boisestate.edu

More information

Design of Miller Compensated Two-Stage Operational Amplifier for Data Converter Applications

Design of Miller Compensated Two-Stage Operational Amplifier for Data Converter Applications Design of Miller Compensated Two-Stage Operational Amplifier for Data Converter Applications Prema Kumar. G Shravan Kudikala Casest, School Of Physics Casest, School Of Physics University Of Hyderabad

More information

Design and Analysis of Two-Stage Op-Amp in 0.25µm CMOS Technology

Design and Analysis of Two-Stage Op-Amp in 0.25µm CMOS Technology Design and Analysis of Two-Stage Op-Amp in 0.25µm CMOS Technology 1 SagarChetani 1, JagveerVerma 2 Department of Electronics and Tele-communication Engineering, Choukasey Engineering College, Bilaspur

More information

Final Exam Spring 2012

Final Exam Spring 2012 1 EE 435 Final Exam Spring 2012 Name Instructions: This is an open-book, open-notes, open computer exam but no collaboration either personal or electronic with anyone except the course instructor is permitted.

More information

BandPass Sigma-Delta Modulator for wideband IF signals

BandPass Sigma-Delta Modulator for wideband IF signals BandPass Sigma-Delta Modulator for wideband IF signals Luca Daniel (University of California, Berkeley) Marco Sabatini (STMicroelectronics Berkeley Labs) maintain the same advantages of BaseBand converters

More information

A Switched-Capacitor Band-Pass Biquad Filter Using a Simple Quasi-unity Gain Amplifier

A Switched-Capacitor Band-Pass Biquad Filter Using a Simple Quasi-unity Gain Amplifier A Switched-Capacitor Band-Pass Biquad Filter Using a Simple Quasi-unity Gain Amplifier Hugo Serra, Nuno Paulino, and João Goes Centre for Technologies and Systems (CTS) UNINOVA Dept. of Electrical Engineering

More information

A Unity Gain Fully-Differential 10bit and 40MSps Sample-And-Hold Amplifier in 0.18μm CMOS

A Unity Gain Fully-Differential 10bit and 40MSps Sample-And-Hold Amplifier in 0.18μm CMOS A Unity Gain Fully-Differential 0bit and 40MSps Sample-And-Hold Amplifier in 0.8μm CMOS Sanaz Haddadian, and Rahele Hedayati Abstract A 0bit, 40 MSps, sample and hold, implemented in 0.8-μm CMOS technology

More information

G m /I D based Three stage Operational Amplifier Design

G m /I D based Three stage Operational Amplifier Design G m /I D based Three stage Operational Amplifier Design Rishabh Shukla SVNIT, Surat shuklarishabh31081988@gmail.com Abstract A nested Gm-C compensated three stage Operational Amplifier is reviewed using

More information

ADVANCES in VLSI technology result in manufacturing

ADVANCES in VLSI technology result in manufacturing INTL JOURNAL OF ELECTRONICS AND TELECOMMUNICATIONS, 2013, VOL. 59, NO. 1, PP. 99 104 Manuscript received January 8, 2013; revised March, 2013. DOI: 10.2478/eletel-2013-0012 Rapid Prototyping of Third-Order

More information

Revision History. Contents

Revision History. Contents Revision History Ver. # Rev. Date Rev. By Comment 0.0 9/15/2012 Initial draft 1.0 9/16/2012 Remove class A part 2.0 9/17/2012 Comments and problem 2 added 3.0 10/3/2012 cmdmprobe re-simulation, add supplement

More information

A stability-improved single-opamp third-order ΣΔ modulator by using a fully-passive noise-shaping SAR ADC and passive adder

A stability-improved single-opamp third-order ΣΔ modulator by using a fully-passive noise-shaping SAR ADC and passive adder A stability-improved single-opamp third-order ΣΔ modulator by using a fully-passive noise-shaping SAR ADC and passive adder Zhijie Chen, Masaya Miyahara, and Akira Matsuzawa Tokyo Institute of Technology,

More information

THE USE of multibit quantizers in oversampling analogto-digital

THE USE of multibit quantizers in oversampling analogto-digital 966 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 57, NO. 12, DECEMBER 2010 A New DAC Mismatch Shaping Technique for Sigma Delta Modulators Mohamed Aboudina, Member, IEEE, and Behzad

More information

Design of High Gain Two stage Op-Amp using 90nm Technology

Design of High Gain Two stage Op-Amp using 90nm Technology Design of High Gain Two stage Op-Amp using 90nm Technology Shaik Aqeel 1, P. Krishna Deva 2, C. Mahesh Babu 3 and R.Ganesh 4 1 CVR College of Engineering/UG Student, Hyderabad, India 2 CVR College of Engineering/UG

More information

A 12-bit Interpolated Pipeline ADC using Body Voltage Controlled Amplifier

A 12-bit Interpolated Pipeline ADC using Body Voltage Controlled Amplifier A 12-bit Interpolated Pipeline ADC using Body Voltage Controlled Amplifier Hyunui Lee, Masaya Miyahara, and Akira Matsuzawa Tokyo Institute of Technology, Japan Outline Background Body voltage controlled

More information

An Improved Recycling Folded Cascode OTA with positive feedback

An Improved Recycling Folded Cascode OTA with positive feedback An Improved Recycling Folded Cascode OTA with positive feedback S.KUMARAVEL, B.VENKATARAMANI Department of Electronics and Communication Engineering National Institute of Technology Trichy Tiruchirappalli

More information

On the Study of Improving Noise Shaping Techniques in Wide Bandwidth Sigma Delta Modulators

On the Study of Improving Noise Shaping Techniques in Wide Bandwidth Sigma Delta Modulators On the Study of Improving Noise Shaping Techniques in Wide Bandwidth Sigma Delta Modulators By Du Yun Master Degree in Electrical and Electronics Engineering 2013 Faculty of Science and Technology University

More information

Lecture 3 Switched-Capacitor Circuits Trevor Caldwell

Lecture 3 Switched-Capacitor Circuits Trevor Caldwell Advanced Analog Circuits Lecture 3 Switched-Capacitor Circuits Trevor Caldwell trevor.caldwell@analog.com Lecture Plan Date Lecture (Wednesday 2-4pm) Reference Homework 2017-01-11 1 MOD1 & MOD2 ST 2, 3,

More information

Improved SNR Integrator Design with Feedback Compensation for Modulator

Improved SNR Integrator Design with Feedback Compensation for Modulator Improved SNR Integrator Design with Feedback Compensation for Modulator 1 Varun Mishra, 2 Abhishek Bora, 3 Vishal Ramola 1 M.Tech Student, 2 M.Tech Student, 3 Assistant Professor 1 VLSI Design, 1 Faculty

More information

University of Michigan, EECS413 Final project. A High Speed Operational Amplifier. 1. A High Speed Operational Amplifier

University of Michigan, EECS413 Final project. A High Speed Operational Amplifier. 1. A High Speed Operational Amplifier University of Michigan, EECS413 Final project. A High Speed Operational Amplifier. 1 A High Speed Operational Amplifier A. Halim El-Saadi, Mohammed El-Tanani, University of Michigan Abstract This paper

More information

EE247 Lecture 26. EE247 Lecture 26

EE247 Lecture 26. EE247 Lecture 26 EE247 Lecture 26 Administrative EE247 Final exam: Date: Mon. Dec. 18 th Time: 12:30pm-3:30pm Location: 241 Cory Hall Extra office hours: Thurs. Dec. 14 th, 10:30am-12pm Closed book/course notes No calculators/cell

More information

DAT175: Topics in Electronic System Design

DAT175: Topics in Electronic System Design DAT175: Topics in Electronic System Design Analog Readout Circuitry for Hearing Aid in STM90nm 21 February 2010 Remzi Yagiz Mungan v1.10 1. Introduction In this project, the aim is to design an adjustable

More information

Chapter 12 Opertational Amplifier Circuits

Chapter 12 Opertational Amplifier Circuits 1 Chapter 12 Opertational Amplifier Circuits Learning Objectives 1) The design and analysis of the two basic CMOS op-amp architectures: the two-stage circuit and the single-stage, folded cascode circuit.

More information

Design of an Assembly Line Structure ADC

Design of an Assembly Line Structure ADC Design of an Assembly Line Structure ADC Chen Hu 1, Feng Xie 1,Ming Yin 1 1 Department of Electronic Engineering, Naval University of Engineering, Wuhan, China Abstract This paper presents a circuit design

More information

Design of a Sample and Hold Circuit using Rail to Rail Low Voltage Compact Operational Amplifier and bootstrap Switching

Design of a Sample and Hold Circuit using Rail to Rail Low Voltage Compact Operational Amplifier and bootstrap Switching RESEARCH ARTICLE OPEN ACCESS Design of a Sample and Hold Circuit using Rail to Rail Low Voltage Compact Operational Amplifier and bootstrap Switching Annu Saini, Prity Yadav (M.Tech. Student, Department

More information

Analysis and Design of Analog Integrated Circuits Lecture 20. Advanced Opamp Topologies (Part II)

Analysis and Design of Analog Integrated Circuits Lecture 20. Advanced Opamp Topologies (Part II) Analysis and Design of Analog Integrated Circuits Lecture 20 Advanced Opamp Topologies (Part II) Michael H. Perrott April 15, 2012 Copyright 2012 by Michael H. Perrott All rights reserved. Outline of Lecture

More information

MODELING BAND-PASS SIGMA-DELTA MODULATORS IN SIMULINK

MODELING BAND-PASS SIGMA-DELTA MODULATORS IN SIMULINK Vienna, AUSTRIA, 000, Septemer 5-8 MODELING BAND-PASS SIGMA-DELTA MODULATORS IN SIMULINK S. Brigati (), F. Francesconi (), P. Malcovati () and F. Maloerti (3) () Dep. of Electrical Engineering, University

More information

A 2.5 V 109 db DR ADC for Audio Application

A 2.5 V 109 db DR ADC for Audio Application 276 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.10, NO.4, DECEMBER, 2010 A 2.5 V 109 db DR ADC for Audio Application Gwangyol Noh and Gil-Cho Ahn Abstract A 2.5 V feed-forward second-order deltasigma

More information

Lecture 2: Non-Ideal Amps and Op-Amps

Lecture 2: Non-Ideal Amps and Op-Amps Lecture 2: Non-Ideal Amps and Op-Amps Prof. Ali M. Niknejad Department of EECS University of California, Berkeley Practical Op-Amps Linear Imperfections: Finite open-loop gain (A 0 < ) Finite input resistance

More information

Low- Power 6- Bit Flash ADC for High- Speed Data Converters Architectures

Low- Power 6- Bit Flash ADC for High- Speed Data Converters Architectures V. Ferragina, N. Ghittori, F. Maloberti: "Low-Power 6-Bit Flash ADC for High- Speed Data Converters Architectures"; IEEE International Symposium on Circuits and Systems, ISCAS 2006, Kos, 21-24 May 2006,

More information

Improved offline calibration for DAC mismatch in low OSR Sigma Delta ADCs with distributed feedback

Improved offline calibration for DAC mismatch in low OSR Sigma Delta ADCs with distributed feedback Improved offline calibration for DAC mismatch in low OSR Sigma Delta ADCs with distributed feedback Maarten De Bock, Amir Babaie-Fishani and Pieter Rombouts This document is an author s draft version submitted

More information

Design and Simulation of an Operational Amplifier with High Gain and Bandwidth for Switched Capacitor Filters

Design and Simulation of an Operational Amplifier with High Gain and Bandwidth for Switched Capacitor Filters IOSR Journal of Electrical and Electronics Engineering (IOSR-JEEE) e-issn: 2278-1676,p-ISSN: 2320-3331, Volume 11, Issue 1 Ver. II (Jan. Feb. 2016), PP 47-53 www.iosrjournals.org Design and Simulation

More information

Chapter 9: Operational Amplifiers

Chapter 9: Operational Amplifiers Chapter 9: Operational Amplifiers The Operational Amplifier (or op-amp) is the ideal, simple amplifier. It is an integrated circuit (IC). An IC contains many discrete components (resistors, capacitors,

More information

Lecture #6: Analog-to-Digital Converter

Lecture #6: Analog-to-Digital Converter Lecture #6: Analog-to-Digital Converter All electrical signals in the real world are analog, and their waveforms are continuous in time. Since most signal processing is done digitally in discrete time,

More information

TWO AND ONE STAGES OTA

TWO AND ONE STAGES OTA TWO AND ONE STAGES OTA F. Maloberti Department of Electronics Integrated Microsystem Group University of Pavia, 7100 Pavia, Italy franco@ele.unipv.it tel. +39-38-50505; fax. +39-038-505677 474 EE Department

More information

ISSCC 2006 / SESSION 16 / MEMS AND SENSORS / 16.1

ISSCC 2006 / SESSION 16 / MEMS AND SENSORS / 16.1 16.1 A 4.5mW Closed-Loop Σ Micro-Gravity CMOS-SOI Accelerometer Babak Vakili Amini, Reza Abdolvand, Farrokh Ayazi Georgia Institute of Technology, Atlanta, GA Recently, there has been an increasing demand

More information

Analysis of the system level design of a 1.5 bit/stage pipeline ADC 1 Amit Kumar Tripathi, 2 Rishi Singhal, 3 Anurag Verma

Analysis of the system level design of a 1.5 bit/stage pipeline ADC 1 Amit Kumar Tripathi, 2 Rishi Singhal, 3 Anurag Verma 014 Fourth International Conference on Advanced Computing & Communication Technologies Analysis of the system level design of a 1.5 bit/stage pipeline ADC 1 Amit Kumar Tripathi, Rishi Singhal, 3 Anurag

More information

Design Examples. MEAD March Richard Schreier. ANALOG DEVICES R. SCHREIER ANALOG DEVICES, INC.

Design Examples. MEAD March Richard Schreier. ANALOG DEVICES R. SCHREIER ANALOG DEVICES, INC. Design Examples MEAD March 008 Richard Schreier Richard.Schreier@analog.com ANALOG DEVICES Catalog nd -Order Lowpass Architecture: Single-bit, switched-capacitor Application: General-purpose, low-frequency

More information

Improved Modeling of Sigma- Delta Modulator Non- Idealities in SIMULINK

Improved Modeling of Sigma- Delta Modulator Non- Idealities in SIMULINK A. Fornasari, P. Malcovati, F. Maloberti: "Improved Model of Sima-Delta Modulator Non-Idealities SIMULINK"; Proc. of the IEEE International Symposium on Circuits and Systems, ISCAS 005, Kobe, 3-6 May,

More information

CHAPTER 3 DESIGN OF PIPELINED ADC USING SCS-CDS AND OP-AMP SHARING TECHNIQUE

CHAPTER 3 DESIGN OF PIPELINED ADC USING SCS-CDS AND OP-AMP SHARING TECHNIQUE CHAPTER 3 DESIGN OF PIPELINED ADC USING SCS-CDS AND OP-AMP SHARING TECHNIQUE 3.1 INTRODUCTION An ADC is a device which converts a continuous quantity into discrete digital signal. Among its types, pipelined

More information

Analog CMOS Interface Circuits for UMSI Chip of Environmental Monitoring Microsystem

Analog CMOS Interface Circuits for UMSI Chip of Environmental Monitoring Microsystem Analog CMOS Interface Circuits for UMSI Chip of Environmental Monitoring Microsystem A report Submitted to Canopus Systems Inc. Zuhail Sainudeen and Navid Yazdi Arizona State University July 2001 1. Overview

More information

Materials in this course have been contributed by Fernando Medeiro, José M. de la Rosa, Rocío del Río, Belén Pérez-Verdú and

Materials in this course have been contributed by Fernando Medeiro, José M. de la Rosa, Rocío del Río, Belén Pérez-Verdú and CMOS Sigma-Delta Converters From Basics to State-of-the-Art Circuits and Errors Angel Rodríguez-Vázquez angel@imse.cnm.es Barcelona, 29-30 / Septiembre / 2010 Materials in this course have been contributed

More information

Operational Amplifiers

Operational Amplifiers Monolithic Amplifier Circuits: Operational Amplifiers Chapter 1 Jón Tómas Guðmundsson tumi@hi.is 1. Week Fall 2010 1 Introduction Operational amplifiers (op amps) are an integral part of many analog and

More information

IJSRD - International Journal for Scientific Research & Development Vol. 4, Issue 02, 2016 ISSN (online):

IJSRD - International Journal for Scientific Research & Development Vol. 4, Issue 02, 2016 ISSN (online): IJSRD - International Journal for Scientific Research & Development Vol. 4, Issue 02, 2016 ISSN (online): 2321-0613 Design & Analysis of CMOS Telescopic Operational Transconductance Amplifier (OTA) with

More information

CHAPTER 4 ULTRA WIDE BAND LOW NOISE AMPLIFIER DESIGN

CHAPTER 4 ULTRA WIDE BAND LOW NOISE AMPLIFIER DESIGN 93 CHAPTER 4 ULTRA WIDE BAND LOW NOISE AMPLIFIER DESIGN 4.1 INTRODUCTION Ultra Wide Band (UWB) system is capable of transmitting data over a wide spectrum of frequency bands with low power and high data

More information