A Low Area, Switched-Resistor Loop Filter Technique for Fractional-N Synthesizers Applied to a MEMS-based Programmable Oscillator

Transcription

1 A Low Area, Switched-Resistor Loop Filter Technique for Fractional-N Synthesizers Applied to a MEMS-based Programmable Oscillator ISSCC 00, Session 3. M.H. Perrott, S. Pamarti, E. Hoffman, F.S. Lee, S. Mukherjee, C. Lee, V. Tsinker 3, S. Perumal 4, B. Soto 5, N. Arumugam, B.W. Garlepp SiTime Corporation, Sunnyvale, CA, USA UCLA, Los Angeles, CA, USA Global Foundries, Sunnyvale, CA, USA 3 Invensense, Sunnyvale, CA, USA 4 Consultant 5 SLAC National Accelerator Laboratory, Palo Alto, CA USA

2 Why Switch to MEMS-based Programmable Oscillators? uartz Oscillators MEMS-based Oscillator source: A part for each frequency and non-plastic packaging - Non-typical frequencies require long lead times Same part for all frequencies and plastic packaging - Pick any frequency you want without extra lead time We can achieve high volumes at low cost using IC fabrication

3 Architecture of MEMS-Based Programmable Oscillator 5 MHz MHz to 5 MHz Oscillator Sustaining Circuit and Charge Pump Fractional-N Synthesizer Programmable Frequency Divider Continuously Programmable MEMS Resonator Digital Frequency Setting MEMS device provides high resonance at 5 MHz - CMOS circuits provide DC bias and sustaining amplifier Fractional-N synthesizer multiplies 5 MHz MEMS reference to a programmable range of 750 to 900 MHz Programmable frequency divider enables to 5 MHz output 3

4 Compensation of Temperature Variation Freq Error (ppm) Freq Error (ppm) Temp 5 MHz MHz Temp Oscillator Sustaining Circuit and Charge Pump MEMS Resonator Fractional-N Synthesizer Programmable Frequency Divider Freq Compensation (ppm) Temp Continuously Programmable to 5 MHz Temperature Sensor Digital Logic Digital Frequency Setting High resolution control of fractional-n synthesizer allows simple method of compensating for MEMS frequency variation with temperature - Simply add temperature sensor and digital compensation logic 4

5 The Focus of This Talk Freq Error (ppm) Freq Error (ppm) Temp 5 MHz MHz Temp Oscillator Sustaining Circuit and Charge Pump MEMS Resonator Fractional-N Synthesizer Programmable Frequency Divider Freq Compensation (ppm) Temp Continuously Programmable to 5 MHz Temperature Sensor Digital Logic Digital Frequency Setting How do we achieve a fractional-n synthesizer with low area, low power, and low design complexity? 5

6 Analog Versus Digital Fractional-N Synthesizer? ref(t) div(t) reset D D Reg up(t) down(t) v tune (t) R C C Analog PLL + Low power - Large loop filter (Dominated by C ) Divider Digital PLL + Smaller loop filter - Difficult in 0.8 CMOS (Higher power) ref(t) div(t) Time-to-Digital Converter Digital Loop Filter Divider DCO out(t) Analog PLL wins in 0.8u CMOS for low power Can we achieve a low area (and low power) analog PLL with reduced design effort? 6

7 The Issue of Area: What Causes a Large Loop Filter? ref(t) div(t) reset D D Reg up(t) down(t) I noise v tune (t) R C C Output Phase Noise Charge Pump Noise VCO Noise f Divider Loop filter noise (primarily from charge pump) often dominates PLL phase noise at low offset frequencies We will show that - The common approach of reducing loop filter noise leads to increased loop filter area (i.e., C for charge pump PLL) - We can instead increase PD gain to lower the impact of loop filter noise Loop filter area can be smaller 7

8 First Step: Model PLL with Charge Pump Noise ref(t) div(t) reset D D Reg up(t) down(t) Divider I noise v tune (t) R C C Output Phase Noise Charge Pump Noise VCO Noise f ref (t) div (t) error (t) PFD PD Gain Charge Pump I pump I noise Divider N nom RC Network Z(s) C VCO Kv s out (t) 8

9 Increasing I pump Reduces Input-Referred Loop Filter Noise ref (t) LF noise I pump div (t) PD Gain LF noise Divider N nom I noise PFD Loop Filter VCO I pump C I pump Z(s) I pump Kv s out (t) Output Phase Noise Loop Filter Noise VCO Noise f ref (t) div (t) error (t) PFD PD Gain Charge Pump I pump I noise Divider N nom RC Network Z(s) C VCO Kv s out (t) Area gets larger since C is typically increased as well to maintain desired open loop gain 9

10 Increasing PD Gain Reduces Impact of Loop Filter Noise ref (t) div (t) PFD PD Gain LF noise Divider Loop Filter I pump C I pump Z(s) PD Gain VCO Kv s out (t) Output Phase Noise Loop Filter Noise VCO Noise f N nom PD Gain I pump PD Gain Impact of Loop Filter Noise on Output Keep Open Loop Gain Constant LF noise N nom PD Gain Loop filter area does not need to become larger But how do we increase the PD gain? PD Gain 0

11 PD Gain of Classical Tristate PFD Div(t) reset D D Reg I pump I pump RC Network Phase Detector Characteristic avg{-} Div(t) PD Gain = - - error Compute gain by averaging Up/Down pulses vs. phase error - Note that tristate PFD has a phase error range of Ref periods

12 Proposed Method of Increasing Phase Detector Gain avg{ - } PD Gain = 8 - /8 /8 - error Div(t) PD Gain = avg{ - } Reduce phase detection range to /4 of the Ref period - Achieves 8X increase in phase detector gain How do we capitalize on this reduced range in the filter? - - error

13 Simple RC Network Can Be Utilized avg{v c (t)} PD Gain = 8 - /8 /8 - error See also: Hedayati, Bakkaloglu RFIC 009 Div(t) High Gain PD Achieves full voltage range at V c as phase error is swept across the reduced phase detector range Note: instead of being influenced by charge pump gain after the PD, we are influenced by (regulated) supply voltage - R C V c (t) 3

14 Implementation of High Gain Phase Detector Delay Buffer For Non-Overlapping Up/Down Pulses D D D D D T ref Phase Detector Characteristic avg{ - } error T div Use 4X higher divider frequency - Simple digital implementation PD Gain = - T div T ref T ref T div = 8 4

15 Multi-Phase Pulse Generation (We ll Use it Later ) Mid(t) D D D D D Short Pulse Generator Last(t) T ref Phase Detector Characteristic avg{ - } error Mid(t) Last(t) T div PD Gain = - T div T ref T ref 8 = T div 5

16 Overall Loop Filter Consider Using Charge Pump High Gain PD See also: Craninckx, JSSC, Dec 998 V dd Gnd I pump I pump R C V tune (t) (Low K v ) V tune (t) (High K v ) C ref (t) div (t) PD Gain 8 PD Gain Supply Gain V dd Charge Pump I pump H(w) RC Network +sr _eff C Integration Cap sc We can use the high gain PD in a dual-path loop filter topology - But we want a simple design! w z w Can we remove the charge pump to reduce the analog design effort? 6

17 Passive RC Network Offers a Simpler Implementation High Gain Phase Detector Regulated V dd R V c (t) R R 3 C C C f C 3 V tune (t) Gnd DC Gain = H(w) C f Capacitive feedforward path provides stabilizing zero Design effort is simply choosing switch sizes and RC values w z C f +C 3 w 7

18 The Issue of Reference Spurs High Gain Phase Detector Regulated V dd R V c (t) R R 3 C C C f C 3 V tune (t) Gnd V c (t) V tune (t) Ripple from Up/Down pulses passes through to VCO tuning input Is there an easy way to reduce reference spurs? 8

19 Leverage Multi-Phase Pulsing Mid(t) Last(t) High Gain Phase Detector Regulated V dd R 3 / R 3 / R V c (t) R / R / C f C C C 3 V tune (t) Gnd V c (t) Ripple from Up/Down pulses blocked before reaching VCO - Reference spurs reduced! - Similar to sample-and-hold technique (such as Zhang et. al., JSSC, 003) Mid(t) Last(t) V tune (t) There is a nice side benefit to pulsing resistors 9

20 Pulsing Resistor Multiplies Resistance! T on T period Pulse_On(t) T period R _eff = R R/ R/ T on Resistor only passes current when pulsed on - Average current through resistance is reduced according to ratio of On time, T on, versus pulsing Period, T period - Effective resistance is actual resistance multiplied by ratio T period /T on Resistor multiplication allows a large RC time constant to be implemented with smaller area 0

21 Parasitic Capacitance Reduces Effective Resistance T on T period Pulse_On(t) < T period R _eff R R/4 R/4 R/4 R/4 T on C p C p C p C p C p C p Parasitic capacitance stores charge during the pulse On time - Leads to non-zero current through resistor during pulse Off time - Effective resistance reduced Spice simulation and measured results reveal that >0X resistor multiplication can easily be achieved

22 Switched Resistor Achieves PLL Zero with Low Area Regulated V dd Gnd R V c (t) Mid(t) R / R / R 3 / R 3 / C f C C C f For robust stability, PLL zero should be set well below PLL bandwidth of 30 khz - Assume desired w z = 4 khz - Set C f =.5pF (for low area) - Required R 3_eff = 6 MegaOhms Large area Last(t) H(w) C 3 V tune (t) w z = R 3_eff C f w z T period T on C f C f +C 3 w Proper choice of T on and T period allows R 3_eff = 6 MegaOhms to be achieved with R 3 = 500 kohms!

23 The Issue of Initial Frequency Acquisition Regulated V dd R 3_eff = 6MegaOhms R V c (t) Gnd R / R / V tune (t) C f C C C f C 3 = 35pF During initial frequency acquisition, V tune (t) must be charged to proper bias point - This takes too long with R 3_eff = 6 MegaOhms How do we quickly charge capacitor C 3 during initial frequency acquisition? 3

24 Utilize Switched Capacitor Charging Technique Gnd Regulated V dd R 3 / R 3 / R V c (t) R / R / C f C C C f Counter Count > 4 Charge Low Count < 4 Charge High Connect V tune (t) C 3 C c V dd Gnd Count T div_4x T ref Charge Low(t) Charge High(t) Connect(t) Charge C 3 high or low only when frequency error is detected - No steady-state noise penalty, minimal power consumption 4

25 CppSim Behavioral Simulation of Frequency Locking 0.5 vtune 0 charge_high 0 charge_low Time (microseconds) Switched capacitor technique allows relatively fast frequency locking 5

26 CMOS and MEMS Die Photos Show Low Area of PLL Active area: - VCO & buffer & bias: 0.5mm - PLL (PFD, Loop Filter, divider): 0.09 mm - Output divider: 0.0 mm External supply -.8/3.3V Current (0 MHz output, no load) - ALL: 3./3.7mA - VCO:.3mA - PLL & Output Divider: 0.7mA 6

27 Measured Phase Noise (00 MHz output) Ref. Spur: -65 dbc -90 dbc/hz -40 dbc/hz Integrated Phase Noise: 7 ps (rms) from khz to 40 MHz 00 Hz 30 khz 40 MHz Suitable for most serial applications, embedded systems and FPGAs, audio, USB. and.0, cameras, TVs, etc. 7

28 Frequency Variation After Single-Temperature Calibration Frequency Variation (PPM) Parts Temperature (degc) < 30 ppm across industrial temperature range with single-temperature calibration 8

29 Conclusion A MEMS-based programmable oscillator provides an efficient solution for industrial clocking needs - Programmability of frequency value simplifies supply chain and inventory management - Leveraging of semiconductor processing, rather than custom tools for quartz, allows low cost and low lead times Proposed fractional-n synthesizer allows low area, low power, and reduced analog design effort - High gain phase detector lowers impact of loop filter noise - Switched resistor technique eliminates the charge pump and reduces area through resistor multiplication - Switched capacitor frequency detection enables reasonable frequency acquisition time with no noise penalty Frequency references have entered the realm of integrated circuit design and manufacturing 9

30 Supplemental Slides 30

31 Noise Analysis (Ignore Parasitic Capacitance of Resistors) Φ div (t) PD Gain Supply Gain Φ ref (t) 8 V dd R _eff R _eff π 4kTR _eff 4kTR _eff 4kTR 3_eff Voltage Signal R 3_eff V tune C C C f C 3 Assumption: switched resistor time constants are much longer than on time of switches - Single-sided voltage noise contributed by each resistor is simply modeled as 4kTR eff (same as for a resistor of the equivalent value) Note: if switched resistor time constants are shorter than on time of switches - Resistors contribute kt/c noise instead of 4kTR eff - We would not want to operate switched resistor filter in this domain since time constants would not be boosted 3

32 Issue: Nonlinearity in Switched Resistor Loop Filter Phase Detector & Pulse Gen Up Down V dd R R / V c C Gnd Up Down T on T hold T period Nonlinearity is caused by - Exponential response of RC filter to pulse width modulation - Variation of T hold due to Sigma-Delta dithering of divide value Note: to avoid additional V c V c [k-] V c [k] V c [k+] nonlinearity, design divide value control logic to keep T on a constant value 3

33 Nonlinearity Due to Pulse Width Modulation Up Phase Detector & Pulse Gen Up V dd Down Gnd R R / V c C Pulse width modulation nonlinearity is reduced as ratio ΔT/(R C ) is reduced - If ΔT/(R C ) is small: Down V c V c [k-] T hold T on T on /+ΔT T on /-ΔT V c [k] Keep T on constant to avoid increased nonlinearity! 33

34 Nonlinearity Due to Hold Time Variation Phase Detector & Pulse Gen Up Down V dd R R / V c C Up Down V c V c [k-] Gnd T hold T on Hold time nonlinearity is reduced as changes in T hold (due to divide value dithering) are reduced - Reduce order of MASH Σ Δ Benefits are offset by reduced noise shaping of V c [k] lower order Sigma-Delta - Reduce step size of MASH Σ Δ Achieved with higher VCO frequency 34

35 Nonlinearity Is Not An Issue For This Design Folded Sigma-Delta uant Noise Other PLL Noise Sources Phase noise referred to VCO carrier frequency Folded quantization noise due to nonlinearity is reasonably below other noise sources for this design - However, could be an issue for a wide bandwidth PLL design Use (CppSim) behavioral simulation to evaluate this issue 35

36 What If We Use A Pure Charge Pump Loop Filter? I pump Div(t) High Gain PD I pump RC Network Phase Detector Characteristic avg{-} - PD Gain = - PD Gain increased by compared to tristate PFD - Reduced phase error range and max/min current occurs High linearity despite charge pump current mismatch - Similar to XOR PD, but noise is reduced error 36