Pulse-Based Ultra-Wideband Transmitters for Digital Communication

Transcription

1 Pulse-Based Ultra-Wideband Transmitters for Digital Communication Ph.D. Thesis Defense David Wentzloff Thesis Committee: Prof. Anantha Chandrakasan (Advisor) Prof. Joel Dawson Prof. Charles Sodini

2 Ultra-Wideband (UWB) Signaling Narrowband Signal Spectrum Impulse-UWB Signal Frequency FCC defines UWB as bandwidth >500MHz UWB signals are narrow in time Energy spread over wide bandwidth

3 UWB Regulations PSD [dbm/mhz] Frequency [GHz] GPS PCS GHz band Wireless Communication Mask Indoor for noise from digital electronics Handheld FCC issues notice of inquiry in 1998 First report and order in 2002 opening GHz band for wireless communication

4 Advantages and Challenges High data rate Precise locationing Low interference and probability of interception 1Gb/s 100Mb/s 10Mb/s 1Mb/s 100kb/s RFID, Locationing WPAN, Multimedia 1m 10m 100m Interference Multipath Wide bandwidth circuits PSD WiMAX a UWB Mask Frequency [GHz]

5 Outline High data rate transmitter Gaussian pulse shaping Variable low data rate transmitter All-digital architecture Conclusions and future directions

6 High Data Rate System 100Mb/s at 10m in dense multipath Minimize acquisition time, energy/bit Sub-banded frequency plan Application HD Video Dolby 5.1 PC Monitor MPEG2 Data Rate 19.2Mb/s 13.8Mb/s Mb/s Mb/s PSD [dbm/mhz] Channel Frequency Plan Frequency [GHz]

7 Transceiver Architecture Digital back-end [R. Blazquez, V. Sze] SiGe RF front-end [F. Lee, D. Wentzloff] Baseband Processing Pulse Shaping ADC ADC I/Q PA LNA UWB Antenna [J. Powell] 5-bit, 500MS/s dual ADC [B. Ginsburg]

8 Gaussian Pulse Generator Generate Gaussian pulse shape Tunable from GHz (14 channels) Matched BPSK pulses TX Architecture gain b 0 input V c b 1 input PA RF OUT A LO Integrated on chip

9 V in /2V th Tanh Approximation Exploit exponential BJT Apply empirically optimized triangle signal Output current approximates Gaussian pulse Differential Input Signal V off PW time [ns] A I c2 /I B v in Core Circuit i c1 Q 1 Q 2 Single-Ended Output Current I B i c time [ns]

10 Optimization Results V 2 V in th PW A t Normalized MSE V off V off PW 10 Minimum MSE is broad Constant-MSE Contours Optimum for σ= A

11 Optimized Pulse Normalized amplitude [V] Tanh Gauss Normalized time Normalized amplitude [db] Tanh -50 Gauss Normalized frequency 1.7% maximum in-band error between Tanh and Gaussian pulse

12 Pulse-Shaping Mixers V bias Replicated Pulse-Shaping Circuit V in0 V out +I LO V in1 V bias -I LO BPSK from opposite LO phases to each side V cm Data = 0 Data = 1 BPSK by pulsing one of two mixers Expandable to QPSK V in0 V in1 RF out

13 RF Amplifier 2 nd order high-pass filter Gain control I PA L 1 L 2 L choke From Mixer C 1 Q 1 V bias Q 2 /N NR B R B Q 2 To Antenna M 1 Class A amplifier directly drives UWB antenna

14 Measured Spectrum Channel 1 Channel 14 FCC Mask

15 BPSK Matching RF output power [dbm] Positive pulse Negative pulse Ideal Tanh Differential input voltage [V] Ideal Tanh Pulse Finite LO feedthrough Measured matching using on-chip VCO Comparison to ideal Tanh response

16 Measured Pulse 292mV 4GHz LO 50mV/div 1ns/div

17 Performance Summary 1.0mSmoot Process Modulation Pulse shape Pulse width Supply voltage Total power 0.18µm SiGe BiCMOS BPSK Gaussian ns 1.8V 31.3mW VCO PA Mixers Filter 0.8mSmoot [VCO by B. Ginsburg] Pulse-shaping and up-conversion in one circuit BPSK inversion in RF for improved matching

18 High-Rate System Summary Custom chipset and antenna solution Pulse-based, 14 channel, CDMA architecture Total power at 100Mb/s Receive mode: 227mW Transmit mode: 51mW TX (31.3mW) Digital back-end (137mW) ADC (16mW) RX (53.7mW) LO (20mW) 2.6nJ/bit

19 Outline High data rate transmitter Gaussian pulse shaping Variable low data rate transmitter All-digital architecture Conclusions and future directions

20 Motivation Low data rate, energy-constrained apps. Energy/bit [J] 1μ 0.1μ 10n 1n 0.1n 1k [ISSCC] 10k 0.1M 1M 10M 0.1G 1G Data rate [b/s] Trend: Data rate Energy/bit Impulse-UWB signaling inherently duty-cycled TX and RX on only when a pulse is present Fast (2ns) turn-on time

21 System Specifications PPM signaling with non-coherent receiver Variable frame time Data encoded in pulse position ns Three channel frequency plan PSD WiMAX Ch 1 3.1GHz FCC Mask Ch 2 Ch a 5.8GHz Center frequency: 6000ppm Relaxed RF tolerance All-Digital Transmitter

22 Energy-Detection Receiver RF front-end performs channel-selection Energy detection by square-and-integrate PPM 1 T 1 T 2 A 1-6 T 2 C 2 RF in LNA C 1 A Bits out T 1 60ns T 1 T 2 V 1 V 2 1 [F. Lee, ISSCC2007] No RF oscillator required

23 Pulse Generation Principle Use a tapped variable delay line and edge combiner to synthesize a pulse Positive Edge Combiner Equivalent to Single modulated pulse Center frequency depends on delay Width depends on number of edges combined Pulse LO Frequency selectivity without LO

24 Transmitter Block Diagram 32 stages, digital delay PRF PRBS Mask edges to combiner Edge Selection 30-Edge Combiner Feedback stage disabled when pulsing All full-swing static CMOS circuits

25 Digital Delay Stage in[n] 25f 50f Full-swing signals in[n+1] in[n] 25f 50f in[n+1] 6-bit current starving Overall ±30% variation in delay 2-bit cap bank 8-bit delay control PRBS R1[n] R2[n] Only selected edges are combined

26 Delay Line Calibration Configure delay line as a ring oscillator 8-bit control f RING = f RF / 32 Measure frequency by counting ring cycles C 1 C 0 I 5 I 4 I 3 I 2 I 1 I 0 Last I-starve bit? Begin Yes Choose cap bank No Choose next I-starve bit 4 banks 6 bits Measure frequency No Frequency in range? Yes Done

27 Delay Range and Accuracy 6 Simulated RF Output Frequency [GHz] FF TT SS Digital Code

28 Delay Range and Accuracy Frequency [GHz] Measured RF Output Measured RF and cal. output Digital Code MHz Calibration Accuracy Digital Code Ring output is an accurate measure of pulse center frequency

29 30-Edge Combiner Interleaved 15-edge combiners 15-Edge Combiner 1 15-Edge Combiner 2 XOR combiner outputs To pad driver x15 Masked edges Edge to pulse [Kim, JSSC 02] M2 A B M1 Q M4 M3 _ Q Q _ Q Edge[1] Edge[2] A B

30 RF Pad Driver From edge combiner Standby Weak pull-up Linear-in-dB scaling Standby Off-chip S11 27% efficiency Stacked NMOS to reduce leakage g[1] g[2] S11 [db] g[7] S11 in Idle State Frequency [GHz]

31 Spectrum Scrambling PSD [dbm/mhz] Normalized Frequency Conventional PPM+BPSK Data n pulse Data n+1 pulse Randomly modulated PPM signals have spectral lines PPM+BPSK scrambling eliminates tones Inverted pulse

32 Spectrum Scrambling PSD [dbm/mhz] Normalized Frequency Proposed PPM+DB-BPSK Data n pulse Data n+1 pulse Randomly modulated PPM signals have spectral lines PPM+Delay-Based BPSK scrambling eliminates tones in the main lobe 0.5T RF Delay DB-BPSK: Minimal Overhead

33 DB-BPSK Implementation Per-stage delay is ½ RF period PRBS bit selects register R1 R2 Mask values offset by 1 bit DB-BPSK Pulses 2.5ns 650mV PSD [dbm/mhz] PPM + DB-BPSK Spectrum PPM FCC Mask PPM + DB-BPSK Frequency [GHz]

34 DB-BPSK Modulation BER Coherent Receiver Simulations DB-BPSK BPSK E b /N 0 DB-BPSK can replace BPSK in a coherent receiver with 0.2dB loss

35 Measured Spectrum Channel Spectrum -40 CH2 Gain Settings PSD [dbm/mhz] PSD [dbm/mhz] Frequency [GHz] Frequency [GHz]

36 Transmitter Summary Technology Active Area Modulation Scrambling Supply Leakage Power Active E/pulse PRF Range Total E/bit 90nm CMOS 0.11x0.22mSmoot 2 PPM DB-BPSK 1V 96μW 37pJ/pulse 10kHz to 16.7MHz 9.6nJ/bit to 43pJ/bit 0.5mSmoot 0.5mSmoot Energy consumed in sub-v t leakage and CV 2 Digital architecture practical for non-coherent RX

37 Low-Rate System Demo Commercial UWB antenna Transmitter FPGA to implement calibration, USB interface Receiver Powered from USB bus Demonstrated wireless link at 16.7Mb/s, 1kb packets Acquisition and timing implemented on FPGA

38 Outline High data rate transmitter Gaussian pulse shaping Variable low data rate transmitter All-digital architecture Conclusions and future directions

39 Summary of Contributions Gaussian pulse approximation Spectrally efficient for dense networks All-digital pulse generation Relax spectral efficiency requirement Digitally programmable pulse spectrum Ultra-low power Proposed DB-BPSK modulation Suitable for scrambling PPM, BPSK replacement

40 Conclusions Exploit available bandwidth to reduce power in electronics UWB systems are receiver power dominated Energy/bit compares favorably to other work Dominated by leakage currents at low data rates Energy/bit [pj] UWB Transmitters Leakage Tanh All-Digital 10 10k 1M 100M 10G Data rate [b/s]

41 Future Directions UWB suitable for high and low data rates Narrowband relies on fine-tuning UWB signaling enables relaxed frequency tolerance CMOS integration Highly digital radios Use standard digital design flow Benefit from process scaling Ultra-low power and area Synthesizable transmitter for UWB

42 Acknowledgements Anantha Chandrakasan Joel Dawson and Charlie Sodini Margaret Flaherty and family MARCO/DARPA Focus Center for Circuits and Systems Solutions (C2S2), National Science Foundation (NSF), HP/MIT Alliance STMicroelectronics for chip fabrication Thank YOU for your attention