A Single-Chip 2.4-GHz Direct-Conversion CMOS Receiver for Wireless Local Loop using Multiphase Reduced Frequency Conversion Technique

Transcription

1 800 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 5, MAY 2001 A Single-Chip 2.4-GHz Direct-Conversion CMOS Receiver for Wireless Local Loop using Multiphase Reduced Frequency Conversion Technique Kyeongho Lee, Joonbae Park, Jeong-Woo Lee, Seung-Wook Lee, Hyung Ki Huh, Deog-Kyoon Jeong, Member, IEEE, and Wonchan Kim Abstract A single-chip direct-conversion CMOS receiver for 2.4-GHz wide-band code-division multiple-access wireless local loop (WLL) is described. The chip includes a low noise amplifier, a 12-phase downconverter, a variable gain amplifier, a channel selection filter, a programmable phase-locked loop for seven channel frequencies, and a 4-bit flash analog-to-digital converter. The proposed multiphase reduced frequency conversion scheme combined with a multiphase sampling fractionalprescaler, a cascaded dc-offset canceler and distributed automatic gain control loops offers solutions to problems of a direct-conversion receiver. Experimental results show 115-dBm sensitivity, 4.4-dB noise figure, and 95-dB dynamic range, which sufficiently meet commercial WLL specification. Index Terms wireless local loop, direct conversion, phase-locked loop, mixer, fractional- frequency synthesizer, filter. I. INTRODUCTION VARIOUS RF communication systems have been developed for a wide range of applications. To reduce the cost and size of RF communication systems, single-chip CMOS integration of RF building blocks has been continuously attempted with some successful results [1], [2]. The superheterodyne RF architecture has been one of the candidates of CMOS RF integration because it can provide sufficiently low noise figure for various applications. However, the superheterodyne architecture has critical drawbacks that prevent RF functions from being integrated in a single chip. It requires an image rejection filter, an IF filter, and at least two phase-locked loops (PLLs), which cannot be easily integrated into a single chip. Another candidate is a direct-conversion architecture [1], [2]. Its simple architecture has a major advantage in CMOS RF integration. It does not require surface acoustic wave (SAW) filters and only one PLL is required. However, there are several challenges to overcome its fundamental drawbacks. First, the local oscillator (LO) frequency, being equal to carrier frequency, can generate a LO leakage, which results in a large dc-offset and signal saturation. Second, integrated CMOS voltage-controlled oscillators (VCOs) should support such high frequencies as 1.9 GHz for PCS applications and 2.4 GHz for IMT2000, HomeRF, and wireless local loop Manuscript received June 20, 2000; revised October 15, K. Lee, J. Park, and J.-W. Lee are with Global Communication Technology, Santa Clara, CA USA. S.-W. Lee, H.-K. Huh, D.-K. Jeong, and W. Kim are with the School of Electrical Engineering, Seoul National University, Seoul , Korea. Publisher Item Identifier S (01)03030-X. (WLL) applications with a sufficiently low phase noise. There has been no adequate circuit for the CMOS VCO to satisfy such requirements except the VCOs with integrated inductors. Third, the adjacent channel blocker cannot be filtered out until the final baseband filter stage, which prevents the received in-band signal from having enough amplification to achieve a low noise figure comparable to the superheterodyne architecture. This work provides robust solutions to fundamental problems of the direct-conversion receiver. The proposed multiphase downconversion scheme can reduce the LO leakage and dc-offset problem. The proposed CMOS ring-oscillator VCO and multiphase sampling fractional- prescaler allows low enough phase noise without on-chip spiral inductors. Also, the proposed baseband architecture composed of a cascaded automatic gain control (AGC) loop and cascaded dc-offset canceling loops provide a noise figure low enough for wide-band CDMA application without the dc-offset problem. A full CMOS implementation without any on-chip spiral inductors has been fabricated and its experimental results show its adequacy of production-worthy integrated CMOS RF systems. II. SYSTEM ARCHITECTURE Fig. 1 shows the proposed receiver architecture. The proposed architecture is composed of a full-cmos low noise amplifier (LNA), a 12-phase downconverter, a PLL generating 12-phase 800-MHz LO signals (LO [0 to 11]), a variable gain amplifier with the first AGC loop, gain-merged four third-order elliptic filter with the second AGC loop, a tuning circuit with polyphase filter configuration, and 4-bit flash analog-to-digital converters (ADCs). The PLL is composed of a 12-phase VCO with multiple feedback loops and a multiphase sampling fractional- prescaler. The VCO cell is designed for short rise/fall times and large swing to obtain the phase noise low enough for a wide-band 2.4-GHz code-division multiple-access (CDMA) application. The proposed multiphase sampling fractional- prescaler performs a conventional fractional- functionality but avoids a fractional spur inside the channel bandwidth. As a result, the proposed PLL can have a bandwidth large enough to get a low phase noise for wide-band 2.4-GHz CDMA without the fractional spur problem. The PLL generates 12-phase LO signals (LO [0 to 11]) for seven different channel frequencies. The 12-phase downconverter is composed of two 6-phase single-balanced mixers, one for I-channel, the other for Q-channel. The proposed 6-phase mixer /01$ IEEE

2 LEE et al.: DIRECT-CONVERSION CMOS RECEIVER FOR WIRELESS LOCAL LOOP 801 Fig. 1. Integrated receiver architecture. receives 800-MHz 6-phase LO signals (LO [0,2,4,6,8,10] for I-channel, LO [1,3,5,7,9,11] for Q-channel) and offers the same functionality as a conventional single-balanced mixer receiving a single-phase 2.4-GHz LO signal. The proposed mixer structure allows the CMOS VCO to operate at one-third of carrier frequency. The low phase noise CMOS VCO operating near 1 GHz has been previously implemented with reasonable performance [3]. Furthermore, the dominant power of the LO leakage is no longer at 2.4 GHz because the VCO is operating at 800 MHz. As a result, the amount of dc-offset can be drastically reduced to a negligible level. The baseband structure is composed of seven-stage variable gain amplifiers with the first AGC loop and gain-merged four third-order elliptic filter with the second AGC loop. The first AGC loop enables the desired channel to get the maximum gain before the channel selection filter on the large adjacent channel condition. The second AGC loop compensates the gain loss of the desired channel caused by large adjacent channel blocker. The gain-merged channel selection filter simultaneously amplifies the desired channel and rejects the adjacent channel by 65.7 db. The proposed baseband structure exhibits an overall noise figure of 4.4 db, which is low enough for a 2.4-GHz wide-band CDMA application. The cascaded dc-offset canceling loop performs 140-dB dc-offset rejection at 30 khz, which is caused by the 2.4-GHz leakage and device mismatches [4]. It occupies a smaller chip area than the conventional single-loop structure under the same rejection ratiorequirement. A 4-bit flash ADC operates at a 32-MHz sampling frequency. III. MULTIPHASE REDUCED FREQUENCY CONVERSION TECHNIQUE The basic idea of the proposed multiphase reduced frequency conversion (MPRF) technique is that the effect of mixing with a single-phase high-frequency periodic signal can be obtained by multiplying by a set of multiphase reduced-frequency periodic signals. To be specific, assume that we use sine and cosine signals in RF systems. The sine and cosine signals with frequency are equivalent to -phase low-frequency sine and cosine signals whose frequencies are, as shown in the following equations. Fig. 2 shows the proposed MPRF downconversion architecture using the proposed multiphase mixers whose circuitry and operation will be described in the following section. Only one PLL with multiphase outputs is required while the PLL in the conventional direct-conversion architecture offers two outputs with quadrature relation. The PLL generates LO and -phase LO signals (total of phases) which are defined as (3) and (4). LO LO (1) (2) -phase where (3) where (4)

3 802 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 5, MAY 2001 Fig. 2. Multiphase reduced frequency conversion architecture. Fig. 3. Six-phase example of multiphase reduced frequency conversion architecture. The functionality of the I-channel multiphase mixer is to multiply the -phase sine signals ( uninverted, inverted) of frequency ( with the RF signal. The Q-channel multiphase mixer works in the same way except it uses the cosine signal. As a result, resultant functionality is equal to the conventional direct conversion using a single-phase signal with frequency. Fig. 3 shows the 6-phase example for MPRF conversion architecture using a 6-phase mixer. The PLL generates the 12-phase sine signals as follows. Phase - (5) Phase - The phase difference between two adjacent LO signals is. Phases {0, 2, 4, 6, 8, 10} are used as I-channel mixer inputs and multiplied together with the RF input. Phases {1, 3, 5, 7, 9, 11} are used as Q-channel mixer inputs. As a result, LO signals whose frequency is reduced to one-third of the conventional direct-conversion LO frequency are used. By reducing LO frequency in direct-conversion architecture, we can expect two distinct advantages. First, we can reduce the amount of dc-offset caused by LO leakage whose frequency is equal to

4 LEE et al.: DIRECT-CONVERSION CMOS RECEIVER FOR WIRELESS LOCAL LOOP 803 Fig. 4. LNA and 12-phase downconverter. the carrier, because the LO frequency is no longer equal to the carrier frequency. Second, reduced LO frequency enables easier implementation of the CMOS VCO with less phase noise. IV. CIRCUIT DESCRIPTION A. LNA and Downconverter Fig. 4 shows the detailed circuit diagram of a full CMOS LNA and 12-phase downconverter. The 900-MHz starved inverter-type LNA has been previously reported [7]. The proposed starved inverter-type LNA shows better linearity using a symmetric structure. The half- bias enables the symmetric operating points so that the pmos and nmos networks have the largest dynamic range, especially under a large input signal. The LNA gain and noise figure is simulated to be 15 and 1.7 db, respectively, at 2.4 GHz. The 12-phase downconverter is composed of two 6-phase single balanced mixers, as shown in Fig. 4. Six-phase LO signals (LO[0,2,4,6,8,10]) are used for I-channel downconversion and the remaining 6-phase LO signals (LO [1, 3, 5, 7, 9, 11]) are used for Q-channel. Each 6-phase mixer with 800-MHz 6-phase LO signals perform the same functionality as the conventional balanced mixer with a 2.4-GHz single-phase LO signal. The proposed mixer structure allows the use of a large amplitude LO signal with reduced rise/fall times and thus increases the mixer conversion gain and decreases the noise figure. Fig. 5 shows the detailed operation of the 6-phase single balanced mixer. As shown in Fig. 5, the VCO generates 6-phase LO signals (LO [0 to 5]). The proposed 6-phase single-balanced mixer receives 6-phase LO signals (LO [0 to 5]) and the RF signal. The timing diagram shows the mechanism to obtain the resultant effect equivalent to applying the single-phase LO signal whose frequency is by using the 6-phase LO signals whose frequency is. The 6-phase single balanced mixer is composed of six switches controlled by 6-phase LO signals. One of three switches on the left and right side is turned on alternately at every phase interval. As a result, virtual LO waveforms (LOT and LOT ) are obtained by multiphase operation, which have the frequency of and act as a virtual single-phase LO signal, even though it does not exist in reality. Thus, the proposed multiphase VCO mixer interconnect structure allows low-frequency multiphase LO signals to have the same functionality as a high-frequency single-phase LO signal, which reduce the amount of LO leakage and dc-offset problem. The combined gain of the LNA and the 12-phase downconverter is 25 db. The combined IIP3 is 6.3 dbm. B. Phase-Locked Loop Fig. 6 shows the circuit diagram of the PLL composed of a full CMOS, a multiphase sampling fractional- prescaler, and an on-chip loop filter. The CMOS VCO is implemented as a ring oscillator with multiple feedback loops [8], which can increase the VCO frequency and reduce the rise/fall time of the LO waveform. The proposed CMOS VCO has a symmetric structure to match the rise/fall time of LO waveforms, which can reduce the phase noise caused by rise/fall time mismatch [3]. The frequency of the VCO is controlled by adjusting the strength of the feedback network. As decreases, the voltage levels of FEED and FEED0 increase and the strength of the feedback increases. Thus, the sharp rise/fall time can be maintained even at low frequencies. An on-chip supply regulator, implemented with a conventional charge-pump circuit, is incorporated to enhance the power supply rejection ratio (PSRR) of the VCO. The proposed multiphase sampling fractional- prescaler is composed of a pulse-swallow divider, a 12-stage multiphase sampler, a 12-to-1 mux, and a modular counter. The pulse-swallow divider performs divide-by- operation. The output of the pulse-swallow divider is sampled by 12-phase 800-MHz

5 804 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 5, MAY 2001 Fig. 5. Operation of 6-phase single-balanced mixer. Fig. 6. PLL using multiphase sampling fractional-n prescaler and full CMOS VCO. LO clocks (LO [0 to 11]). The outputs of the 12-stage sampler (TCK [0 to 11]) have twelve different timings determined by 12-phase LO clocks. The modular counter periodically selects one of TCK [0 to 11] according to which ranges from 0 to 11. The resultant division ratio of the proposed prescaler is. As a result, the proposed prescaler, with a fractional-12 operation, increases the PLL bandwidth and reduces the phase noise without a fractional spur. By changing the,, and values, the PLL supports seven different channel frequencies ( MHz, ).

6 LEE et al.: DIRECT-CONVERSION CMOS RECEIVER FOR WIRELESS LOCAL LOOP 805 Fig. 7. Baseband signal flow. Fig. 8. Gain-merged g 0C third-order elliptic filter and tuning circuit with poly-phase filter configuration. C. Baseband Circuit Fig. 7 shows the baseband signal flow. When an adjacent channel power is smaller than or equal to the desired channel, the desired channel takes the required gain mainly from the first AGC loop. When the adjacent channel power is substantially larger than the desired channel, the first AGC loop amplifies the desired channel until the adjacent channel power reaches the linearity limit. The second AGC loop merged in a channel selection filter amplifies the desired channel to the desired level.regardless of gain distribution, the four third-order elliptic filters perform 65.7-dB adjacent channel rejection with a 4-MHz cutoff frequency. Fig. 8 shows the structure of the gain-merged third-order elliptic filter and the proposed

7 806 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 5, MAY 2001 Fig. 9. Detailed circuit diagram of the proposed tuning circuit. Fig. 10. Phase noise of VCO. Fig. 11. RMS phase jitter of VCO. RMS phase noise = :0059 radians, tuning circuit based on the polyphase filter configuration. Fig. 9 shows the detailed circuit diagram of the proposed tuning circuit. The tuning circuit receives a 4-MHz sine wave as a reference to set the filter cutoff frequency. It offers a simpler circuit configuration than a conventional tuning circuit with a voltage-controlled filter. Also, it can provide a more robust operation than a VCO-type tuning circuit that shows drawbacks such as difficulty of oscillation and too high Q-factor requirement. The equivalent circuit diagram of polyphase filter is shown in Fig. 9, where the values of the polyphase filter are controlled by.as increases, values increase, the amplitude of low pass filter (LPF) output increases, and that of high pass filter (HPF) output decreases. The rectifiers for the comparison detect the peak levels of LPF and HPF outputs. The converter receives the rectified outputs and generates the pumping current whose amount is proportional to the difference of amplitudes. As a result, the amplitudes of a high-pass and a low-pass filter outputs are equalized by the negative feedback loop, which results in the steady-state value as shown in the formula of Fig. 9. A 4-bit conventional flash ADC in differential architecture is implemented. The minimum of 4-bit resolution is required for a 2.4-GHz wide-band CDMA WLL using the 32-kb/s adaptive differential pulse code modulation (ADPCM) speech coding scheme. Peak signal-to-noise-plusdistortion ratio (SNDR) of the 4-bit flash ADC is 25.2 db. Measured integral nonlinearity (INL) and differential nonlinearity (DNL) are 0.39 and 0.34 LSB, respectively. It consumes 4.5 ma for the sampling rate of 32 MS/s. The dynamic range of overall baseband gain stage is 95 db. V. EXPERIMENTAL RESULTS The chip has been fabricated with a m 2-poly 3-metal CMOS process. The chip is connected to the system with a chip-on-board technique to reduce the parasitic inductance

8 LEE et al.: DIRECT-CONVERSION CMOS RECEIVER FOR WIRELESS LOCAL LOOP 807 (a) (b) Fig. 12. (a) Mixer output spectrum when 070-dBm 2402-MHz and 030-dBm 2406-MHz RF inputs are applied to LNA. (b) g 0C filter output spectrum under the same condition. Fig. 13. CDMA output spectrum measured on I/Q channel selection filter. Fig. 15. receiver. Calling test setup for 2.4-GHz wireless local loop using implemented Fig. 14. Chip microphotograph. and capacitance. The measured overall noise figure and receiver sensitivity is 4.4 db and 115 dbm, respectively, at the maximum 95-dB gain condition. The IIP3 of the overall system is 10.1 dbm. Fig. 10 shows the measured result of VCO phase noise. The phase noise of the closed-loop VCO operating at 800 MHz is 105 dbc/hz at 10-kHz offset when all blocks are operating for receiving a 2.4-GHz CDMA signal. Fig. 11 shows the measured RMS phase jitter of the VCO. The measured value is Fig. 12(a) shows the mixer output spectrum when a 70-dBm 2402-MHz input is applied to the LNA with a 30-dBm 2406-MHz adjacent channel blocker. Fig. 12(b) shows the filter output spectrum under the same condition, which shows that 70-dBm desired channel is amplified by 70-dB gain (25 db by the LNA and mixer plus 45 db by baseband) and 30-dBm adjacent channel is rejected by 65.7 db (40 db 25.7 db). The noise floor shown in Fig. 12(b) indirectly shows the characteristics of the four third-order elliptic filter. Fig. 13 shows the CDMA output spectrum of the I/Q channel selection filter. The output signals are attenuated by 225 db for the measurement purpose. The measured amplitude of the filter output is 0 dbm. The measured I/Q mismatch is smaller than 0.9 db. Fig. 14 shows the chip microphotograph. The total area is 3 mm 3.5 mm. Fig. 15 shows the calling test setup for 2.4-GHz WLL using the implemented receiver chip. The chip is fully functional

9 808 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 5, MAY 2001 TABLE I SUMMARY OF CHIP CHARACTERISTICS TABLE II DISTRIBUTION OF CURRENT CONSUMPTION in a system environment. Table I shows the summary of chip characteristics. Table II shows the distribution of current consumption. VI. CONCLUSION A multiphase reduced frequency conversion receiver architecture and a baseband architecture are presented to solve many of the problems of integrating a conventional direct-conversion receiver in a single chip. The dc-offset problem caused by LO leakage, which has been the most difficult one to solve, is overcome by using an LO frequency much smaller than the carrier frequency. Furthermore, the reduced LO frequency allows easier implementation of the CMOS VCO with less phase noise. The proposed PLL composed of a full CMOS VCO and multiphase sampling fractional- prescaler provides the equivalent functionality to the conventional fractional- prescaler with less fractional spur. As a result, the large bandwidth required for low phase noise for commercial WLL specification is safely obtained without the fractional spur problem. Measured results show that the phase noise of the proposed PLL is 105 dbc/hz at 10-kHz offset. The baseband architecture composed of cascaded AGC loops and gain-merged filters significantly enhances the noise-figure performance of the conventional baseband amplifier in a direct-conversion receiver. The single-chip 2.4-GHz direct-conversion receiver implemented in m CMOS technology meets the stringent requirement of the RF specification of the WLL and shows feasibility for low-cost commercial application. REFERENCES [1] A. Parssinen et al., A wide-band direct conversion receiver for WCDMA applications, in ISSCC Dig. Tech. Papers, Feb. 1999, pp [2] A. Rofougaran et al., A single-chip 900-MHz spread-spectrum wireless transceiver in 1-m CMOS Parts I and II, IEEE J. Solid-State Circuits, vol. 33, pp , Apr [3] A. Hajimiri et al., A general theory of phase noise in electrical oscillators, IEEE J. Solid-State Circuits, vol. 33, pp , Feb [4] J. Park et al., An automatic gain control loop apparatus, U.S. patent pending. [5] K. Lee et al., VCO-mixer structure, U.S. patent pending. [6] K. Lee et al., Single chip CMOS transmitter/receiver, U.S. patent pending. [7] A. N. Karanicolas, A 2.7-V 900-MHz CMOS LNA and mixer, IEEE J. Solid-State Circuits, vol. 31, pp , Dec [8] D.-Y. Jeong et al., CMOS current-controlled oscillators using multiple-feedback-loop ring architectures, in ISSCC Dig. Tech. Papers, Feb. 1997, pp Kyeongho Lee was born in Seoul, Korea, in He received the B.S., M.S., and Ph.D. degrees in electronics engineering from Seoul National University, Seoul, Korea, in 1993, 1995, and 2000, respectively. He was with Silicon Image, Inc., Sunnyvale, CA, as a Member of Technical Staff, where he worked on CMOS high-bandwidth low-emi transceivers. He is currently with Global Communication Technology, Inc., Santa Clara, CA, as a Chief Technical Officer. His research interests include various CMOS highspeed circuits for wired/wireless communication systems and integrated CMOS RF systems. Dr. Lee received the distinguished dissertation award from the School of Electrical Engineering, Seoul National University. Joonbae Park was born in Seoul, Korea, in He received the B.S. and M.S. degrees in electronics engineering from Seoul National University, Seoul, Korea, in 1993 and 1995, respectively, and the Ph.D. degree from the School of Electrical Engineering, Seoul National University. In 1998, he joined Global Communication Technology, Santa Clara, CA, as Director of Analog Division. He is involved with the development of CMOS RF chip sets for WLL, W-CDMA, and wireless LAN. His other research interests include data converters and high-speed communication interfaces. Dr. Park received the Best Paper Award of VLSI Design 99, Goa, India. Jeong-Woo Lee received the B.S. and M.S. degrees in electronics engineering and the Ph.D. degree in electrical engineering in 1994, 1996, and 2000, respectively, from Seoul National University, Seoul, Korea. He then joined Global Communication Technology, Santa Clara, CA. He is currently a Manager with the W-CDMA Team. His current research interests include CMOS transceiver circuitry for highly integrated radio applications. Seung-Wook Lee was born in Seoul, Korea, in He received the B.S. and M.S. degrees in electronics engineering from Seoul National University, Seoul, Korea, in 1995 and 1997, respectively. He is currently working toward the Ph.D. degree from the School of Electrical Engineering, Seoul National University. His research interests include CMOS RF circuit design and high-speed communication interface. Mr. Lee is the winner of the bronze prize of the IC design contest held by the Federation of Korean Industries in 1995.

10 LEE et al.: DIRECT-CONVERSION CMOS RECEIVER FOR WIRELESS LOCAL LOOP 809 Hyung Ki Huh was born in Seoul, Korea. He received the B.S. degree in electrical engineering from Seoul National University in 1998, where he is currently working toward the M.S. degree in electrical engineering. His research interests are in the area of RF circuits and systems with emphasis on frequency synthesizers and analog-to-digital converters. Deog-Kyoon Jeong (S 85 M 89) received the B.S. and M.S. degrees in electronics engineering from Seoul National University, Seoul, Korea, in 1981 and 1984, respectively, and the Ph.D. degree in electrical engineering and computer sciences from the University of California, Berkeley, in From 1989 to 1991, he was with Texas Instruments Inc., Dallas, TX, where he was a Member of Technical Staff and worked on the modeling and design of BiCMOS gates and the single-chip implementation of the SPARC architecture. He joined the faculty of the Department of Electronics Engineering and Inter-University Semiconductor Research Center, Seoul National University, as an Assistant Professor in He is currently an Associate Professor of the School of Electrical Engineering, Seoul National University. His main research interests include high-speed I/O circuits, VLSI systems design, microprocessor architectures, and memory systems. Wonchan Kim was born in Seoul, Korea, in He received the B.S. degree in electronics engineering from Seoul National University, Seoul, in He received the Dip.-Ing. and Dr.-Ing. degrees in electrical engineering from the Technische Hochschule Aachen, Aachen, Germany, in 1976 and 1981, respectively. In 1972, he was with Fairchild Semiconductor Korea as a Process Engineer. From 1976 to 1982, he was with the Institut für Theoretische Electrotecnik RWTH, Aachen. Since 1982, he has been with the School of Electrical Engineering, Seoul National University, where he is currently a Professor. His research interests include development of semiconductor devices and design of analog/digital circuits.