A PROCESS AND TEMPERATURE COMPENSATED RING OSCILLATOR

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1 A PROCESS AND TEMPERATURE COMPENSATED RING OSCILLATOR Yang-Shyung Shyu * and Jiin-Chuan Wu Dept. of Electronics Engineering, National Chiao-Tung University 1001 Ta-Hsueh Road, Hsin-Chu, 300, Taiwan * p @alab.ee.nctu.edu.tw Abstract An on-chip oscillator with small frequency variation in a digital 0.6μm CMOS technology is described. The oscillator utilizes a bias technique to compensate for the influences on the oscillation frequency caused by both temperature and process variations. No external components are needed in the oscillator. Simulation results show that the frequency of the proposed oscillator has a peak variation of ±6.8% for all process corners and a temperature range of 120 C. The oscillator is measured to operate at a center frequency of 680 KHz and have a peak variation of ±4.7% over 29 sample chips in two different lots and a temperature range of 35 C to 115 C. As a comparison, a conventional inverter chain oscillator is made on the same chip. The frequency variation of the conventional inverter chain is ±14.6%. I. INTRODUCTION Most digital circuits need a precise clock frequency to operate correctly. Some high-resolution systems need crystal oscillators to generate the precise clock frequency that is immune to supply voltage, temperature and process variations. However, it requires an external crystal and at least two extra package pins. In some applications, the circuits can function correctly with a less precise clock and an on-chip clock generator is preferred for the reduction of printed circuit boards area and external components. The common drawbacks of on-chip clock generators are that their output frequency varies significantly with temperature, supply voltage and process variations. A voltage regulator can be used to reduce the variations caused by supply voltage drifts. The effects of process and temperature variation, however, must be compensated using circuit design techniques

2 An on-chip clock generation can be made by using a voltage controlled oscillator with a specific control voltage. The most widely used delay elements are shown in Fig. 1, [1,2]. The delay of each delay element and the number of the stages of the ring determine the oscillation period. The drawback of such delay elements is that the charging and discharging current are affected by temperature and process variations and thus the clock period differs. Besides, the effective resistance of the MOS controlled by Vcontrol would make its immunity even worse if Vcontrol is not designed to compensate these variations. Another kind of oscillators is based on a multi-vibrator, [3]. This circuit structure alternatively charges two capacitors with an amount of current and discharges them with a larger current. Comparing the voltages of the two capacitors with the reference voltage, and with the aid of RS-latch, the cycle time of this oscillator can be decided by the amount of charging current, capacitors, and the reference voltage, regardless of the discharging current. Though it is reported that this oscillator can have a good temperature coefficient, the effects of the variations due to process have not been considered. Bipolar oscillators based on emitter-coupled multi-vibrators usually offer excellent temperature immunity [4]. However, its high power consumption and its process preclude bipolar oscillators from some applications in standard CMOS process and similarly, the effects due to process variations have not been mentioned. Fig. 1 Conventional delay element (a) current-starved inverter (b) voltage-control delay It can be seen from above discussion that the difficulty of generating precise on-chip clock pulses is how to improve its immunity to the operating temperature and its process variations simultaneously. For this reason, some bias techniques have been proposed to compensate for variations in either temperature or process, but none of them can reduce the sensitivities to both variations, simultaneously

3 This paper presents a design of the temperature and process compensated ring oscillators which can achieve good immunity to those variations. In section II, the operation principle and the bias technique are explained. Experimental results of this ring oscillator are shown in section III and section IV gives the conclusion. II. DESIGN CONCEPTS AND CIRCUIT TECHNIQUES In order to generate a precise frequency, this design is based on the voltage controlled ring oscillator described in [5-7] and uses a process and temperature compensation bias technique to improve the oscillator's immunity to environmental variations. The block diagram of this ring oscillator is shown in Fig. 2. The ring of this oscillator is composed of several stages of differential buffers. The number of stages and the delay of each buffer determine the oscillating period. The block Ctrl-Gen generates the control voltage Vctrl and the block Cs-Gen provides the bias voltage of the current source in differential buffers. Fig. 2 Block diagram of the ring oscillator - 3 -

4 Fig. 3 Differential buffer used in the oscillator The control voltage Vctrl controls the buffer delay and the operating frequency of the ring oscillator while Vcs gives the proper bias current. A. Differential Buffer The ring oscillator can be realized with either single ended or differential inverting buffers. Fig. 3 shows the schematic of the buffer used in this design. This differential buffer is based on an NMOS source-coupled pair with a symmetric load element and a simple NMOS current source. The symmetric load elements are composed of a diode-connected PMOS device in parallel with an equally sized PMOS device biased at a voltage of Vctrl. With a proper buffer bias current in the current source, the output swing varies with the control voltage Vctrl, rather than being fixed. Besides, the load element can then have a symmetric I-V characteristic. With the top supply voltage as its upper swing limit, the lower limit is symmetrically opposite at the bias level of the PMOS load. That is, if there is a proper bias current, Vctrl sets the lower limit of the swing while the top supply sets its upper limit. B. Generation of Vcs Fig. 4 gives the generation of the bias for current sources. This circuit adjusts the output current of the NMOS current source so that the voltage at the output of the replicated load element, Vload, is equal to the control voltage. When Vload is different from Vctrl, the difference is amplified by the differential stage, Vcs would change accordingly to make Vload equals to Vctrl. The entire circuit is actually a 2-stage differential operational amplifier connected in the unity-gain configuration. In other words, Cs-Gen limits the output range of differential buffers from Vctrl to the top supply voltage. In this case, the delay of the buffer is determined by the control voltage Vctrl and the symmetric load which is composed of PMOS only. As can be seen, the delay is insensitive to the characteristic of the NMOS

5 Fig. 4 Generation of bias for the current source Now, consider the effects of the operating temperature and process variations to the differential buffer. When temperature increases, the threshold voltage, Vthp, of the PMOS decreases but the hole mobility also decreases. The net result is that the effective resistance of PMOS increases and thus the oscillating frequency decreases. Similarly when the process deviates from typical to slow, the Vthp increases and both the effective resistance of PMOS and the oscillating frequency decreases. Since the oscillating frequency changes oppositely with Vctrl, in order to keep the oscillating frequency fixed, the control voltage Vctrl has to decrease when temperature increases or process is drifting toward the slower corner. C. Generation of Vctrl Fig. 5 gives the most commonly used bias circuits in the standard CMOS process. The bias voltage, Vbiasp, is generated from MOS only. If the threshold voltage of the PMOS is increased (decreased) due to process variations, the effective resistance of the load element in the differential buffer would increase (decrease) correspondingly and hence the buffer delay increases (decreases). Since the output voltage, Vbiasp, in Fig. 5(a) decreases when Vthp increases, Fig. 5(a) can be used to generate Vctrl to bias the load element in the differential buffer and it can compensate the effects due to process variations in the ring oscillator. On the other hand when the temperature increases (decreases), the Vthp of PMOS decreases (increases) but the effective resistance of the load element increases (decreases). As can be seen, both the gate voltage of PMOS load and its threshold voltage have the same trend to increase or decrease as temperature varies and this makes the oscillating frequency much different from the original. This indicates that the bias circuit shown in Fig. 5(a) can compensate for process variations only but cannot alleviate the effects due to changes of temperature

6 As to the circuit configuration shown in Fig. 5(b), its output voltage decreases when temperature increases but increases when process drifts toward slow. It can be seen that, with similar analysis described above, the output voltage of Fig. 5(b) can compensate for the variations in temperature only but will make it worse when process conditions drift. Fig. 5 Bias circuits for PMOS. (a) For process compensation. (b) For temperature Compensation (c) Proposed bias circuit To overcome the above-mentioned drawbacks of the conventional bias circuit, a bias voltage that can compensate both variations in temperature and process simultaneously is necessary to keep the oscillating frequency constant. Fig. 5(c) shows the circuit that generates the control voltage, Vctrl. Vctrl is generated with the combination of the MOS and BJT. The PMOS in Fig. 5(c) are used to compensate for the process compensation i.e., when process varies from fast to slow, its output voltage becomes smaller. The BJT makes output voltage changing inversely proportional to the temperature in order to compensate for the ambient temperature changes. Since the current in this bias circuit is small, the variation of Vctrl due to resistance is small and can be neglected. The voltage Vctrl in Fig. 5(c) has the correct characteristic needed to be used as a control voltage of the ring oscillator but its slopes versus temperature and process variation are not exactly what are needed. An N-times amplifier is used to obtain the correct slope. Fig. 6 shows the amplified Vctrl variations due to the changes of temperature and different process corners

7 III. EXPERIMENTAL RESULT A ring oscillator with five stages of differential buffer has been fabricated in a 0.6-μm CMOS SPTM technology. The micrograph of the fabricated oscillator is shown in Fig. 7. With a power supply of 4 volts, this oscillator is measured to operate at an average frequency of 680 KHz. This oscillator occupies an area of 0.075mm 2 and its power consumption is 0.4mW. Table I summarizes the measured performance of this design. Fig. 6 Vctrl under different process and temperature Fig. 7 Mirograph of the fabricated oscillator Supply Voltage Power Dissipation 4V 0.4mW Avg. Temperature Coeff ppm C Overall Variation (35 C to 115 C within chips in two lots) ±4.7% Area mm 2 Table I Characteristic Summary - 7 -

8 A conventional oscillator composed of an inverter chain is also fabricated on the same chip as a comparison. In order to measure the frequency variations due to drifts in process and due to varied temperatures, a total of 29 sample chips in two different lots are tested and measured over a temperature range of 35 C to 115 C. Fig. 8 gives the measured frequencies of the proposed oscillator over a wide temperature range while Fig. 9 gives that of the conventional oscillator. The average temperature coefficients of the inverter chain and the proposed oscillator are ppm C and ppm C, respectively i.e., for a temperature range of 35 C to 115 C, the frequency variations due to temperature are ±13.58% and ±0.85%. This experimental result shows that the proposed ring oscillator has a good immunity to temperature variations. Taking all the tested chips and temperature variations into account, the overall frequency variations are ±14.6% and ±4.7% for inverter chain and the proposed oscillator, respectively. From the frequency distribution in the measured result, the process doesn't drift significantly between these two lots. As a result, the performance of the process compensation in this design is not observed. Fig. 10 gives a simulated frequency characteristic in different process corners of a temperature compensated oscillator [8]. It shows that this temperature compensated circuit has a small temperature coefficient in the typical process but has a drastic change in other process corners. For the performance of the proposed oscillator in Fig. 11, it can be seen that the proposed circuits compensate both process and temperature variations simultaneously. Fig. 8 Measured frequencies of the proposed oscillator in differential chips and temperatures - 8 -

9 Fig. 9 Measured frequencies of the conventional inverter chain in different chips and temperatures Fig. 10 Simulated frequencies of a temperature compensated oscillator [8] Fig. 11. Simulated frequencies of the proposed oscillator - 9 -

10 IV. CONCLUSION A 4-V temperature and process compensated ring oscillator has been described. This oscillator can be fabricated in the standard CMOS process since it does not need any special process requirement. To minimize the variations of the oscillating frequency, a temperature and process compensated biasing technique is exploited. The maximum frequency variation is measured to be ±4.6% in 29 chips within two different lots and over a testing temperature range of 35 C to 115 C. This ring oscillator occupies an active area of 0.075mm 2. V. ACKNOWLEDGMENT The authors would like to thank the Chip Implementation Center of the National Science Council for chip fabrication ad die bonding. This work was supported by National Science Council, Taiwan, by Grant NSC E V. REFERENCES 1. K. Kurita et al., "PLL-based BiCMOS on-chip clock generator for very high-speed microprocessor," IEEE Journal of Solid-State Circuits, vol. 26, pp , Apr M.G. Johnson et al., "A variable delay line PLL for CPU-coprocessor synchronization," IEEE Journal of Solid-State Circuits, vol. 23, pp , Oct M. P. Flynn et al., "A 1.2-um CMOS Current-Controlled Oscillator," IEEE Journal of Solid-State Circuits, vol. 25, pp , Jul K. Kato et al., "A low-power 128-MHz VCO for monolithic PLL IC's," IEEE Journal of Solid-State Circuits, vol. 23, pp , Feb I. I. Novof et al., "Fully Integrated CMOS Phase-Locked Loop with 15 to 240 MHz Locking Range and +-50ps Jitter," IEEE Journal of Solid-State Circuits, vol. 30, pp , Nov J. G. Maneatis et al., "Precise Delay Generation Using Coupled Oscillators," IEEE Journal of Solid-State Circuits, vol. 28, pp , Dec J. G. Maneatis et al., "Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques," IEEE Journal of Solid-State Circuits, vol. 31, pp , Nov D. Min et al., "Temperature-Compensation Circuit Techniques for High-Density CMOS DRAM's," IEEE Journal of Solid-State Circuits, vol. 27, pp , Apr

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