Single-Ended to Differential Converter for Multiple-Stage Single-Ended Ring Oscillators

Transcription

1 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 1, JANUARY Single-Ended to Differential Converter for Multiple-Stage Single-Ended Ring Oscillators Yuping Toh, Member, IEEE, and John A. McNeill, Member, IEEE Abstract This paper presents an improved technique for single-ended to differential conversion that allows for the use of single-ended CMOS ring oscillators in an otherwise fully differential integrated circuit environment. An interpolating resistor network is used to derive a fully differential representation of the single-ended voltage-controlled-oscillator (VCO) signal. The technique preserves the fundamental noise performance of singleended ring oscillators in the presence of supply and substrate interference. Experimental results in a m CMOS process show the applicability of this technique at the VCO speeds of up to 1.3 GHz. Index Terms Jitter, phase noise, power-supply interference, power-supply noise, single-ended to differential conversion, substrate noise, voltage-controlled oscillator. I. INTRODUCTION ACHALLENGE in the design of integrated oscillators is the preservation of fundamental phase noise performance in the presence of supply and substrate interference. Although better fundamental phase noise performance is achieved with LC-based oscillators, CMOS ring oscillators are easier to integrate [1] and consume less die area. In either case, differential circuits and signals are often employed because of their good rejection of common-mode supply and substrate noise and their lower noise injection into other circuits. On the other hand, single-ended CMOS ring oscillators have better thermal noise performance than their differential CMOS counterparts and can achieve better phase-noise performance for a given power dissipation [2], [3]. The lower thermal noise jitter in single-ended ring oscillators (SROs) is largely due to the larger voltage swings than those available in differential ring oscillators (DROs). DRO voltage swings are typically limited to approximately a threshold voltage because of headroom constraints. Furthermore, it has been shown that saturated-type oscillators, which fully switch the devices in the delay cell, exhibit better phase-noise performance than nonsaturated-type oscillators [1]. SROs fall under the category of saturated-type oscillators. While their lower thermal noise jitter is attractive, SROs are susceptible to supply noise due to their single-ended signal path. Reducing this susceptibility with techniques such as capacitive bypassing and supply regulation [4], [5] provides a low-noise, single-ended clock signal with acceptable immunity to supply and substrate noise. However, it may be the case that the SRO is Manuscript received August 2, 2001; revised June 28, This work was supported by National Science Foundation under Award Y. Toh was with the Worcester Polytechnic Institute, Worcester, MA USA. He is now with Analog Devices, Wilmington, MA USA ( yuping.toh@analog.com). J. A. McNeill is with the Worcester Polytechnic Institute, Worcester, MA USA. Digital Object Identifier /JSSC Fig. 1. Single-ended to differential conversion circuit using a single phase and dc average of the ring. Waveforms for Fig. 1. used in an otherwise fully differential integrated circuit environment. As will be shown in Section II, it is difficult to develop a high-quality differential version of the single-ended ring signal. In Section III, an improved method of performing the singleended to differential conversion in a three-stage ring oscillator is described. Sections IV and V describe design considerations and experimental results; Section VI describes possible generalization to ring oscillators with more than three stages. II. SINGLE-ENDED TO DIFFERENTIAL CONVERSION Figs. 1 and 2 show two possible methods of performing single-ended to differential conversion of the output of a CMOS /03$ IEEE

2 142 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 1, JANUARY 2003 Fig. 2. Single-ended to differential conversion circuit using two phases of the ring. Waveforms for Fig. 2. SRO. In each case, a PMOS differential pair, formed by transistors and, is used as a simple comparator and level shifter to develop the desired output signals and, which are the differential representation of the single-ended ring signal. The differential pair is biased by current, which is developed by current source with bias voltage. Capacitor represents the sum of all parasitic capacitances at node. In the approach shown in Fig. 1, the comparator input is obtained from one phase of the ring and input from a half-amplitude reference developed by shorting the output and input of a replica ring stage. In the approach shown in Fig. 2, the comparator inputs are obtained from two phases of the ring [6]. This approach eliminates the need to develop the half-amplitude reference required in the approach of Fig. 1. Figs. 1 and 2 show the waveforms associated with each approach. Idealized waveforms are shown for comparator inputs and ; also shown are simulated output waveforms in a 0.35 m CMOS process. It can be seen from the simulated waveforms that outputs and deviate significantly Fig. 3. Improved single-ended to differential conversion circuit using interpolating resistor network. Waveforms for Fig. 3. from the ideal differential representation of the single-ended ring signal. The two major nonidealities are duty-cycle distortion and waveform asymmetry. The main cause of these nonidealities is the varying common mode of the inputs and, shown as the dashed waveform in Figs. 1 and 2. Although low-frequency common-mode variations are rejected by the differential pair, at higher frequencies, common mode rejection is reduced significantly due to. Variation in causes variation in the voltage, which in turn causes a variation in differential pair bias current in accordance with. This variation in results in amplitude variations at the differential pair output. III. IMPROVED CONVERSION TECHNIQUE A. Development of Improved Technique Fig. 3 shows the single-ended to differential conversion technique developed in this work. In this approach, the same differential pair is used but the inputs and are taken from an interpolating network. Assuming resistors R1 through

3 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 1, JANUARY R4 to be of equal value, the outputs of the interpolating network are given by (1) (2) The function of the interpolating network is to develop a differential representation of the SRO signal with a constant common mode component. To see how this function results, we first develop idealized expressions for the phase voltages,, and. At each stage of the ring, the oscillator waveform propagates with a phase lag of radians (due to the stage delay) as well as an inversion ( radians). Although the ring oscillator is often thought to be a square wave oscillator, at high speeds the waveforms in a three-stage ring are more nearly sinusoidal. If we idealize the waveforms to be sinusoidal with equal delay in each stage, then, the voltage waveforms at each phase can be represented as with sinusoid frequency, peak amplitude and dc average. Substituting (3) (5) into (1) and (2) and performing some trigonometric manipulation, gives Thus, (6) and (7) show that and constitute a signal pair with common mode and differential signal. Fig. 3 shows the waveforms associated with the approach of Fig. 3. The idealized waveforms for comparator inputs and show a constant common mode component. It can be seen that the simulated outputs and exhibit much improved duty cycle regularity and amplitude symmetry. In practice, is not constant since the signal from each phase of the voltage-controlled oscillator (VCO) is not purely sinusoidal; for a three-stage VCO operating near maximum speed the assumption of pure sinusoids is only approximately true. This results in some variation in, which causes small variations in and. This in turn causes the slight variation in the amplitudes of and as shown in the simulated waveforms in Fig. 3. Even with these slight variations, waveform symmetry shows significant improvement over the cases shown in Figs. 1 and 2 (3) (4) (5) (6) (7) Fig. 4. Noise model. IV. DESIGN CONSIDERATIONS A. Resistor Value In this work, the interpolating resistors through were implemented using N-well resistors with a nominal value of 20 k. This value results from an optimization between conflicting design drivers. A high resistance is desired so as to minimize current drawn from the VCO. The value of through cannot be increased arbitrarily for a number of reasons. A high value will reduce the maximum operating frequency of the circuit due to the RC lowpass formed between the resistor and the input gate capacitance of the differential pair transistors. Additionally, high-resistor values will increase thermal noise. B. Noise Fig. 4 shows a circuit model that can be used to determine the effect of noise from one of the interpolation resistors. Analysis of the effect on phase noise requires use of the impulse-sensitivity-function technique [7] due to the time-varying impedance at the delay stage output. Simulation shows that for the resistor values used in this work, the additional noise contribution does not significantly degrade VCO phase noise performance. In general, it may be the case that other design constraints dictate resistor values that would degrade VCO phase noise performance. In that case, the gate outputs could be buffered prior to interpolation. Although buffers would add jitter in the signal path to the eventual differential output, the jitter would be outside the VCO ring and would not accumulate. Note that noise of the PMOS differential pair (and of any subsequent sources referred to the PMOS differential pair input) is outside the VCO ring and does not accumulate. Therefore, VCO jitter performance is dominated by the jitter accumulated within the VCO ring. C. Resistor Matching The differential nature of the signal pair was derived assuming equal values of resistors in the and interpolating networks. The interpolation technique depends on resistor ratios and is therefore tolerant of process and temperature variations in absolute resistor values; however, the effects of mismatch must be considered. The analysis [8] is simplified by considering separately the effects of mismatch in the and interpolating networks. It can be shown that mismatch (in the network interpolating between phases and ) leads to a phase error in. Defining mismatch variables for and (8)

4 144 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 1, JANUARY 2003 Fig. 5. Chip micrograph. analysis [8] shows that the phase error is related to the fractional mismatch ( (in radians) for )by (9) Fig MHz VCO output waveform after division by 8. (10) In analogous fashion, mismatch (in the network interpolating between ring phase and the dc average signal ) leads to an amplitude error in. With mismatch variables (11) (12) analysis shows that the amplitude error for is related to the fractional mismatch by (13) or for the fractional amplitude error : (14) The results in (10) and (14) indicate that the matching requirements are modest: a fractional mismatch of 2% corresponds to a phase error of 1 or an amplitude error of 1%. V. EXPERIMENTAL RESULTS The VCO output buffer in this work was implemented in silicon using the TSMC 4-metal 1-poly 0.35 m CMOS process. A chip micrograph is shown in Fig. 5. The total area consumed by the VCO, interpolating resistors and differential pair level shifter is m m. At maximum speed, power consumption of the ring VCO core is 80 mw. Additional power consumption of the single-ended to differential conversion circuitry is 5.3 mw. The circuit has been operated at VCO speeds of up to 1.3 GHz. Fig. 6 shows the output waveform for a VCO frequency of 640 MHz after an on-chip divide-by-8. To examine performance in the presence of power supply noise, the circuit configurations of Figs. 1 and 3 were simulated with a 200-mV pk-pk, 100-MHz sine wave superimposed on the 3.3-V power supply. Zero-crossing times of the output differential waveforms are shown in Figs. 7 and. Jitter for the circuit using the improved technique is 1.73 ps rms, which Fig. 7. Simulated output, simple differential pair buffer [Fig. 1]. Jitter = 9.85-ps rms Horizontal: 5 ps/div. Vertical: 20 mv/div. Simulated output, improved differential pair buffer [Fig. 3]. Jitter = 1.73-ps rms Horizontal: 5 ps/div. Vertical: 20 mv/div. represents a 5 of Fig. 1. reduction from the 9.85-ps rms for the circuit VI. GENERALIZATION OF TECHNIQUE It is logical to consider whether this technique can be generalized to rings with more than three stages. One possible generalization, to expand the interpolating networks and connect

5 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 1, JANUARY alternate stages to alternate sides, is shown for the example of a seven-stage ring in Fig. 8. The most straightforward generalization assumes sinusoidal waveforms; this assumption is indicated with the sinusoid inside the gate symbol in Fig. 8. If the waveforms are sinusoidal, it can be shown that the interpolator outputs and will be sinusoidal waveforms 180 out of phase, with a constant common-mode component equal to. The general proof is mathematically cumbersome; an intuitive argument for plausibility can be seen from a phasor representation of the ring signals shown in Fig. 8. Grouping the phasors corresponding to each interpolator and finding the resultants gives two phasors of equal magnitude and opposite direction. Unfortunately, in a practical realization, the waveform in the ring becomes more like a square wave as more stages are added. With the sinusoidal assumption invalid, (6) and (7) no longer hold and the common-mode component of the interpolator outputs is no longer constant. Thus, the requirement for approximately sinusoidal signals prevents this technique from readily generalizing to longer rings. This is not a limitation to applicability of the technique, however; the need for this technique arose from the problems associated with the high frequency signals present in the three-stage ring oscillator. Fig. 8. Interpolation example for seven-stage ring. Phasor representation for seven-stage ring. VII. CONCLUSION An improved technique for single-ended to differential conversion has been presented that allows for the use of singleended CMOS ring oscillators in an otherwise fully differential integrated circuit environment. The technique preserves the fundamental noise performance of single-ended ring oscillators in the presence of supply and substrate interference. This technique uses an interpolating network of resistors to derive a fully differential representation of the single-ended VCO signal. Experimental results in a m CMOS process show the applicability of this technique at VCO speeds of up to 1.3 GHz. ACKNOWLEDGMENT The authors thank C. Liu for assistance with jitter simulations. The authors also thank the reviewers for their careful consideration and helpful comments. REFERENCES [1] C.-H. Park and B. Kim, A low-noise, 900-MHz VCO in 0.6-m CMOS, IEEE J. Solid-State Circuits, vol. 34, pp , May [2] T. H. Lee and A. Hajimiri, Oscillator phase noise: A tutorial, IEEE J. Solid-State Circuits, vol. 35, pp , Mar [3] A. Hajimiri, S. Limotyrakis, and T. H. Lee, Jitter and phase noise in ring oscillators, IEEE J. Solid-State Circuits, vol. 34, pp , June [4] J. M. Ingino, A 4 GHz 40 db PSRR PLL for an SOC application, in Dig. Tech. Papers ISSCC, Feb. 2001, pp [5] V. R. von Kaenel, A high-speed, low power clock generator for a microprocessor application, IEEE J. Solid-State Circuits, vol. 33, pp , Nov [6] D. Bowler, Jitter in single-ended CMOS ring oscillators, M.S. thesis, Worcester Polytechnic Institute, Worcester, MA, [7] A. Hajimiri and T. H. Lee, A general theory of phase noise in electrical oscillators, IEEE J. Solid-State Circuits, vol. 33, pp , Feb [8] Y. Toh, The effect of channel width on jitter in CMOS ring oscillators, M.S. thesis, Worcester Polytechnic Institute, Worcester, MA, 2002.