CMOS Dual Band Receiver GSM 900-Mhz / DSS-GSM1800-GHz

Transcription

1 CMOS Dual Band Receiver GSM 900-Mhz / DSS-GSM1800-GHz By : Dhruvang Darji Transistor integrated Circuit

2 A Dual-Band Receiver implemented with a weaver architecture with two frequency stages operating at 900MHz and 1.8GHz by using two Voltage Controlled Oscillator fabricated with 0.18µm CMOS technology. The receiver achieves total Gain of db at 900MHz and db at 1.8GHz of G, and dbm/ dbm of IIP3, dbm/ dbm of Noise Figure, while consuming mw of Power Consumption in a 1.8V supply Voltage. 1. Introduction T he main Goal of this project is to design a single dual band radio frequency receiver for GSM- 900MHz and GSM-1.8GHz communication system the simple block diagram of the given system in shown in Figure 1. Here two different antenna is used as the input impedance can be different for the two given input therefore two system are designed with such architecture. The main aim of the project was to attain low noise figure, optimum linearity, optimum Gain for the given communication Bands. The first block toward the designing process was to choose the appropriate architecture. Some of the architecture which were kept for were brief study and consideration were i) Superheterodyne Receiver architecture: the Superheterodyne receiver offers superior sensitivity, Frequency stability and selectivity. But the major drawback of Superheterodyne Receiver Is that the image frequency is received. LO and IF signals and harmonics and mixtures leaking to different places may cause problems ii) Direct Conversion Receiver Architecture: the disadvantages of the Superheterodyne receive are overcome i.e. there are no image band but the disadvantage of Direct conversion architecture is difficulties in implementation of dc offsets, leakage between RX and TX in full duplex operation, mixing spurs with direct conversion with even order distortion and flicker noise. iii) Image rejection Architectures like Heartley Architecture and Weaver Architecture. : this two architecture avoid the tradeoff between the image rejection and channel selection the further detail of this architecture is given in next block of description. Then in later part of the each design of building block of the system is discussed in detail based on Weaver Architecture, and at results of Spurs and comparison of experimental and hand calculated results summarizes the report. From Figure 1 we observe that two different frequency are been transformed to intermediate Frequency(IF) and then added after the channel selection further given to analog to digital converter (ADC). In this given architecture we find a heavy tradeoff between image rejection and channel selection. Figure 1: 900Mhz 1.8GHz Dual Band Receiver 2. Image Reject Receiver Architecture The objective of this Architecture is to eliminate image rejection filters and move channel selection to the baseband. Hartley Architecture Hartley s circuit mixes the RF input with the quadrature outputs of the local oscillator (LO) and low pass filters and shifts the results by 90 before adding them together. It can be shown that at point A and B contain the desired channel with the same polarity and the image with opposite polarity. The summed output is therefore free from the image.

3 translates this component to 2ω2-ωin-2ω1, i.e., image of the signal with respect to ω2, and mixing with ω2 brings it to ω2-ωin1+ω1, the same IF at which the signal appears. Figure 2: Hartley Image Rejection [1] The principal drawback of the Hartley architecture is its sensitivity to mismatches with phase and gain imbalance, the image is only partially cancelled. The influence of gain and phase mismatch on image rejection can be studied by lumping the mismatches of the mixers, the low-pass filters, the two ports of the adder, and the 90 phase-shift network into the error terms A and Ө for the gain and phase mismatches, respectively, between the two paths in the Hartley architecture. Figure 3: Weaver Architecture [2] Weaver Architecture Weaver architecture [4] is an extension of Hartley architecture. It can work as a modulator as well as image reject receiver. The architecture is shown in figure 3. Weaver architecture implements two consecutive quadrature down conversion on the signal such that the image is suppressed while adding at the output or else they are inverted so eliminated by adding at the output. Weaver topology avoids the issues related to RC- CR networks: resistance and capacitance variations, degradation of IRR as the frequency departs from 1/ (R1C1), attenuation, and noise. The weaver architecture must deal with a secondary image if the second IF is not zero. Illustrated in Figure 4, this effect arises if a component at 2ω2-ωin1+2ω1 accompanies the RF signal. Downconversion to the first IF Figure 4: Secondary Image in Weaver Architecture [1] 3. Receiver Architecture As shown in Figure 5 the receiver architecture, to employ 450- and 1350-MHz LO frequencies, we postulate that the transmitter must incorporate two upconversion steps: from baseband to an intermediate frequency (IF) of 450 MHz and from 450 to 900 MHz or 1.8 GHz. We also recognize that a simple mixer driven by the 450- MHz IF and the 1350-MHz LO generates the 900- MHz and 1.8-GHz signals with equal amplitudes, necessitating substantial filtering to suppress the unwanted component. It is therefore desirable to perform the second upconversion by singlesideband (SSB) mixing

4 Figure 5 Receiver Schematic Circuit is then undergo second quadrature Downconversion operation. The LNA and mixer of the two band are separate to allow flexibility in choice of device dimension and bias current, thus optimizing the performance in each path. For the second down conversion two quadrature down conversion mixer is provided both for I Q baseband output. Figure 6 Dual Band Receiver Architecture As shown in figure 3 given architecture the signal received is given to duplexer to perform band selection. The next step would be a Low Noise Amplifier (LNA) and two quadrature mixer which boosts and translates the IF to 450MHz the result The in receiver LO1 is set to midway between 900MHz and 1.8GHz bands, making two band images of each other. So RF mixing is highside for 900MHz and low side for 1.8GHz. The band select switches between two i.e. 900Hz and 1.8GHz. Also band select switch controls the addition and subtraction at the receiver output in order to generate the desired signal and reject image component. The Gain, Noise, Linearity play a vital role in the receiver s overall performance. Necessary iterations were made to achieve the optimum solution Transistor integrated Circuit

5 Even this Architecture suffers from disadvantages in context with direct conversion receiver. For example DC Offset due to selfmixing of the second LO, Flicker Noise, even I-Q mismatch degrades the down converted signal. 4. Building Blocks The design of Building blocks were designed with many iterations and trades of over noise, linearity, gain and power consumption. A. Low Noise Amplifier An LNA [1] is a key component which is placed at the front-end of a RF Communication circuit. Using an LNA, the effect of noise from subsequent stages of the receive chain is reduced by the gain of the LNA, while the noise of the LNA itself is injected directly into the received signal. Thus, it is necessary for an LNA to boost the desired signal power while adding as little noise and distortion as possible. This enables retrieval of the signal in the later stages of the system. A good LNA has a low NF (e.g. 2 db), a large enough gain (e.g. 20 db) and should have large enough intermodulation and compression point (IP3 and P1dB). Low noise amplifiers are one of the basic building blocks of any communication system. The purpose of the LNA is to amplify the received signal to acceptable levels with minimum self-generated additional noise. Gain, NF, non-linearity and impedance matching are four most important parameters in LNA design. There are few topologies by which optimum Results of LNA can be achieved. Iteration in topologies were for example 1) common Gate LNA, 2) Common Source LNA, 3) Inductor less LNA, 4) cascade Source degenerative LNA. Cascaded Source Degenerative LNA description and design specification are shown below. B. LNA + Mixer To achieve a relative low noise figure and a reasonable Input match, the LNA employs a common-source cascade stage with inductive degeneration [1]. To avoid uncertainties due to bond wire inductance, both the source inductor and the drain inductor or are integrated on the chip. Drawing approximately 5 ma from the supply, the LNA exhibits a noise figure of less than 4.5 db and IP 3 of greater than -2dBm. The parasitic capacitance of L 2 the drain junction and overlap capacitance of M 2, and the input capacitance of the mixers resonate with L 2 at the frequency of interest. With a Q of about three, this resonance lowers the image signal by approximately 10 db The LNA directly drives the quadrature RF mixers, which are configured as single-balanced circuits. Employing inductive loads to minimize thermal noise, each mixer drains 2 ma to achieve a reasonable tradeoff between noise and nonlinearity. With 39 db of voltage gain in the LNA, it is desirable to realize an of greater than 1.26 V (equivalent to 15dBm in a 50- interface) in the mixer, while maintaining its input-referred noise voltage below roughly 5 nv/ Hz 1/2. The dimensions of the LO input transistor play a key role in performance of a Mixer. Transistor is sized such that its overdrive voltage is sufficiently large to guarantee the required IP 3. Transistors LO input and in Fig. 7 also influence the noise and conversion gain of the mixer. The choice of the width of these devices is governed by a tradeoff between their switching time and the parasitic capacitances they introduce at node For a given (sinusoidal) LO swing, and are simultaneously on for a shorter period of time as their width increases. A compromise is thus reached by choosing (W/L)=200μm/0.18µm, allowing the pair to turn off with a differential swing of 100 mv while degrading the conversion gain by less than 1 db.

6 The interface between the LNA and the mixer merits particular attention. As shown in Fig. 6, to achieve a well-defined bias current in the mixer, the LNA incorporates the dc load with diodeconnected devices and Neglecting the dc drop across L, we note that V GS4 + V GS5 = V GS7 + V GS7 Thus, proper rationing of biasing transistor of LNA with respect to Input LO transistor of Mixer defines I d7 as a multiple I 2 of Capacitor C provides an ac ground at the source of so that the output resistance of does not degrade Q of LO 2. Realized as an NMOS transistor, C consists of a large number of gate fingers to reduce the channel resistance, achieving a Q of greater than 30 at the frequency of interest. In contrast to ac coupling techniques, the above approach incurs no signal loss, but it consumes some voltage headroom. Interestingly, Interface Transistor of LNA can serve as the current source for another circuit, e.g., an oscillator, thus reusing the bias current of the LNA. Figure 7: LNA with Mixer Biasing (Interface) Circuit Figure 9: P 1dB of LNA1.8Ghz Figure 8: RF Mixer 900Mhz 1.8GHz Noise Figure 4.02dB 3.92dB IIP 3-4dB -6dB S11-12dB -8.25dB S21 18dB 14dB P 1dB -9.17dB dB Gain 28.4dB 39.5dB

7 Figure 10: Mixer TestBench

8 Figure11: inputs given to mixer (a)vif (b)vlo Figure12:output after low pass amplifier Figure13:output from the mixer Figure14:differential output after LPF Figure 14: Output after Low Pass Amplifier Figure 13: Vin and VLO input to the mixer Figure 12: Differential Output after LPF Figure 11: output from Mixer

9 Table 1: LNA Stimulated Results Figure 17 Band Switching in IF Mixer [2] Figure 15: Gain, Noise Figure, S11 C. IF Mixer Figure 16: Transient Analysis RF Mixer The differential input of RF mixer is capacitive coupled to the input of the IF mixer, allowing independent biasing. With over all voltage gain of 39dB in LNA and Mixer, the linearity of IF tends to limit the performance of Receiver. The addition and subtraction discussed before has to be incorporate in RF stage. To avoid voltage headroom limitations at the output of the mixer, this function is implemented by switching the polarity of one of the differential signals generated by the RF mixers (Figure 12). The switching network is present in both signal paths to equalize the delays, but only one of the paths is controlled by the band-select input and the other is hard-wired. Figure 18 IF Mixer As shown in Figure 13 the IF mixer has double balanced circuit topology with transistor with vinn, vinp as input pair baseband and!baseband! as current multiplexer, vlop and vlon as switching Transistors. Whole circuit drain current is 1mA, input transistors are sized which can incorporate an over drive voltage of approx. 500mV, therefor achieving Ip3 of 18dB. The low transconductance of input transistors together

10 with voltage headroom limitations ultimately results in a slight voltage conversion loss of about -2 db in the IF mixer. The current multiplexer performs the switching function illustrated in Fig. 12. chosen. Figure 21: Simple Cross Coupled VCO [1] Figure 19: Noise Figure IF Mixer D. Voltage Controlled Oscillator Balanced NMOS VCO. The only losses being assumed in Figure 2.2 are those associated with the inductor. In reality there would also be losses associated with the variable capacitors (varactors) and the MOSFETs (the active devices). In practical integrated VCOs the inductors are on-chip spiral inductors with low quality factor that dominates the losses of the VCO tank. The quality factor QL of the inductor is given by An LC tank VCO can be thought of as two 1-port networks connected together. Figure 20: RLC Tank [1] One 1-port represents the frequency selective tank where the oscillations occur and the other 1-port represents the active circuit that cancels the losses in the tank. Oscillations can occur when i) the negative conductance of the active network cancels out the positive conductance (loss) of the tank ii) the closed loop gain has zero phase shift. Conditions i) & ii) above amount to a closed loop gain greater than or equal to unity magnitude with no imaginary component. The first step in designing an oscillator is to choose a circuit topology or type. For this example a balanced NMOS VCO will be Figure 22: VCO 1350MHz/450MHz Schematic Diagram

11 Q L = ω LR Where, ω is the oscillation frequency [rad/s]. L is the value of the inductance [H]. R is inductor s equivalent series resistance [Ω]. QL in practical silicon RF IC processes ranges from 5 to 10. Values of on-chip inductances range from 0.1 nh to 10 mh in practical RF IC processes. It can be shown that the oscillation frequency of the circuit shown in Figure 15-16, assuming ideal varactors and MOSFETs is given by ω = 1 2 LC 2 1 R2 C L It can also be shown, under the same set of assumptions that the gm of each MOSFET must be gm RC/ L for oscillation to occur. plot is shown below Figure 24: Bandpass Filter Response 5. Spurious Response An important concern in Heterodyne and image rejection receiver is the translation of various interferes to the desired channel frequency after Downconversion. Owing to nonlinearities and switching operations in each mixers, an interference at f int results in component at kf int + mf LO. With two down conversion using LO 1 and LO 2 the down conversion spurs appears at kf int ± mf LO1 ± mf LO2, many of which may fall in the desired based band channel. Since in band interferers are not filtered before channel selection and since they are located on the same side of f LO1 as the desired signal, they are not suppressed by the image rejection technique used in the receiver Figure 23: VCO 1.8GHz Periodic Phase Noise E. Baseband Filter Baseband filter or we can see image reject filter which is added at the output of RF mixer before giving it to IF mixer. Image rejection is required to get desired frequency In this Receiver system we have use a 500MHz Low Pass Filter with R=160Ω and C=2pF the Bode Figure 25: spurious component downconverted to baseband (a) effect of in band interference (b) most significant spur combination [2]

12 It is also important to know that spurious response is not exercise in single noise figure measurement, but it revels the performance of the receiver. The spurious response of a dual band receiver has been examined with the aid of spreadsheet program. Five interference frequencies in each band were found to be the most significant sources of downconverted spurs. Fig. 20 (b) illustrates the mixing mechanisms that generate in-channel components. Random mismatches in the RF mixers together with the finite bandwidth of the IF bandpass filter yield another type of spur that results from mixing of the RF input and harmonics of the second LO. In addition to input-dependent spurious response, some other tones are observed that result from mixing of the LO signals themselves. The most significant of these is given byf LO1-3f LO2. Another affect arises in 1.8GHz mode is the receiver signal corruption by image before the first down conversion. As illustrated in Fig. 16, if a strong image Component at 900 MHz accompanies the desired signal, second-order distortion in the LNA creates the second harmonic of the image, thereby degrading the signal-to-noise ratio SNR in the DCS1800 band. Nevertheless, since the Duplexer suppresses the image considerably, the corruption is negligible. Simulations indicate that if a 98-dBm 1800GHz signal and a 30-dBm 900-MHz image are applied to the receiver, the output of the LNA exhibits an SNR of 50 db provided the duplexer attenuates the image by 40 db. With a fully differential LNA/mixer design, this effect would be even less critical. Figure 26: Second Order distortion in 1800MHz band 6. Experimental Results 900MHz 1.8GHz Noise Figure 3.8dB 4.2dB IIP 3-8dBm -6dBm Image 40dB 36dB Rejection Power 84mW 90mW Dissipation Voltage Gain 31dBm 39dBm Supply Voltage 1.8V Technology 0.18µm Table 2: Experimental Result for Dual Band Receiver

13 Reference: [1] B. Razavi, RF Microelectronics, Englewood Cliffs, NJ: Prentice-Hall, [2] S. Wu and B. Razavi, A 900-MHz/1.8-GHz CMOS receiver for dual band applications, in ISSCC Dig. Tech. Papers, Feb. 1998, pp [3] R. Hartley, Modulation system, U.S. Patent , Apr [4]D. K. Weaver, Jr., A third method of generation and detection of single-sideband signals, Proc. IRE, pp , June [5] D. K. Shaeffer and T. H. Lee, A 1.5V, 1.5GHz CMOS low noise amplifier, in Symp. VLSI Circuits Dig. Tech. Papers, June 1996, pp [6] D. K. Weaver, Jr., A third method of generation and detection of single-sideband signals, Proc. IRE, pp , June 1956.