ECEN620: Network Theory Broadband Circuit Design Fall 2014

Transcription

1 ECEN60: Network Theory Broadband Circuit Design Fall 014 Lecture 13: Frequency Synthesizer Examples Sam Palermo Analog & Mixed-Signal Center Texas A&M University

2 Agenda Frequency Synthesizer Examples Design of Frequency Synthesizers for Short Range Wireless Transceivers A Multi-Standard Frequency Synthesizer

3 Design of Frequency Synthesizers for Short Range Wireless Transceivers Ari Y. Valero - López Department of Electrical Engineering Analog & Mixed-Signal Center Texas A&M University A M S C February 3 th, 004 3

4 Most Popular Wireless Standards WirelessLAN a (5.5GHz, 54Mbps, 50m) 11b (.45GHz, 11Mbps, 100m) 11g (.45GHz, 4Mbps, 100m) Short Range Wireless UWB ( GHz, 110Mbps, 10m) Bluetooth (.45GHz, 1Mbps,10m) 4

5 Frequency Synthesizer in a Wireless Communication System Downconverter LNA Baseband Processing (Channel Select Filter, VGA) ADC Receiver T/R Switch 90 o Frequency Synthesizer Digital Signal Processor Transmitter Modulator RF Radio Upconverter Digital Baseband Analog Baseband Where does a Frequency Synthesizer fits in a Radio Transceiver? 5

6 Function of a Frequency Synthesizer in a Radio Received Signal Desired Channel f RF The Frequency Synthesizer generates the required frequency reference for selection of a communication channel Syn. Output Desired Tone Receiver Output f LO The desired channel is downconverted to a frequency corresponding to: f F = f RF - f LO f F 6

7 Frequency Synthesizer Building Blocks VCO and Frequency Divider operate f in at high frequency PFD UP DWN VDD Loop Filter VCO f out θ in f div Phase Detector R1 Loop Filter C VCO f out θ div Charge Pump C1 PFD, Charge Pump and LPF generate proper control voltage of VCO Frequency Divider 1 N Frequency Divider θ in = θ div f in = f div = f out /N 7

8 FS for Bluetooth Receiver.4GHz MHz Demodulator RF filter LNA PLL Polyphase Filter Offset Cancellation /Decision Bluetooth Low F Receiver in 0.35µm CMOS f REF PFD Charge Pump LPF VCO f OUT Frequency Divider Modulus Selection 8

9 Micrograph Phase Noise Measurement Results Tuning Range: GHz PN: -10dBc / 1MHz Frequency Step 1MHz Power: 1 ma 9

10 Dual Mode Receiver BT Wi-Fi reset Pipeline Pipeline Digital MUX RF N LNA Gain control Measure signal level Wi-Fi -15dB Attenuator.45GHz BT LPF BT: BW=600kHz Wi-Fi: BW=6MHz reset VGA with offset cancellation BT: 0/4dB, 1 stage Wi-Fi: 0-6dB, 3 stage Pipeline Pipeline Digital MUX ADC BT: 11-bit 11MHz Wi-Fi: 8-bit 44MHz Phase Switching Block Programmable Divider 15/16 Prescaler 4.9GHz VCO LPF CP PFD f ref = MHz Direct Conversion Bluetooth/Wi-Fi Receiver 10

11 Frequency Synthesizer Specifications Frequency Range Channel Spacing Settling time (max) Phase Noise Center frequency accuracy Bluetooth GHz 1 MHz 0 µs MHz ±75 khz EEE 80.11b GHz 5 MHz 4 µs MHz ±60 khz Bluetooth specifications are more stringent Complying with Bluetooth specs covers WiFi 11

12 Frequency Synthesizer Architecture An nteger N Frequency Synthesizer architecture is used. The VCO oscillates at 5 GHz to accommodate all the standards (requires 10% tuning range). A Divide-by- generates quadrature outputs for BT and 80.11b..45GHz Bluetooh EEE 80.11b Programmable Divider Phase Switching Block 15/16 Prescaler f ref = MHz PFD CP LPF VCO 4.9GHz 1

13 Design Considerations Phase Margin φ φ m m = tan = tan 1 1 ω ω C C p 1 z tan tan 1 ω ω z p 1 C1 + 1 C ω n /ω c Damping Factor ξ ω -3dB /ω c Phase Margin [Degrees] Phase Margin [Degrees] t lock Settling Time Nfref ln ε 1 ζ = ωnζ 1 ( ξ ξ 1) ln ω n ( Nfref ξ 1 + ξ ) ε 1 ξ τ ζ = ζ < 1 ζ > 1 K pd K f N K vco = sin ( φm ) ( φ ) cos m ω ω ( ζ + 1) + ( ζ + 1) 1 3 db = n + Design Parameters Loop Bandwidth VCO Gain Charge Pump Current Loop Filter Components 13

14 Loop Filter cp + K vco = 300MHz/V cp = 35 µa C 1 = 340 pf C = 6.15 pf R1 N = 450 R 1 = 5.6 kω Vo C1 C - Trade offs Settling Time Close-in Phase Noise Total Capacitance Charge Pump Current Loop Bandwidth = 35 khz Phase Margin = 60 14

15 Capacitance Multiplier Schematic Model Vdd M3 i in in M4 1:M V biasp 5 µa Z in Z 0 i 1 Mi 1 C B A M 1:M M1 V biasn z in z0 = M

16 Loop Filter Layout Active Filter. Reduced area 40µm x 80µm Passive Filter. Reduced spurs 430µm x 780µm Active vs. Passive 16

17 Phase Switching Prescaler Architecture f in / 5 GHz To Mixers LO Port Phase switching prescaler for reduced power consumption compared with traditional architectures. / f in / f in /4 / / /.5 GHz 1.5 GHz p 0 p p 4 p 6 p 1 p 3 p 5 p 7 Phase Selection Phase Selection Mux 65 MHz f in /8 Total Current: 4 ma Modulus Control f out Modulus Control 15/16 Dual Modulus 17

18 Phase Switching Prescaler Circuit Operation f in /4 / p 0 p p 4 p 6 Phase Selection Mux / p 1 p p 5 GHz p 65 7 MHz Phase Selection f in /8 Modulus Control f out Modulus Control p 5 p 6 p 7 Mux f out

19 Phase Switching Prescaler.45GHz mplementation: High Frequency D Flip-flop Vdd CLK D Phase Switching Block D 15/16 Prescaler R R D D CLK CLK V bias bias 1 st stage nd stage 3 rd stage bias 500 µa 375 µa 50 µa R 1 kω 1.3 kω kω 19

20 Measurement Results Phase Noise Settling Time Phase Noise: -14 3MHz Settling time : 150 µs (0 µs spec) 0

21 Measurement Results Output Spectrum / Mismatch Tuning Range: GHz Worst case measurement Phase error 3 Magnitude error 1dB 1

22 Summary of FS Testing Results Parameter Value Units Frequency Range GHz Phase Noise -14 3MHz Settling Time 150 µs Reference Spur -35 dbc Power Consumption 31.5 mw / Mismatch Phase Amplitude < 3 < 1 db

23 Summary of Testing Results Power Consumption Distribution Total current consumption = 1.5mA with buffers Digital 0.6mA CP, CM, Bias 0.4mA VCO 3mA 5GHz Buffer 1.5mA Prescaler 4mA.4 GHz Buffers 3mA 3

24 Die Micrograph Die Area: 1 mm Package: TFP 18pins Synthesizer Area: 1.87 mm 4

25 A Multi-standard Frequency Synthesizer Sung Tae Moon April 4, 003 5

26 Bluetooth + WLAN 80.11b Specification Bluetooth WLAN 80.11b Band.4~.48.4~.47 GHz Channel 1 MHz 5 MHz Settling 39 µs MAX 0 µs MAX Phase noise 14 dbc 16 MHz Accuracy ±75 khz ±60 khz 6

27 Bluetooth + WLAN 80.11b Specification 1MHz Bluetooth MHz 80.11b Non-overlapping MHz 80.11b Overlapping

28 What s the Challenge? Limited loop bandwidth : 100 khz Results in slow settling Adaptive dual-loop PLL Wide band VCO Necessary Multi-frequency bands to allow for low K VCO and wide tuning range Automatic calibration to switch between bands 8

29 Adaptive Dual-loop PLL Auxiliary Loop PFD CP Dead-zone H VCO f REF PFD1 CP1 L Loop Filter %N 9

30 Adaptive Dual-loop PLL Less costly solution to limited loopbandwidth problem Flexible Loop-bandwidth Glitch problem between bandwidth switching Smooth transition using dead-zone mproved dead-zone control 30

31 Dead-zone Control Digital Control PFD CP Dead-zone H VCO f REF PFD1 CP1 L Loop Filter %N 31

32 MATLAB simulation 3

33 Wide-Band VCO with Calibration D0 D1 Vc Vc Discrete capacitor array Without array, tuning gain is too high With array, both wide band operation and low tuning gain are achieved Comparator loop for automatic calibration 33

34 Automatic Calibration H LO Comparator PLL VCO 34

35 Next Time Fractional-N Frequency Synthesizers 35