CMOS RFIC Design for Direct Conversion Receivers. Zhaofeng ZHANG Supervisor: Dr. Jack Lau

Transcription

1 CMOS RFIC Design for Direct Conversion Receivers Zhaofeng ZHANG Supervisor: Dr. Jack Lau

2 Outline of Presentation Background Introduction Thesis Contributions Design Issues and Solutions A Direct Conversion Pager Receiver Conclusion

3 Research Goal Low Cost Process: CMOS Device is good enough Improved passive components Integration level Minimize external components Minimize IC area and pin numbers Low Power High integration = low power Low power individual block design System architecture is important

4 Heterodyne Receivers High IF: more than 2 down-conversions Best sensitivity Need off-chip image-rejection SAW filters and channel-selection filters Highest cost, high power, low integration Low IF Relaxed image-rejection requirement compared to high-if No DC offset problem Quadrature LO is required Flicker noise may be a problem High integration level, low cost

5 Homodyne Receivers I Pros LNA! Simple architecture! No image problem! No 50ohm interfaces! High integration level! Lowest cost, low power 90º Cons Q! DC offsets! Flicker noise! LO leakage! Even-order distortion

6 Outline of Presentation Background Introduction Thesis Contributions Design Issues and Solutions A Direct Conversion Pager Receiver Conclusion

7 Thesis Contribution (I) On-chip cross-talk and substrate noise was studied and shielding schemes were proposed [RFIC1998, Baltimore]. Flicker noise under switching conditions was studied experimentally for the first time and a simple flicker noise model was proposed [CICC2001, San Diego]. Square-law based harmonic mixing technique was proposed to solve DC offset and LO leakage problem in a CMOS process [RAWCON2000, Denver].

8 Thesis Contribution (II) A lateral bipolar harmonic mixer was developed for solving both DC-offset and flicker noise problem [RAWCON2001, Boston]. A direct-conversion RF front-end was developed [ISCAS2001, Sydney]. Fully-integrated single-chip pager in a CMOS process was demonstrated [ISSCC2001, SFO].

9 Outline of Presentation Thesis Contributions Background Introduction Design Issues and Solutions A Direct Conversion Pager Receiver Conclusion

10 Origin of Problem! DC offsets! Flicker noise! LO leakage! Even-order distortion! Linearity requirement! Noise requirement! IQ mismatch All problems are limited by the mixer design! The mixer: the most critical component! Our research focus!

11 DC Offsets & LO LO Leakage Leakage Zero IF + Offset The offset originates from self-mixing. It can be as large as mv range at the mixer output. It varies with the environment and moving speed of the mobile and changes with time. The maximum bandwidth can be as large as khz range. LO leakage forms an interference to other receivers.

12 Spectrum Illustration Power Narrow Band DC offset Power Broad Band High-pass corner DC Offsets Frequency Frequency Power Flicker noise Frequency Power Signal Frequency Offset-Free

13 Existing Solutions on DC Offset AC coupling or high pass filtering Autozeroing or double sampling Offset cancellation in digital domain Double LO frequency method [ISSCC99] Adaptive dual-loop algorithm combined with the mixer [RAWCON00] Pulse-width-modulation based bipolar harmonic mixer [CICC97] However, these methods are either not so effective or very complicated, or not suitable for CMOS process.

14 Proposed Harmonic Mixing RF Signal LO Leakage f rf f lo =f rf BB Signal DC Offset 0 Conventional RF Signal LO Leakage f lo =f rf /2 f rf 2f lo =f rf BB Signal 0 f lo Our Work

15 Square-law Based Mixer RF Voltage No Coupling Current 2 IF Vrf+ 3V Vrf- Voltage LO Vlo+ Vlo- LO leakage free. Ideally self-mixing free. Current controlled switching. No noise contribution from LO stage.

16 Flicker Noise Reduction 3V Vrf+ I 0 Vlo- Vrf- Vlo+ Flicker noise is proportional to the current. Current injection is used to reduce flicker noise. No noise contribution from current source too.

17 Offset Cancellation Gain (db) TSMC0.35µ >35dB LO Input Power (dbm)

18 Noise Performance Noise 10kHz (db) Injected Current I 0 (µa)

19 How to improve more? However, flicker noise is still too large due to CMOS devices, minimum noise figure achieved is larger than 10kHz for CMOS harmonic mixer. It requires a high gain and low noise LNA to overcome flicker noise while the front-end linearity suffers. For a narrow-band communication system such as FLEX pager, the noise requirement at low frequency is very tough. It is well known that bipolar device is a good candidate to eliminate flicker noise. But, can we do it in a CMOS process and how good is the device? YES!

20 Lateral Bipolar Transistor in a Bulk CMOS Process Base W.T. Holman95 Emitter Gate Emitter P+ N+ Collector Ground Gate Vertical Collector Base Lateral Collector

21 Physical Model of LBJT Gate D. Mac98 Collector M1 Q1 Emitter Base Q3 Q2 Base P-Sub P-Sub Pure LBJT: M1, Q3 off, Q1, Q2 on.

22 Gummel Plot of LBJT TSMC0.35µ β>40 at mas max f T 4GHz

23 LBJT Harmonic Mixer VDD VLO+ M1 M2 VLO- VRF+ Q1 I i Q2 VRF- OUT- OUT+ RL RL

24 Noise Performance Large LO improves noise.

25 Even Order Distortion RF Signal a 1 x+a 2 x 2 +a 3 x 3 + BB Signal Interference IM2 (f 2 -f 1 ) f 1 f 2 f rf 0 It is mainly introduced by layout asymmetry and device mismatch. Since direct-conversion, the intermodulation components IM2 will fall into the demodulated signal spectrum. Therefore, good IIP2 is required for homodyne receivers. It is found that varying the loading resister or voltage bias can compensate the device mismatch and improve IIP2 significantly.

26 IIP2 Improvement Same DC bias IIP2=18dBm Compensation IIP2>40dBm

27 LBJT Mixer Performance Technology VDD Signal Gain DC offset suppression Noise 10kHz 1dB compression point Input-referred IP3 Input-referred IP2 Power consumption TSMC 3M2P 0.35µm 3V +15dB >30dB <18dB >-20dBm >-9dBm >+40dBm <2.2mW

28 Summary on Mixer Flicker noise free, corner frequency is below 10kHz. DC offset free, more than 30dB DC offset suppression is achieved. No LO leakage problem. Sufficient IIP2 after bias compensation. High gain and low power consumption. Complete CMOS process. Suitable for CMOS direct conversion applications.

29 Outline of Presentation Background Introduction Thesis Contributions Design Issues and Solutions A Direct Conversion Pager Receiver Conclusion

30 db Difficulties in FLEX Pager FLEX 6400, 4FSK khz Big Challenges Narrow band modulation Significant energy near DC High pass filtering is not viable DC offset problem Flicker noise is significant 12dB Eb/N0 10 BER High pass corner (Hz) Eb/N0 (db) DC Offset Effect High pass effect

31 4-FSK Pager Receiver AGC LNA 45 VCO RF: Zhaofeng BB: Zhiheng DEMOD AGC Fully differential architecture to reject substrate noise. Harmonic mixers are used to solve time-varying DC offset. Peak detectors are used to cancel static DC offset. High front-end gain and current injection to reduce flicker noise.

32 LNA Non-quasi-static phenomenon makes it unnecessary to do on-chip matching. Off-chip matching by a single inductor and a balun. S11 930MHz Both on-chip and off-chip inductive loads were tried.

33 Double Balanced Mixer Improve the linearity; Provide constant impedance to LNA; Current injection provides more than 20dB flicker noise reduction.

34 Ring Oscillator Half RF frequency, Provide 45 phase.

35 AGC Gain: -14.5dB~18.6dB. The linear resistor R0 is used to improve the linearity. The signal level is sensed by the peak detector.

36 Static DC Offset Cancellation Zero-IF 4-FSK Signal Peak Detector Fmin 200Hz

37 Low Pass Filter 0-20 Gain [db] Frequency [khz] 5 th order elliptic gyrator-c filter Pass-band gain 6.2dB, ripple 0.5dB ( 9kHz) Stop-band attenuation 63dB ( 17.8kHz)

38 Noise Performance Front End Base Band

39 Performance Summary Front-End Off-chip ind On-chip ind Pager receiver with off-chip ind RF/BB gain: 51.13dB 40.33dB Maximum Gain: 62dB IIP3: 11.5dB 5.8dB -26dBm 24.0dB 15.0dB -20.7dBm Noise 14.5dB Overall DC offset at LPF output: <1mV (Signal: 400mV) IIP2: -10dBm -5.6dBm Power dissipation: 58mW Operating frequency: 930.1MHz Technology: TSMC0.35µm 4M2P LO frequency: 465MHz Die area: 4.6 mm 2 IQ gain mismatch: < 0.3dB Baseband (Zhiheng) IQ phase mismatch: < 5 RF/BB over LO/BB: > 54dB Self-mixing free Input matching: < -20dB Power dissipation: 52.76mW AGC gain: -14.5dB~18.6dB LPF: Pass-band gain-6.2db, ripple 0.5dB ( 9kHz) Stop-band attenuation 63dB ( 17.8kHz) Offset cancellation: <2mV (under ±100mV input offset) Input Referred Noise: 600nV/ 10kHz Clock Recovery: Capture range > 550Hz Power dissipation: 5.4mW (including all testing buffers)

40 OSC DEMOD LNA OSC LNA Die Photo AGC LNA 45 VCO DEMOD AGC RF Front-End Mixer Mixer AGC LPF Base Band Circuitry [Zhiheng] RF Front-End

41 Summary on Pager Receiver Feasibility of direct conversion has been demonstrated. Proposed harmonic mixing technique solves selfmixing induced DC offset problem successfully. With the help of static DC offset cancellation, the total DC offset is less than 1mV at the receiver output. The modified ZIFZCD 4-FSK demodulator functions correctly. A 4-FSK FLEX pager receiver in a single chip has been implemented successfully.

42 Outline of Presentation Background Introduction Thesis Contributions Design Issues and Solutions A Direct Conversion Pager Receiver Conclusion

43 Conclusion Circuit design for direct-conversion has been discussed. DC offset: more than 30dB improvement LO leakage: no longer a problem Flicker noise: corner frequency is less than khz due to lateral bipolar device. IIP2: larger than +40dBm after bias compensation. System on chip has been successfully demonstrated using CMOS direct conversion architecture. Crosstalk has been studied and can be improved more than 20dB with proposed shielding method. Flicker noise under switching has been studied and a flicker noise model has been proposed.

44 Crosstalk & Substrate Noise Signal Leakage Switching noise Substrate noise Device noise Interference Inductive coupling Capacitive coupling Inductor induced noise Line-line crosstalk Very bad for high-level integration!

45 Crosstalk in RFPCB Near end crosstalk S21 (db) Thickness-distance ratio (h/d)

46 Crosstalk in RFIC Near end crosstalk S21 (db) Separation distance (µm)

47 Shielding Schemes Air w d w SiO2 P- Epi (~20 Ω-cm) Method I P+ Bulk (~0.05 Ω-cm) Air w d w P- Epi (~20 Ω-cm) Method II P+ Bulk (~0.05 Ω-cm) Air w d w Air w d w P- Epi (~20 Ω-cm) Method III P+ Bulk (~0.05 Ω-cm) P- Epi (~20 Ω-cm) Method IV P+ Bulk (~0.05 Ω-cm)

48 Crosstalk Comparison Near end crosstalk S21 (db) Separation distance (µm) No shielding Method I Method II Method III Method IV

49 Summary on Crosstalk Crosstalk in RFIC: about -30~-40dB at GHz range. Separation is pointless. Proper shielding provides excellent crosstalk immunity, crosstalk can be improved by 20~40dB. Receiver gain can be improved due to reduced feedback effect through substrate. Penalty: One metal layer may be sacrificed.

50 Flicker Noise CMOS is the best candidate for low cost and high integration, but flicker noise may be a problem in homodyne receivers, how to reduce it? Flicker noise under static bias was well studied and modeled, but how about under switching conditions, such as in mixers? Will this correlated noise respond to the switching signal? If yes, how and how much? The flicker noise performance usually depends on measurements. Is it possible to optimize the flicker noise in the circuits without any measurements?

51 Measurement Setup Dynamic Signal Analyzer 3V RL 512 SR780 RL /2 DS345 84/2

52 Methodology Complicated Non-linear System Assumption Frequency Independent Non-linear System Enough Output Bandwidth High Frequency Switching Low Frequency Switching + Frequency Dependent Linear System Low Pass Filtering Solution Fortunately, the assumption is true, we will see.

53 Output PSD (dbm/hz) Fast Switching (Switching frequency > 100kHz) Switching frequency independent. 1MHz Switching 500kHz Switching 200kHz Switching Square Wave VGS=0.6V VPK=0.5V Frequency (KHz)

54 Slow Switching (Switching frequency < 100kHz) -132 Output PSD (dbm/hz) Frequency (KHz)

55 Base Band Output Noise Output 1kHz (dbm/hz) VGS(V)

56 Proposed Noise Model 1/f v 2 G(t)v G( t) = k =0 g k cos( kω t) 0 Gate voltage noise is used. Linearized model: AM modulations and noise superposition. Valid for most cases except LIN-OFF switching! Where g 0 reflects base band noise, g 1 reflects noise at switching frequency. They are important to mixers and VCOs.

57 Model Verification (With different switching) Noise ratio g 0 /g 1 (db) Line: Simulation Symbol: Measured Swing amplitude VPK (V) 0.6

58 Summary on Flicker Noise Flicker noise mechanism under switching conditions has been explored experimentally. Flicker noise should be modeled as a gate voltage noise. Not-so-hard switched flicker noise can be modeled by AM modulations and output noise is the superposition of up-converted flicker noise. Noise optimization through simple simulations becomes possible with the proposed model. Results can be used directly in harmonic mixer design.