Fractional- N PLL with 90 Phase Shift Lock and Active Switched- Capacitor Loop Filter
|
|
- Winfred Long
- 5 years ago
- Views:
Transcription
1 J. Park, F. Maloberti: "Fractional-N PLL with 90 Phase Shift Lock and Active Switched-Capacitor Loop Filter"; Proc. of the IEEE Custom Integrated Circuits Conference, CICC 2005, San Josè, 21 September 2005, pp xx IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
2 IEEE 2005 CUSTOM INTEGRATED CIRCUITS CONFERENCE Fractional-N PLL with 90º Phase Shift Lock and Active Switched-Capacitor Loop Filter Joohwan Park (1), and Franco Maloberti (2) (1) University of Texas at Dallas, P.O.Box , Richardson, TX 75083, USA. (2) Department of Electronics, University of Pavia, Pavia, Italy. Abstract-This paper describes a new possibility of fully integrated fractional-n phase locked loop (PLL). The approach uses switched-capacitor fully differential low pass filter (LPF) instead of huge continuous-time filter. The discrete-time operation has the potential to provide a phase noise enhancement (PNE) block, variable gain, to improve noise. The circuit is implemented in 2.8 mm 2 including all capacitors and modulator using 0.25 µm CMOS process. The proposed PLL achieves a phase noise of -102 dbc at 600 khz and spur level of -80 dbc with mid-band frequency. Power dissipation is 30 mw with a 3-V supply. I. INTRODUCTION Mobile communication architectures use PLL able to comply with the frequency hopping requirements and provide low phase noise output in the IF receiver and the up conversion transmitter. The targets must be possibly accomplished with all the components fabricated in a single chip. This is not always possible since the filtering requirements for the low-pass filter often lead to external capacitors or demand for large silicon area that, in turn, increases the cost. In the present solutions in locked loop conditions one of the current generator of the phase frequency detector (PFD) switches on for a very short time. The noise on rise and fall time of the current pulse is affecting the accuracy of the circuit operation. Moreover, the continuous-time filtering of high frequency components is, in some extent, problematic. If the loop-bandwidth is very narrow, the phase-noise is good, but the locking time and the channel switching time increase [1]. The best would be using a dynamic control of the loop filter response that enhances the phase noise when the PLL is in the lock state. A fractional frequency results from a periodic change of the division factor between two (or more) integer numbers. Using of a sigma delta modulator obtains a fractional control with a good noise shaping. However, even if the N/N+1 divider control is well randomized, there is extra fluctuation in the VCO control. Thus, the loop filter design becomes more challenging. The solution can be the use of programmable loop filter [2], employing dual path [3] or multiple charge pumps [4]. In general the problems associated to the uncertainty between acquisition mode and phase lock mode lead to a longer PLL settling time. This paper describes a fractional-n PLL that uses a PFD with 90º phase-shift lock. The feature reduces the rise and fall time influence and enhances the charge pump linearity. Moreover, the 90º phase-shift feature enables an operation in the sampled-data domain. Thus, it is possible to implement the loop filter using the switched capacitor technique and obtain on-chip filtering functions that can be digitally programmable. The proposed approach has been proved with a fully integrated version. The PLL employs a source couple multivibrator [5] with 133-MHz free running frequency. However, the approach can be used with other types of VCO and higher operating frequency. II. PROPOSED METHOD The two inputs of a PFD are the reference and the output of the fractional divider. In the lock conditions, the frequencies of the two inputs are equal and a possible phase shift is the information used to control the VCO. We observe that the reference can be the basis for a clock (at low frequency). Therefore, having the reference signal facilitates a lowfrequency sampled-data processing. Assume that the phase shift of the PFD inputs, REF and Output, is as shown in Fig. 1, 90º. A simple logic can generate the control signals X1 and X2. They are used to switch-on the equal current generators of the PFD; a third switch resets the integrating capacitor at the end of the half-period of the reference. Fig. 1 Illustration of the basic concept used in the paper /05/$ IEEE. P
3 Fig. 2 Proposed loop filter The 90º phase shift makes equal to zero the voltage across the capacitor immediately before the reset. If the shift is larger we have a negative voltage, the opposite if the shift is smaller. Obviously, the reset of the capacitor can be done through a virtual ground, thus obtaining the input of a sampled-data circuit. Observe that it is problematic using the method for 0º phaseshift: The integration of the current into a capacitance is obviously possible but the timing of measurement and the reset phase can be properly defined only using a delayed version of the reference. III. SWITCHED CAPACITOR LOOP FILTER Fig. 2 shows a possible fully differential loop filter to be associated with the 90º phase shift PFD. The charge stored on the sampling capacitances at the end of phase 1 is the input of the low-pass active filter. Assuming that the reference signal is in the MHz range, the required bandwidth of the OTA is few ten of MHz, thus requiring limited power consumption. The reference frequency and the maximum swing V M allowed by the current generators of the PFD determine the relationship between the capacitor C s and the current in the PFD, I PFD. Assume that full-scale input signal of the SC filter is V M. With 0º phase shift, the upper current generator is switched on for 1/(2 f R ) while the lower one never switches on. Thus IV. FRACTIONAL-N PLL WITH SC FILTER LOOP Fig. 3 shows the block diagram of the designed fractional-n PLL. It is composed of a PFD (with the charge pump), sampling capacitor, switched capacitor filter, smoothing filter, voltage controlled oscillator (VCO), divider and sigma-delta modulator. Once in lock, the sigma-delta modulator will control the output to get fractional frequency and it will convert the systematic fractional sidebands to random noise. Actually, the cascade of a switched capacitor and a continuous-time section makes the loop filter. Since the clock frequency of the SC is the reference frequency, the continuous-time is a simple RC which pole is at 0.06f R. The loop filters used MIM capacitors. The resistor of the RC smoothing is a 100 KΩ poly structure. The VCO is a modified version of the source-coupled multivibrator. The architecture was selected just to demonstrate the capability to fully integrate the PLL. The free-running oscillation frequency is relatively low (133-MHz). The method is quite general: the use of oscillator with LC tank would give a higher free-running frequency with the need of a pre-scalar. A detailed description of the VCO is given below. The resolution obtained by the second-order sigma delta is 1- MHz/2 7. The design uses a standard cell approach and the total area is 0.5 x 0.4 mm. A. VCO Description The circuit diagram of the source-coupled multivibrator is shown Fig. 4. It is the CMOS version of a well know bipolar configuration. The oscillation frequency depends on the capacitor size and amount of current through it. Two additional sections (in the dashed blocks) enable the frequency control. The two sections change the core bias currents in the positive or negative direction under the control of a differential signal. The capacitance C is 1.1pF, the currents I 1 and I 2 are 1mA and 0.2mA respectively. The resulting range of frequency variation is ±25MHz. The degeneration resistances in the additional blocks help in improving the linearity of the control block. Simulation results show that by optimizing the transistor sizes for minimizing the 1/f noise while keeping the speed leads to good linearity and reasonable phase noise. C s V M = I PFD 2 f R (1) with V M = 0.4V and f R = 1MHz a current I PFD = 0.8µA gives C s = 1pF. The ratio between C S and C R gives the dc gain of the SC filter. The value of the sampling capacitance and the capacitances of the SC filter are suitable for a fully integrated implementation. The filter in Fig. 2 is a simple low-pass. Either using a single OTA or with more than one OTA is possible to realize more complex filtering functions. Moreover, the use of digitally programmable capacitances enables a digital control of the loop filter. Fig. 3 Discrete time PLL 330 P-34-2
4 Fig. 4 Modified VCO with current control circuit V. PHASE NOISE ENHANCEMENT The use of an active sampled-data control instead of a simple continuous-time filter provides good flexibility and programmability. In order to reduce the phase noise, it is necessary to desensitize the VCO control when the loop is in the lock zone. This is what is done in [4] is to use digitally programmable multiple charge pumps. The action is equivalent to a programmable gain in the signal at the output of the charge pump. This chip includes a gain control section that, at the same time decouple the charge pump section by the loop SC filter. The circuit schematic is shown in Fig. 5. It includes two OTA. The first is a inverting unity-gain buffer. The next stage is the SC loop filter with programmable gain. A sensing block detects the voltage level at the output of the buffer and changes the gain by 6dB. The control is simple but suitable for demonstrating the flexibility of the used approach. Fig. 6 shows the plot of the forward signal as a function of the sensing voltage. The response is non-linear with a jump at the transition points. The region with low gain is for operation in the locked mode. The threshold is ±5mV and is big enough to account for the fluctuations due to noise and spurs contributions. A signal above 5mV indicates the non-locked mode: the gain jumps up by 6 db. The given response is the optimum for limiting the locking time degradation. Simulation results, verified by experimental measurement show that with a full gain the locking time is 180 µsec with the phase noise enhancement the locking time is 200 µsec. Fig. 6 Variable gain with PNE Fig. 5 Phase noise enhancement block and fully differential LPF P
5 VI. EXPERIMENTAL RESULT The fully differential phase locked loop discussed in previous sections has been fabricated in a 0.25-µm CMOS technology with 2.8 mm 2 of active area (Fig. 7). Because the LPF size is drastically decreased, the switch capacitor PLL becomes suitable for a full integration. With proper shielding, the noise coupling is blocked from digital block to analog and VCO. In addition, large on-chip PMOS capacitor is used to maintain a small bounce on the supply. The power dissipation is 30 mw from a 3-V supply. Fig. 8 shows the voltages across the sampling capacitors in lock conditions. The signal has the expected triangular shape due to the charging and discharging phases. The trigger of the scope synchronizes itself during the first and second of the reference period. The fractional-n synthesizer locks properly at MHz. A 128/129 dual divider brings the frequency of the VCO down to the 1MHz used by the reference. The free-running frequency of the VCO is MHz, close to the designed value 133-MHz. Fig. 9 shows the measured phase noise without and with the PNE function. Results show that the PNE reduces the spur level below -80 dbc. Fig. 9 Phase noise measurement: without PNE (solid) with PNE (dashed) Moreover, the phase noise at 600 khz is as low as -102 dbc; 5 db better than without the enhancement circuit. Multiple gain values and a smart digital control possibly permit 15 db of phase noise improvement. The spur level is not completely satisfactory. Continuous-time solutions obtain better results. However, the result is still comparable with other published figures [3]. VII. CONCLUSION In the paper, we demonstrate possibility of a fully on-chip design and phase noise enhancement in the fractional-n PLL. A switched capacitor LPF enables on-chip implementation being only 50pF used for the fully differential LPF. The used capacitance is at least ten times smaller than a continuous-time counterpart. The use of switched capacitor active processing offers the benefit of digital control filtering. As an example the chip includes a phase noise enhancement circuit: it reduces the loop gain in the lock conditions and permits a 5 db reduction of the phase noise. Therefore, the proposed approach and the experimental verifications open new perspective for the design of fully integrated fractional-n PLL. Fig. 7 PLL die photograph Fig. 8 Sampling capacitor waveform REFERENCES [1] E. Temporiti, G. Albasini, I. Bietti, R. Castello and M. Colombo, A 700-kHz bandwidth fractional synthesizer with spurs compensation and linearization techniques for WCDMA application, IEEE J. Solid- State Circuits, vol. 39, Sep [2] P. Jacobs, J. Janssens, T. Geurts and J.Crols, A 0.35µm CMOS fractional-n transmitter for 315/433/868/915 MHz ISM applications, European Solid-State Circuits, Sept [3] Z. Shu, K. L. Lee and B. H. Leung, A 2.4-GHz ring-oscillator-based CMOS frequency synthesizer with a fractional divider dual-pll architecture, IEEE J. Solid-State Circuits, vol. 39, Mar [4] D. Boerstler, A low-jitter PLL clock generator for microprocessors with lock range of MHz, IEEE J. Solid-State Circuits, vol. 34, Apr [5] P. Gray, P. Hurst, S. Lewis and R. Meyer, Analysis and design of analog integrated circuits, Fourth Ed., New York: John Wiley, P-34-4
An 11 Bit Sub- Ranging SAR ADC with Input Signal Range of Twice Supply Voltage
D. Aksin, M.A. Al- Shyoukh, F. Maloberti: "An 11 Bit Sub-Ranging SAR ADC with Input Signal Range of Twice Supply Voltage"; IEEE International Symposium on Circuits and Systems, ISCAS 2007, New Orleans,
More informationACTIVE SWITCHED-CAPACITOR LOOP FILTER. A Dissertation JOOHWAN PARK
FRACTIONAL-N PLL WITH 90 o PHASE SHIFT LOCK AND ACTIVE SWITCHED-CAPACITOR LOOP FILTER A Dissertation by JOOHWAN PARK Submitted to the Office of Graduate Studies of Texas A&M University in partial fulfillment
More informationA Random and Systematic Jitter Suppressed DLL-Based Clock Generator with Effective Negative Feedback Loop
A Random and Systematic Jitter Suppressed DLL-Based Clock Generator with Effective Negative Feedback Loop Seong-Jin An 1 and Young-Shig Choi 2 Department of Electronic Engineering, Pukyong National University
More informationModulator with Op- Amp Gain Compensation for Nanometer CMOS Technologies
A. Pena Perez, V.R. Gonzalez- Diaz, and F. Maloberti, ΣΔ Modulator with Op- Amp Gain Compensation for Nanometer CMOS Technologies, IEEE Proceeding of Latin American Symposium on Circuits and Systems, Feb.
More informationDESIGN OF MULTIPLYING DELAY LOCKED LOOP FOR DIFFERENT MULTIPLYING FACTORS
DESIGN OF MULTIPLYING DELAY LOCKED LOOP FOR DIFFERENT MULTIPLYING FACTORS Aman Chaudhary, Md. Imtiyaz Chowdhary, Rajib Kar Department of Electronics and Communication Engg. National Institute of Technology,
More informationA 3-10GHz Ultra-Wideband Pulser
A 3-10GHz Ultra-Wideband Pulser Jan M. Rabaey Simone Gambini Davide Guermandi Electrical Engineering and Computer Sciences University of California at Berkeley Technical Report No. UCB/EECS-2006-136 http://www.eecs.berkeley.edu/pubs/techrpts/2006/eecs-2006-136.html
More informationOn the Design of Single- Inductor Multiple- Output DC- DC Buck Converters
M. Belloni, E. Bonizzoni, F. Maloberti: "On the Design of Single-Inductor Multiple-Output DC-DC Buck Converters"; IEEE Int. Symposium on Circuits and Systems, ISCAS 2008, Seattle, 18-21 May 2008, pp. 3049-3052.
More informationPhase Locked Loop Design for Fast Phase and Frequency Acquisition
Phase Locked Loop Design for Fast Phase and Frequency Acquisition S.Anjaneyulu 1,J.Sreepavani 2,K.Pramidapadma 3,N.Varalakshmi 4,S.Triven 5 Lecturer,Dept.of ECE,SKU College of Engg. & Tech.,Ananthapuramu
More information/$ IEEE
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 53, NO. 11, NOVEMBER 2006 1205 A Low-Phase Noise, Anti-Harmonic Programmable DLL Frequency Multiplier With Period Error Compensation for
More informationSingle-Ended to Differential Converter for Multiple-Stage Single-Ended Ring Oscillators
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 1, JANUARY 2003 141 Single-Ended to Differential Converter for Multiple-Stage Single-Ended Ring Oscillators Yuping Toh, Member, IEEE, and John A. McNeill,
More informationDesign of Phase Locked Loop as a Frequency Synthesizer Muttappa 1 Akalpita L Kulkarni 2
IJSRD - International Journal for Scientific Research & Development Vol. 3, Issue 03, 2015 ISSN (online): 2321-0613 Design of Phase Locked Loop as a Frequency Synthesizer Muttappa 1 Akalpita L Kulkarni
More informationNEW WIRELESS applications are emerging where
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 4, APRIL 2004 709 A Multiply-by-3 Coupled-Ring Oscillator for Low-Power Frequency Synthesis Shwetabh Verma, Member, IEEE, Junfeng Xu, and Thomas H. Lee,
More informationECEN620: Network Theory Broadband Circuit Design Fall 2014
ECEN60: Network Theory Broadband Circuit Design Fall 014 Lecture 13: Frequency Synthesizer Examples Sam Palermo Analog & Mixed-Signal Center Texas A&M University Agenda Frequency Synthesizer Examples Design
More informationDESIGN AND VERIFICATION OF ANALOG PHASE LOCKED LOOP CIRCUIT
DESIGN AND VERIFICATION OF ANALOG PHASE LOCKED LOOP CIRCUIT PRADEEP G CHAGASHETTI Mr. H.V. RAVISH ARADHYA Department of E&C Department of E&C R.V.COLLEGE of ENGINEERING R.V.COLLEGE of ENGINEERING Bangalore
More informationTHE reference spur for a phase-locked loop (PLL) is generated
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 54, NO. 8, AUGUST 2007 653 Spur-Suppression Techniques for Frequency Synthesizers Che-Fu Liang, Student Member, IEEE, Hsin-Hua Chen, and
More informationCHAPTER 6 PHASE LOCKED LOOP ARCHITECTURE FOR ADC
138 CHAPTER 6 PHASE LOCKED LOOP ARCHITECTURE FOR ADC 6.1 INTRODUCTION The Clock generator is a circuit that produces the timing or the clock signal for the operation in sequential circuits. The circuit
More informationISSCC 2003 / SESSION 20 / WIRELESS LOCAL AREA NETWORKING / PAPER 20.2
ISSCC 2003 / SESSION 20 / WIRELESS LOCAL AREA NETWORKING / PAPER 20.2 20.2 A Digitally Calibrated 5.15-5.825GHz Transceiver for 802.11a Wireless LANs in 0.18µm CMOS I. Bouras 1, S. Bouras 1, T. Georgantas
More informationFrequency Synthesizers for RF Transceivers. Domine Leenaerts Philips Research Labs.
Frequency Synthesizers for RF Transceivers Domine Leenaerts Philips Research Labs. Purpose Overview of synthesizer architectures for RF transceivers Discuss the most challenging RF building blocks Technology
More informationA CMOS Phase Locked Loop based PWM Generator using 90nm Technology Rajeev Pankaj Nelapati 1 B.K.Arun Teja 2 K.Sai Ravi Teja 3
IJSRD - International Journal for Scientific Research & Development Vol. 3, Issue 06, 2015 ISSN (online): 2321-0613 A CMOS Phase Locked Loop based PWM Generator using 90nm Technology Rajeev Pankaj Nelapati
More informationDesign of a Frequency Synthesizer for WiMAX Applications
Design of a Frequency Synthesizer for WiMAX Applications Samarth S. Pai Department of Telecommunication R. V. College of Engineering Bangalore, India Abstract Implementation of frequency synthesizers based
More informationTime- interleaved sigma- delta modulator using output prediction scheme
K.- S. Lee, F. Maloberti: "Time-interleaved sigma-delta modulator using output prediction scheme"; IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 51, Issue 10, Oct. 2004, pp. 537-541.
More informationA PROCESS AND TEMPERATURE COMPENSATED RING OSCILLATOR
A PROCESS AND TEMPERATURE COMPENSATED RING OSCILLATOR Yang-Shyung Shyu * and Jiin-Chuan Wu Dept. of Electronics Engineering, National Chiao-Tung University 1001 Ta-Hsueh Road, Hsin-Chu, 300, Taiwan * E-mail:
More information5.5: A 3.2 to 4GHz, 0.25µm CMOS Frequency Synthesizer for IEEE a/b/g WLAN
5.5: A 3.2 to 4GHz, 0.25µm CMOS Frequency Synthesizer for IEEE 802.11a/b/g WLAN Manolis Terrovitis, Michael Mack, Kalwant Singh, and Masoud Zargari 1 Atheros Communications, Sunnyvale, California 1 Atheros
More informationAn Analog Phase-Locked Loop
1 An Analog Phase-Locked Loop Greg Flewelling ABSTRACT This report discusses the design, simulation, and layout of an Analog Phase-Locked Loop (APLL). The circuit consists of five major parts: A differential
More informationA 2.2GHZ-2.9V CHARGE PUMP PHASE LOCKED LOOP DESIGN AND ANALYSIS
A 2.2GHZ-2.9V CHARGE PUMP PHASE LOCKED LOOP DESIGN AND ANALYSIS Diary R. Sulaiman e-mail: diariy@gmail.com Salahaddin University, Engineering College, Electrical Engineering Department Erbil, Iraq Key
More informationI. INTRODUCTION. Architecture of PLL-based integer-n frequency synthesizer. TABLE I DIVISION RATIO AND FREQUENCY OF ALL CHANNELS, N =16, P =16
320 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, VOL. 56, NO. 2, FEBRUARY 2009 A 5-GHz CMOS Frequency Synthesizer With an Injection-Locked Frequency Divider and Differential Switched Capacitors
More informationDedication. To Mum and Dad
Dedication To Mum and Dad Acknowledgment Table of Contents List of Tables List of Figures A B A B 0 1 B A List of Abbreviations Abstract Chapter1 1 Introduction 1.1. Motivation Figure 1. 1 The relative
More informationIntegrated Circuit Design for High-Speed Frequency Synthesis
Integrated Circuit Design for High-Speed Frequency Synthesis John Rogers Calvin Plett Foster Dai ARTECH H O US E BOSTON LONDON artechhouse.com Preface XI CHAPTER 1 Introduction 1 1.1 Introduction to Frequency
More informationLINEAR IC APPLICATIONS
1 B.Tech III Year I Semester (R09) Regular & Supplementary Examinations December/January 2013/14 1 (a) Why is R e in an emitter-coupled differential amplifier replaced by a constant current source? (b)
More informationA VCO-based analog-to-digital converter with secondorder sigma-delta noise shaping
A VCO-based analog-to-digital converter with secondorder sigma-delta noise shaping The MIT Faculty has made this article openly available. Please share how this access benefits you. Your story matters.
More informationA10-Gb/slow-power adaptive continuous-time linear equalizer using asynchronous under-sampling histogram
LETTER IEICE Electronics Express, Vol.10, No.4, 1 8 A10-Gb/slow-power adaptive continuous-time linear equalizer using asynchronous under-sampling histogram Wang-Soo Kim and Woo-Young Choi a) Department
More informationTaheri: A 4-4.8GHz Adaptive Bandwidth, Adaptive Jitter Phase Locked Loop
Engineering, Technology & Applied Science Research Vol. 7, No. 2, 2017, 1473-1477 1473 A 4-4.8GHz Adaptive Bandwidth, Adaptive Jitter Phase Locked Loop Hamidreza Esmaeili Taheri Department of Electronics
More informationDesign of a 3.3-V 1-GHz CMOS Phase Locked Loop with a Two-Stage Self-Feedback Ring Oscillator
Journal of the Korean Physical Society, Vol. 37, No. 6, December 2000, pp. 803 807 Design of a 3.3-V 1-GHz CMOS Phase Locked Loop with a Two-Stage Self-Feedback Ring Oscillator Yeon Kug Moon Korea Advanced
More informationLow Power Phase Locked Loop Design with Minimum Jitter
Low Power Phase Locked Loop Design with Minimum Jitter Krishna B. Makwana, Prof. Naresh Patel PG Student (VLSI Technology), Dept. of ECE, Vishwakarma Engineering College, Chandkheda, Gujarat, India Assistant
More informationLow- Power Third- Order ΣΔ Modulator with Cross Couple Paths for WCDMA Applications
C. Della Fiore, F. Maloberti, P. Malcovati: "Low-Power Third-Order ΣΔ Modulator with Cross Couple Paths for WCDMA Applications"; Ph. D. Research in Microelectronics and Electronics, PRIME 2006, Otranto,
More informationA Fast Locking Digital Phase-Locked Loop using Frequency Difference Stage
International Journal of Engineering & Technology IJET-IJENS Vol:14 No:04 75 A Fast Locking Digital Phase-Locked Loop using Frequency Difference Stage Mohamed A. Ahmed, Heba A. Shawkey, Hamed A. Elsemary,
More informationA SiGe 6 Modulus Prescaler for a 60 GHz Frequency Synthesizer
A SiGe 6 Modulus Prescaler for a 6 GHz Frequency Synthesizer Noorfazila Kamal,YingboZhu, Said F. Al-Sarawi, Neil H.E. Weste,, and Derek Abbott The School of Electrical & Electronic Engineering, University
More informationBehavior Model of Noise Phase in a Phase Locked Loop Employing Sigma Delta Modulator
Behavior Model of Noise Phase in a Phase Locked Loop Employing Sigma Delta Modulator Tayebeh Ghanavati Nejad 1 and Ebrahim Farshidi 2 1,2 Electrical Department, Faculty of Engineering, Shahid Chamran University
More informationLecture 7: Components of Phase Locked Loop (PLL)
Lecture 7: Components of Phase Locked Loop (PLL) CSCE 6933/5933 Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides are borrowed from various books, websites, authors pages,
More informationBootstrapped ring oscillator with feedforward inputs for ultra-low-voltage application
This article has been accepted and published on J-STAGE in advance of copyediting. Content is final as presented. IEICE Electronics Express, Vol.* No.*,*-* Bootstrapped ring oscillator with feedforward
More informationTwo- Path Band- Pass Σ- Δ Modulator with 40- MHz IF 72- db DR at 1- MHz Bandwidth Consuming 16 mw
I. Galdi, E. Bonizzoni, F. Maloberti, G. Manganaro, P. Malcovati: "Two-Path Band- Pass Σ-Δ Modulator with 40-MHz IF 72-dB DR at 1-MHz Bandwidth Consuming 16 mw"; 33rd European Solid State Circuits Conf.,
More informationArchitectures and Design Methodologies for Very Low Power and Power Effective A/D Sigma-Delta Converters
0 Architectures and Design Methodologies for Very Low Power and Power Effective A/D Sigma-Delta Converters F. Maloberti University of Pavia - Italy franco.maloberti@unipv.it 1 Introduction Summary Sigma-Delta
More informationA Wide-Bandwidth 2.4GHz ISM Band Fractional-N PLL with Adaptive Phase Noise Cancellation. Outline
A Wide-Bandwidth 2.4GHz ISM Band Fractional-N PLL with Adaptive Phase Noise Cancellation Ashok Swaminathan,2, Kevin J. Wang, Ian Galton University of California, San Diego, CA 2 NextWave Broadband, San
More informationLecture 160 Examples of CDR Circuits in CMOS (09/04/03) Page 160-1
Lecture 160 Examples of CDR Circuits in CMOS (09/04/03) Page 160-1 LECTURE 160 CDR EXAMPLES INTRODUCTION Objective The objective of this presentation is: 1.) Show two examples of clock and data recovery
More informationA multi-band single-loop PLL frequency synthesizer with dynamically-controlled switched tuning VCO Samuel, A.M.; Pineda de Gyvez, J.
A multi-band single-loop PLL frequency synthesizer with dynamically-controlled switched tuning VCO Samuel, A.M.; Pineda de Gyvez, J. Published in: Proceedings of the 43rd IEEE Midwest Symposium on Circuits
More informationPerformance Enhanced Op- Amp for 65nm CMOS Technologies and Below
Aldo Pena Perez and F. Maloberti, Performance Enhanced Op- Amp for 65nm CMOS Technologies and Below, IEEE Proceeding of the International Symposium on Circuits and Systems, pp. 21 24, May 212. 2xx IEEE.
More informationMultiple Reference Clock Generator
A White Paper Presented by IPextreme Multiple Reference Clock Generator Digitial IP for Clock Synthesis August 2007 IPextreme, Inc. This paper explains the concept behind the Multiple Reference Clock Generator
More informationA Fully Integrated CMOS Phase-Locked Loop With 30MHz to 2GHz Locking Range and ±35 ps Jitter
University of Pennsylvania ScholarlyCommons epartmental Papers (ESE) epartment of Electrical & Systems Engineering 7-1-2003 A Fully Integrated CMOS Phase-Locked Loop With 30MHz to 2GHz Locking Range and
More informationPhase interpolation technique based on high-speed SERDES chip CDR Meidong Lin, Zhiping Wen, Lei Chen, Xuewu Li
5th International Conference on Computer Sciences and Automation Engineering (ICCSAE 2015) Phase interpolation technique based on high-speed SERDES chip CDR Meidong Lin, Zhiping Wen, Lei Chen, Xuewu Li
More informationPublication [P3] By choosing to view this document, you agree to all provisions of the copyright laws protecting it.
Publication [P3] Copyright c 2006 IEEE. Reprinted, with permission, from Proceedings of IEEE International Solid-State Circuits Conference, Digest of Technical Papers, 5-9 Feb. 2006, pp. 488 489. This
More informationResearch and Development Activities in RF and Analog IC Design. RFIC Building Blocks. Single-Chip Transceiver Systems (I) Howard Luong
Research and Development Activities in RF and Analog IC Design Howard Luong Analog Research Laboratory Department of Electrical and Electronic Engineering Hong Kong University of Science and Technology
More informationLow Power, Wide Bandwidth Phase Locked Loop Design
Low Power, Wide Bandwidth Phase Locked Loop Design Hariprasath Venkatram and Taehwan Oh Abstract A low power wide bandwidth phase locked loop is presented in the paper. The phase frequency detector, charge
More informationA Sub-0.75 RMS-Phase-Error Differentially-Tuned Fractional-N Synthesizer with On-Chip LDO Regulator and Analog-Enhanced AFC Technique
A Sub-0.75 RMS-Phase-Error Differentially-Tuned Fractional-N Synthesizer with On-Chip LDO Regulator and Analog-Enhanced AFC Technique Lei Lu, Lingbu Meng, Liang Zou, Hao Min and Zhangwen Tang Fudan University,
More informationA 9.5mW 4GHz WCDMA Frequency Synthesizer in 0.13µm CMOS
A 9.5mW 4GHz WCDMA Frequency Synthesizer in 0.13µm CMOS Xinhua Chen and Qiuting Huang Integrated Systems Laboratory Swiss Federal Institute of Technology (ETH) Gloriastrasse 35, CH-8092 Zurich, Switzerland
More informationECE1352. Term Paper Low Voltage Phase-Locked Loop Design Technique
ECE1352 Term Paper Low Voltage Phase-Locked Loop Design Technique Name: Eric Hu Student Number: 982123400 Date: Nov. 14, 2002 Table of Contents Abstract pg. 04 Chapter 1 Introduction.. pg. 04 Chapter 2
More informationA Low Power Single Phase Clock Distribution Multiband Network
A Low Power Single Phase Clock Distribution Multiband Network A.Adinarayana Asst.prof Princeton College of Engineering and Technology. Abstract : Frequency synthesizer is one of the important elements
More informationA 10-Gb/s Multiphase Clock and Data Recovery Circuit with a Rotational Bang-Bang Phase Detector
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.16, NO.3, JUNE, 2016 ISSN(Print) 1598-1657 http://dx.doi.org/10.5573/jsts.2016.16.3.287 ISSN(Online) 2233-4866 A 10-Gb/s Multiphase Clock and Data Recovery
More informationAnalysis of Phase Noise Profile of a 1.1 GHz Phase-locked Loop
Analysis of Phase Noise Profile of a 1.1 GHz Phase-locked Loop J. Handique, Member, IAENG and T. Bezboruah, Member, IAENG 1 Abstract We analyzed the phase noise of a 1.1 GHz phaselocked loop system for
More informationNOWADAYS, multistage amplifiers are growing in demand
1690 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, VOL. 51, NO. 9, SEPTEMBER 2004 Advances in Active-Feedback Frequency Compensation With Power Optimization and Transient Improvement Hoi
More informationISSCC 2006 / SESSION 20 / WLAN/WPAN / 20.5
20.5 An Ultra-Low Power 2.4GHz RF Transceiver for Wireless Sensor Networks in 0.13µm CMOS with 400mV Supply and an Integrated Passive RX Front-End Ben W. Cook, Axel D. Berny, Alyosha Molnar, Steven Lanzisera,
More informationA Very Fast and Low- power Time- discrete Spread- spectrum Signal Generator
A. Cabrini, A. Carbonini, I. Galdi, F. Maloberti: "A ery Fast and Low-power Time-discrete Spread-spectrum Signal Generator"; IEEE Northeast Workshop on Circuits and Systems, NEWCAS 007, Montreal, 5-8 August
More informationPhase-Locked Loop Engineering Handbook for Integrated Circuits
Phase-Locked Loop Engineering Handbook for Integrated Circuits Stanley Goldman ARTECH H O U S E BOSTON LONDON artechhouse.com Preface Acknowledgments xiii xxi CHAPTER 1 Cetting Started with PLLs 1 1.1
More informationLM13600 Dual Operational Transconductance Amplifiers with Linearizing Diodes and Buffers
LM13600 Dual Operational Transconductance Amplifiers with Linearizing Diodes and Buffers General Description The LM13600 series consists of two current controlled transconductance amplifiers each with
More informationericssonz LBI-38640E MAINTENANCE MANUAL FOR VHF TRANSMITTER SYNTHESIZER MODULE 19D902780G1 DESCRIPTION
MAINTENANCE MANUAL FOR VHF TRANSMITTER SYNTHESIZER MODULE 19D902780G1 TABLE OF CONTENTS Page DESCRIPTION........................................... Front Cover GENERAL SPECIFICATIONS...................................
More informationBand- Pass ΣΔ Architectures with Single and Two Parallel Paths
H. Caracciolo, I. Galdi, E. Bonizzoni, F. Maloberti: "Band-Pass ΣΔ Architectures with Single and Two Parallel Paths"; IEEE Int. Symposium on Circuits and Systems, ISCAS 8, Seattle, 18-21 May 8, pp. 1656-1659.
More informationHigh Performance Digital Fractional-N Frequency Synthesizers
High Performance Digital Fractional-N Frequency Synthesizers Michael Perrott October 16, 2008 Copyright 2008 by Michael H. Perrott All rights reserved. Why Are Digital Phase-Locked Loops Interesting? PLLs
More informationSynchronous Mirror Delays. ECG 721 Memory Circuit Design Kevin Buck
Synchronous Mirror Delays ECG 721 Memory Circuit Design Kevin Buck 11/25/2015 Introduction A synchronous mirror delay (SMD) is a type of clock generation circuit Unlike DLLs and PLLs an SMD is an open
More informationDual-Frequency GNSS Front-End ASIC Design
Dual-Frequency GNSS Front-End ASIC Design Ed. 01 15/06/11 In the last years Acorde has been involved in the design of ASIC prototypes for several EU-funded projects in the fields of FM-UWB communications
More informationA Variable-Frequency Parallel I/O Interface with Adaptive Power Supply Regulation
WA 17.6: A Variable-Frequency Parallel I/O Interface with Adaptive Power Supply Regulation Gu-Yeon Wei, Jaeha Kim, Dean Liu, Stefanos Sidiropoulos 1, Mark Horowitz 1 Computer Systems Laboratory, Stanford
More informationCopyright 2007 Year IEEE. Reprinted from ISCAS 2007 International Symposium on Circuits and Systems, May This material is posted here
Copyright 2007 Year IEEE. Reprinted from ISCAS 2007 International Symposium on Circuits and Systems, 27-30 May 2007. This material is posted here with permission of the IEEE. Such permission of the IEEE
More informationA Clock Regenerator using Two 2 nd Order Sigma-Delta Modulators for Wide Range of Dividing Ratio
http://dx.doi.org/10.5573/jsts.2012.12.1.10 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.12, NO.1, MARCH, 2012 A Clock Regenerator using Two 2 nd Order Sigma-Delta Modulators for Wide Range of
More informationAn Efficient Design of CMOS based Differential LC and VCO for ISM and WI-FI Band of Applications
IJSTE - International Journal of Science Technology & Engineering Volume 2 Issue 10 April 2016 ISSN (online): 2349-784X An Efficient Design of CMOS based Differential LC and VCO for ISM and WI-FI Band
More informationAC LAB ECE-D ecestudy.wordpress.com
PART B EXPERIMENT NO: 1 AIM: PULSE AMPLITUDE MODULATION (PAM) & DEMODULATION DATE: To study Pulse Amplitude modulation and demodulation process with relevant waveforms. APPARATUS: 1. Pulse amplitude modulation
More informationA CMOS Frequency Synthesizer with an Injection-Locked Frequency Divider for a 5 GHz Wireless LAN Receiver. Hamid Rategh
A CMOS Frequency Synthesizer with an Injection-Locked Frequency Divider for a 5 GHz Wireless LAN Receiver Hamid Rategh Center for Integrated Systems Stanford University OUTLINE Motivation Introduction
More informationUMAINE ECE Morse Code ROM and Transmitter at ISM Band Frequency
UMAINE ECE Morse Code ROM and Transmitter at ISM Band Frequency Jamie E. Reinhold December 15, 2011 Abstract The design, simulation and layout of a UMAINE ECE Morse code Read Only Memory and transmitter
More informationTHE serial advanced technology attachment (SATA) is becoming
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 54, NO. 11, NOVEMBER 2007 979 A Low-Jitter Spread Spectrum Clock Generator Using FDMP Ding-Shiuan Shen and Shen-Iuan Liu, Senior Member,
More informationA Dual-Step-Mixing ILFD using a Direct Injection Technique for High- Order Division Ratios in 60GHz Applications
A Dual-Step-Mixing ILFD using a Direct Injection Technique for High- Order Division Ratios in 60GHz Applications Teerachot Siriburanon, Wei Deng, Ahmed Musa, Kenichi Okada, and Akira Matsuzawa Tokyo Institute
More informationDesign and noise analysis of a fully-differential charge pump for phase-locked loops
Vol. 30, No. 10 Journal of Semiconductors October 2009 Design and noise analysis of a fully-differential charge pump for phase-locked loops Gong Zhichao( 宫志超 ) 1, Lu Lei( 卢磊 ) 1, Liao Youchun( 廖友春 ) 2,
More informationA Multiobjective Optimization based Fast and Robust Design Methodology for Low Power and Low Phase Noise Current Starved VCO Gaurav Sharma 1
IJSRD - International Journal for Scientific Research & Development Vol. 2, Issue 01, 2014 ISSN (online): 2321-0613 A Multiobjective Optimization based Fast and Robust Design Methodology for Low Power
More informationA Low Area, Switched-Resistor Loop Filter Technique for Fractional-N Synthesizers Applied to a MEMS-based Programmable Oscillator
A Low Area, Switched-Resistor Loop Filter Technique for Fractional-N Synthesizers Applied to a MEMS-based Programmable Oscillator ISSCC 00, Session 3. M.H. Perrott, S. Pamarti, E. Hoffman, F.S. Lee, S.
More informationA high speed and low power CMOS current comparator for photon counting systems
F. Borghetti, L. Farina, P. Malcovati, F. Maloberti: "A high speed and low power CMOS current comparator for photon counting systems"; Proc. of the 2004 Int. Symposium on Circuits and Systems, ISCAS 2004,
More informationHigh-Robust Relaxation Oscillator with Frequency Synthesis Feature for FM-UWB Transmitters
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.15, NO.2, APRIL, 2015 ISSN(Print) 1598-1657 http://dx.doi.org/10.5573/jsts.2015.15.2.202 ISSN(Online) 2233-4866 High-Robust Relaxation Oscillator with
More informationAN3: Application Note
: Introduction The PE3291 fractional-n PLL is well suited for use in low data rate (narrow channel spacing) applications below 1 GHz, such as paging, remote meter reading, inventory control and RFID. It
More informationDEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE MASSACHUSETTS INSTITUTE OF TECHNOLOGY CAMBRIDGE, MASSACHUSETTS 02139
DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE MASSACHUSETTS INSTITUTE OF TECHNOLOGY CAMBRIDGE, MASSACHUSETTS 019.101 Introductory Analog Electronics Laboratory Laboratory No. READING ASSIGNMENT
More informationIN radio-frequency wireless transceivers, frequency synthesizers
784 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 6, JUNE 1999 A 2-V, 1.8-GHz BJT Phase-Locked Loop Wei-Zen Chen and Jieh-Tsorng Wu, Member, IEEE Abstract This paper describes the design of a bipolar
More informationA Robust Oscillator for Embedded System without External Crystal
Appl. Math. Inf. Sci. 9, No. 1L, 73-80 (2015) 73 Applied Mathematics & Information Sciences An International Journal http://dx.doi.org/10.12785/amis/091l09 A Robust Oscillator for Embedded System without
More informationEnhancement of VCO linearity and phase noise by implementing frequency locked loop
Enhancement of VCO linearity and phase noise by implementing frequency locked loop Abstract This paper investigates the on-chip implementation of a frequency locked loop (FLL) over a VCO that decreases
More informationTHE TREND toward implementing systems with low
724 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 30, NO. 7, JULY 1995 Design of a 100-MHz 10-mW 3-V Sample-and-Hold Amplifier in Digital Bipolar Technology Behzad Razavi, Member, IEEE Abstract This paper
More informationA Self Tuning System for On- Die Terminators in Current Mode Off- Chip Signaling
E. Lopez- Delgadillo, J.A. Diaz- Mendez, M.A. Garcia- Andrade, M.E. Magana, F. Maloberti: "A Self Tuning System for On-Die Terminators in Current Mode Off-Chip Signaling"; 5nd IEEE ternational Midwest
More informationPackage and Pin Assignment SSOP-6 (0.64mm pitch) OSCIN OSCOUT TXEN 3 VSS 4 TXOUT 5 VSS 6 7 MODIN 8 HiMARK SW DO RES RESB VREFP VSS Symbol
Low Power ASK Transmitter IC HiMARK Technology, Inc. reserves the right to change the product described in this datasheet. All information contained in this datasheet is subject to change without prior
More informationPhase-locked loop PIN CONFIGURATIONS
NE/SE DESCRIPTION The NE/SE is a versatile, high guaranteed frequency phase-locked loop designed for operation up to 0MHz. As shown in the Block Diagram, the NE/SE consists of a VCO, limiter, phase comparator,
More informationNoise Analysis of Phase Locked Loops
Noise Analysis of Phase Locked Loops MUHAMMED A. IBRAHIM JALIL A. HAMADAMIN Electrical Engineering Department Engineering College Salahaddin University -Hawler ERBIL - IRAQ Abstract: - This paper analyzes
More informationProject #3 for Electronic Circuit II
Project #3 for Electronic Circuit II Prof. Woo-Young Choi TA: Tongsung Kim, Minkyu Kim June 1, 2015 - Deadline : 6:00 pm on June 22, 2015. Penalties for late hand-in. - Team Students are expected to form
More informationDesign of High Performance PLL using Process,Temperature Compensated VCO
Design of High Performance PLL using Process,Temperature Compensated O K.A.Jyotsna Asst.professor CVR College of Engineering Hyderabad D.Anitha Asst.professor GITAM University Hyderabad ABSTRACT In this
More informationA Novel High Efficient Six Stage Charge Pump
A Novel High Efficient Six Stage Charge Pump based PLL Ms. Monica.B.J.C (Student) Department of ECE (Applied Electronics), Dhanalakshmi Srinivasan college of Engineering, Coimbatore, India. Ms. Yamuna.J
More informationLow Phase Noise CMOS Ring Oscillator VCOs for Frequency Synthesis
Low Phase Noise CMOS Ring Oscillator VCOs for Frequency Synthesis July 27, 1998 Rafael J. Betancourt Zamora and Thomas H. Lee Stanford Microwave Integrated Circuits Laboratory jeihgfdcbabakl Paul G. Allen
More informationLM13700 Dual Operational Transconductance Amplifiers with Linearizing Diodes and Buffers
LM13700 Dual Operational Transconductance Amplifiers with Linearizing Diodes and Buffers General Description The LM13700 series consists of two current controlled transconductance amplifiers, each with
More informationWITH the growth of data communication in internet, high
136 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 55, NO. 2, FEBRUARY 2008 A 0.18-m CMOS 1.25-Gbps Automatic-Gain-Control Amplifier I.-Hsin Wang, Student Member, IEEE, and Shen-Iuan
More informationDesign of a low voltage,low drop-out (LDO) voltage cmos regulator
Design of a low,low drop-out (LDO) cmos regulator Chaithra T S Ashwini Abstract- In this paper a low, low drop-out (LDO) regulator design procedure is proposed and implemented using 0.25 micron CMOS process.
More informationDesigning Nano Scale CMOS Adaptive PLL to Deal, Process Variability and Leakage Current for Better Circuit Performance
International Journal of Innovative Research in Electronics and Communications (IJIREC) Volume 1, Issue 3, June 2014, PP 18-30 ISSN 2349-4042 (Print) & ISSN 2349-4050 (Online) www.arcjournals.org Designing
More information