A Self Tuning System for On- Die Terminators in Current Mode Off- Chip Signaling

Transcription

1 E. Lopez- Delgadillo, J.A. Diaz- Mendez, M.A. Garcia- Andrade, M.E. Magana, F. Maloberti: "A Self Tuning System for On-Die Terminators in Current Mode Off-Chip Signaling"; 5nd IEEE ternational Midwest Symposium on Circuits and Systems, MWSCAS 009, Cancun, - 5 August 009, pp xx IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.

2 A Self Tuning System for On-Die Terminators in Current Mode Off-Chip Signaling E. López-Delgadillo,J.A.Díaz-Méndez,M.A.García-Andrade,M.E.Magaña and F. Maloberti National stitute for Astrophysics, Optics and Electronics (AOE). Tonantzintla, Puebla, México. National Polytechnical stitute, SEPI Culhuacán. Culhuacán, DF, México. Universidad Autónoma de Baja California, Engineering Faculty. Mexicali Baja California, México. Oregon State University, School of Electrical Engineering and Computer Science. Corvallis, Oregon, USA. University of Pavia, Department of Electronics. Pavia, Italy Abstract A system for self tuning of on-die terminators in current mode off-chip signaling is presented. The proposed method is based on an algorithm that uses the sign of the impedance matching error and the sign of the coupling branch current to perform the self tuning operation. The circuit implementation of the system is described and computer simulations at the transistor level are presented for process, temperature and load impedance variations. I. TRODUCTION The evolution of integrated circuit technologies has allowed the development of more complex electronic systems. This is, mainly, due to the scaling trends into submicrometric dimensions of silicon based devices, which permits the integration of a large number of systems in a single chip. At the same time, the operating frequencies of such systems are higher and a large amount of information can be processed in a short period of time. On the other hand, while the core frequencies are increasing, higher data rates for off-chip interconnections become necessary. Unfortunately, at high rates the signal wave length is comparable with the physical length of the interconnections, because of this, parasitic and transmission line effects have to be taken into account. As a consequence, the transmitted signal integrity is degraded resulting in communication errors [1], []. It has been shown that current-mode signaling offers several advantages over voltage-mode at high data rates [3], but the use of termination resistors is necessary and due to the large number of input/output circuits, terminations have to be placed on-chip [4]. One of the most important transmission line effects that degrades signal integrity in these signaling schemes is reflection loss. It appears when the transmission line characteristic impedance is not perfectly matched to the line driver and receiver impedance. this case, signal reflections traveling trough the line are present in either, driver to receiver or receiver to driver, directions. Unfortunately, it is difficult to achieve perfect matching due to the large process variations in the fabrication of interconnect lines and the different traces between them [5]. Moreover, temperature variations and external effects are also present. As a consequence, impedance matching techniques must be developed in order to automatically adapt the impedance variations of the line. Conventional approaches for impedance matching are termination techniques, where either parallel, Thevenin, AC or series terminators are implemented at the driver and/or receiver side of the line []. The drawback for these methods is that they are implemented with fixed impedances and variations for characteristic impedance of the line are not considered. [6], [7], [8] and [9] impedance matching techniques are presented in which digitally controlled parallel arrays of transistors with different dimensions match the line impedance. Disadvantages of these techniques are that noise at the power supply line can be generated because of the simultaneous switching of impedance branches and that a large number of branches are used if high precision is needed [4]. Other types of impedance matching techniques are those in which the appropriate value of impedance is achieved by controlling analog variable resistors, [5] and [4], reducing noise and achieving high precision. An important issue in matching is the impedance reference for automatic adaptation. A commonly used technique is to implement a voltage divider composed of an off chip resistance in series with a replica of the terminator, the voltage is compared against an on chip reference, [4], [8] and [9]. The drawbacks are that interconnect impedance variations are not considered and the area of the PCB increases due to the off-chip resistance. [7] the use of an external resistor is avoided by using an internal current source that produces a voltage drop on the replica of the terminator. [5] the tuning scheme is implemented to directly use the line impedance to generate the voltage reference, avoiding the problems presented before. this paper we present a method for automatic impedance matching in current mode off chip signaling schemes, which uses a continuous calibration technique that matches for PT (Process, oltage and Temperature) and interconnect variations and no off chip reference resistors are needed. II. BASIC PRCIPLE The principle for the proposed impedance matching technique is shown in Fig. 1. The core of the scheme is the unipolar current mode driver, which sinks the current I S from its outputs depending on the logic state of its inputs and. The terminators Z g are variable impedances that can be analog programmed via CTRL to match the interconnect impedance Z 0. The voltage reference generator system is depicted in the dashed rectangle. It is in essence a replica of the main driver, the only difference is that it sinks a current I S from the impedance Z g when the input is at logic one. The voltages Out of the driver and REF of the reference generator are the inputs for the impedance calibration circuit. This circuit generates the control voltage CTRL for the programmable resistances which minimizes the mismatching with the line characteristic impedance. Analyzing Fig. 1 and ignoring package effects, the voltage at the output of the driver Out is given by equation (1). «ZgZ 0 Out = DD0 I S. (1) Z g + Z 0 After some mathematical manipulation, it is possible to express equation (1) in a more convenient form, i.e /09/$ IEEE 10

3 P Fig. 1. CTRL Zg CTRL Out Ig DDO OutB Zg I g Z OUT g REF DDO I g a c k a g e Impedance Calibration Z 0 Z 0 CTRL Termination scheme for impedance matching. (n) (n) CLK OUT REF Cmp Ref FFD1 D Q D Fig.. Q Latch1 O Latch O O O Multiplier I CH I- Filter I CH Signal Condit. Impedance calibration circuit implementation. CTRL CTRL Also, the reference voltage REF Out = DD0 I gz g. () is given by REF = DD0 Is Z g. (3) From equations () and (3), the impedance matching error e is defined in (4). «IS e = Out REF = Z g I g. (4) As stated before, the goal of the impedance calibration circuit is to find the correct value for CTRL, to achieve this, the technique performed in [10] is used, namely, Z t CTRL = β Sgn(e(u))Sgn(I g(u))du, (5) where β is constant and establishes the speed of adaptation of the system. The function Sgn(e(u)) is deduced from (4) by assuming Z g > 0 as shown in (6). This equation presents the same result as in [10] and means that the matching condition is achieved when the current I g of the matching impedance is the same as that in the interconnect line, in other words, Z g = Z 0. «««IS Sgn(e(u)) = Sgn Z g I IS g = Sgn I g. (6) From equation (5), the proposed implementation of the impedance calibration circuit is shown in Fig.. The function Sgn(e(u)) is achieved with the clocked comparator Cmp, the inputs for this stage are the reference and the output voltages. The Sgn(I g(u)) is directly estimated from the input data and with the flip flop FFD1, the input buffers are used to compensate the driver delay. It is important to note that due to the use of the comparator and the flip flop with a control clock, the data signals can work in higher data rate applications and allows us to have a low frequency impedance calibration circuit. order to have the information of the signs of the mismatch error and I g at the same time, Latch1 and Latch are implemented, it is mainly because of the settling time of the comparator that gives a different delay time depending on the voltage difference of its inputs. The next stage is the multiplication, which is performed by AND gates, this is because the driver is unipolar and Sgn(I g(u)) only represent a logic one or a zero. The subsequent stage of the circuit is the integrator which is composed of the charge pump and the I- filter. The first converts its digital inputs into current pulses, then those pulses are integrated and changed to voltage in the filter. Finally, the signal conditioning circuit provides adequate differential control voltage for the programmable terminators. III. CIRCUIT TECHNIQUES this section the circuit techniques for the implementation of the elements of Fig. and the programmable terminator are presented. Circuits are designed in a standard CMOS 0.35μm technology. A. On-die Programmable Terminator The implemented on die programmable terminator resistor is shown in Fig. 3. The basic cell of the circuit is composed of M1, M and R1. Transistors M1 and M are connected as a transmission gate, in order to improve linearity. The gate voltages CTRL and CTRL control the impedance of the circuit and have to be differential. R1 is realized with a parallel combination of poly resistors and its function is to keep a fixed impedance value if for some reason M1 and M leave the linear region. As can be seen in Fig. 3, the total impedance is composed of two basic cells connected in series so that the drain to source voltages of the transistors are reduced and as a consequence the linear range is increased. Fig. 3 the voltage to current characteristic of the programmable terminator is shown for several values of CTRL and CTRL. CTRL Ma M R1a R1 M1a M1 CTRL Fig. 3. Programmable terminator circuit. B. Clocked Comparator The clocked comparator is shown in Fig. 4, [11]. It is composed of tree stages. The first stage is the preamplifier, which consists of a differential pair Ma1 and Ma and its diode connected loads Ma3 and Ma4. the second stage (Mc1 10) the comparison is achieved. This stage works in two modes: tracking and latching. the tracking mode, the clock falls from high to low, turning off transistors Mc5 and Mc6. this mode, input transistors Mc1 and Mc4 convert input voltages into currents that charge nodes n1 and n to an 103

4 appropriate value. tracking mode, the transistors Mc8 and Mc10 are on and set the output nodes to DD. the latching mode, the clock is high, Mc5 and Mc6 are turned on, while Mc8 and Mc10 are turned off. this case, transistors Mc 3 and Mc8 9 latch and amplify the voltages in n1 and n to the rails. The last stage is the amplify and hold. this stage, the output voltages from the second stage are first amplified with inverters and then latched with a NOR latch in order to keep the correct logic output. in Ma3 BIAS Ma1 Ma Mbias Ma4 ref Mc7 Mc8 Mc9 Mc10 Mc5 Mc6 n1 n Mc1 Mc Mc3 Mc4 AMP & HOLD ctrl Fig. 6. pd nd Charge pump control. E. Charge Pump Filter the charge pump circuit of Fig. 5, if the output node voltage takes a value near DD or SS then the drain to source voltage of M3 or M5 is so small that it produces a mismatch between the currents of these transistors. order to reduce the effect of current mismatch, an OTA-based active integrator is implemented as shown in Fig. 7. Due to the high gain of the OTA, the input node of the filter nin is set to a voltage near DD. C1 Out OutD nin OUT Fig. 4. Clocked comparator. DD C. Flip Flop and Latches The goal of the flip flop is to sample the sign of the data to be transmitted. Since this has to be done at the same time as the comparator, they need to have the same clock signal. this case, a master-slave D flip flop is implemented with a cascade of two latches that are clocked in opposite phases [1]. These latches are also implemented as a pipe line for the outputs of the comparator and the flip flop. D. Charge Pump The schematic of the implemented charge pump is shown in Fig. 5, [13]. The main part of the circuit is the right branch composed by the transmission gates TG1 and TG, which are used to control the output current I OUT to the load. order to reduce the start up delay of the current sources, a dummy branch is implemented through TG3 and TG4, so that when a transmission gate in the main branch is closed, the current is redirected by the dummy branch to REF. Also, in Fig. 5, an example of control signals for the transmission gate is shown. They are shaped in such a way that current is always flowing through M3 and M5. Fig. 7. Charge pump filter. F. Signal Conditioning Circuit The last section of the impedance calibration system is the signal conditioning circuit. As shown in Fig. 8, this circuit consists of a unitary gain inverter amplifier that produces a complementary output signal. The unity gain is achieved by setting the correct values to the diffusion resistors R1 and R, the gray part of the circuit is used to cancel the offset generated by PT variations. Finally, the output voltage followers set the complementary signals CTRL and CTRL near a desired value. DD R1 R BIAS BIAS CTRL CTRL M1 M M3 Fig. 8. Impedance Calibration Circuit Implementation Pd Nd I REF M4 Fig. 5. REF Pu Pd TG4 TG3 Charge pump. Nu Pu Nd Pd Fig. 6, the circuits used to generate the control signals for the charge pump are shown. With the circuit in Fig. 6 the signals of Fig. 5 are synthesized. The circuit is based on a delay line and an OR gate, in order to get wider pulses and another delay line is used for delay compensation. Finally, the differential signal generator for the transmission gates is shown in Fig. 6, [13]. M5 TG TG1 Nu Nd I OUT I. SIMULATION RESULTS order to verify the performance of the impedance calibration circuit of Fig., the circuits are designed in a standard CMOS 0.35μm technology and simulated using Mentor Graphics tools. The test vehicle is the circuit of Fig. 1, but with different ideal resistive loads of 40Ω, 50Ω and 60Ω. The data inputs to the system and are generated with the pseudorandom sequence generator used in [14], with 1Gb/s data rate. The clock frequency for the impedance calibration circuit is established at 400MHz. Fig. 9 the output and the reference voltages are presented when the load impedance is 40Ω. The signals before adaptation are shown in Fig. 9. Fig. 9 the same signals are shown after adaptation. The normalized error as a function of time for the system with load impedance of 40Ω is shown in Fig. 10 and for a load impedance of 104

5 oltage () oltage () show the simulations results m 96m 100m 104m 108m 11m Fig. 9. Performance of the system Fig. 1. Normalized error for process variations.. CONCLUSIONS A method for self tuning of on-die terminators for current mode off-chip signaling based on a sign minimization algorithm has been presented. The performance of the system has been probed by means of transistor level simulations for load, temperature and process variations. The proposed system can work in a low frequency environment while the data rates are high. The proposed implementation is simple and no off chip reference impedance is needed and only needs a small number of circuit elements. Fig. 10. Normalized error for different load impedances. 60Ω the error is presented in Fig. 10. the last case, the system adapts faster because it starts from a smaller error. The normalized error behavior of the system for temperature variations is shown in Fig. 11. As can be seen, the performance is worst in Fig. 11 which corresponds to a temperature of 10 o C. Fig. 11 represents the normalized error of the system working at 40 o C. Fig Normalized error for temperature variations. The last simulations deal with worst case speed and power scenarios. The Mentor Graphics kit is used to perform this task. Only worst power and speed cases are presented because they result in poor performance compared with the others. Figs. 1 and 1 REFERENCES [1] S. Thierauf, High-Speed Circuit Board Signal tegrity. Artech House, c., 004. [] D. Brooks, Signal tegrity Issues and Printed Circuit Board Design. Prentice Hall PTR, 003. [3] F. Juan, CMOS Current-Mode Circuits for a Communications. Springer, 007. [4] Y. Fan and J. Smith, On-die termination resistors with analog impedance control for standard cmos technology, IEEE Journal of Solid-State Circuits, vol. 38, no., pp , Feb [5] N. Ramachandran, H. Dinc, and A. Karsilayan, A 3.3-v cmos adaptive analog video line driver with low distortion performance, IEEE Journal of Solid-State Circuits, vol. 38, no. 6, pp , 003. [6] A. DeHon, T. Knight, and T. Simon, Automatic impedance control, IEEE ternational Conference on Solid State Circuits, pp , Feb [7] K. Koo, J. Seo, and J. Kim, A new impedance control circuit for usb.0 transceiver, Proceedings of 7th European Solid State Circuits Conference, pp , Sept [8] K. Koo et al., A versatile i/o with robust impedance calibration for various memory interfaces, IEEE ternational Symposium on Circuits and Systems, pp , May 006. [9] H. Muljono et al., A 400-mt/s 6.4-gb/s multiprocessor bus interface, IEEE Journal of Solid-State Circuits, vol. 38, no. 11, pp , Nov [10] E. Lopez-Delgadillo, M. A. Garcia-Andrade, J. Díaz-Méndez, and F. Maloberti, Automatic impedance control for chip-to-chip interconnections, IEEE ternational Conference on Electronics, Circuits, and Systems, pp , 008. [11] D. Johns and K. Martin, Analog tegrated Circuit Design. John Wiley and Sons, c., [1] K. Martin, Digital tegrated Circuit Design. Oxford University Press, 000. [13] B. Muer, CMOS Fractional-N Synthesizers. Kluwer Academic Publishers, 003. [14] X. Lin and J. Liu, A digital power spectrum estimation method for the adaptation of high-speed equalizers, IEEE Transactions on Circuits, and Systems-I: Regular Papers, vol. 51, no. 1, pp , Dec