An 8- bit current mode ripple folding A/D converter

Transcription

1 H. Dinc, F. Maloberti: "An 8-bit current mode ripple folding A/D converter"; Proc. of the 2003 Int. Symposium on Circuits and Systems, ISCAS 2003, Bangkok, May 2003, Vol. 1, pp xx IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.

2 AN 8-BIT CURRENT MODE RIPPLE FOLDING A/D CONVERTER Huseyin Dine, Student Member, IEEE and Franco Maloberti*, Fellow IEEE School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA * Department of Electrical Engineering, University of Texas at Dallas, Richardson, TX ABSTRACT This paper discusses the design of a ripple-folding analog to digital (AID) converter in the current mode technique, which makes the design fully compatible with standard digital CMOS processes. The AID converter, which is designed in TSMC 0.35 Fm CMOS process, achieves 8 hits of resolution at a clock frequency of 100MHz. Simulated results show that the SFDR is better than 62 db and the DNL and INL are 0.4 LSB. The A/D converter operates from a symmetrical +/-1.65 V supply. he power dissipated by the analog circuitry is 1SOmW. 1. INTRODUCTION Perhaps. the most popular technique to design the analog circuitry, especially A/D converters, in a mixed mode IC is the switched capacitor technique. Although, switched capacitor technique enjoys such a popularity, with the process optimization biased towards digital design, the main blocks, such as high gain operational transconductance amplifiers (OTAs) and linear capacitors, that comprise the switched capacitor systems are becoming problematic when it is required to use modem CMOS processes [I]. 2. RIPPLE FOLDING 2.1 Conceptual Description Given any block MM which has the relation (I), between its inputs (X,, X? and outputs (Y,, Y3, can be used to implement a ripple through folding by subtracting or adding binary weighted reference quantity to the proper outputs. Figure 1 depicts the block diagram of such a folding structure, corresponding signal quantities labeled on the diagram and the hits generated by the AID converter in parts a, b and c respectively. The previously designed ripple-folding topology [61 has inherent architectural limitations to the maximum achievable conversiun resolution. On the other hand 171 avoids employing ripple To avoid the problems that the switched capacitor technique suffers, an alternative analog sampled data processing technique can he used the switched current (Sl) technique. This technique does not require linear, poly-poly, capacitors and high gain amplifiers. which makes the SI approach fully compatible with standard CMOS processes. Due to this compatibility, the approach has attracted a significant attention and there are several published books on SI technique [2,3,4]. Furthermore, nowadays it is common to see complete analog processing systems designed in SI approach. Most recently, design of an analog Viterhi decoder using SI technique has been reported [SI. This paper discusses the design of a ripple-folding AID converter utilizing the SI technique. The specific architecture used and simulation results show that it is possible to attain 8-hit at a clock frequency of 100 MHz. The organization of the paper is as follows; section II presents the ripple-folding technique and describes the proposed current mode solution. Section 111 discusses the circuit implementation. Finally, section IV provides the simulation results and section V draws some conclusions. Figure 1. a) Conceptual ripple-folding AID converter. b) Corresponding signal quantities labeled in part a. c) The Gray coded bits generated by the cascaded blocks (c) /031% IEEE 1-981

3 ~ T T Figure 2. The SI realization of the ripple folding technique. folding to obtain each hit. Instead a flash A/D converter resolves the 3 LSBs, mainly. to increase speed, reduce power and area. Furthermore [6] is designed in a SO1 process and [7] utilizes only bipolar transistors in a BiCMOS process. The SI approach followed in this architecture overcomes the inherent limitation in [6] and makes the design fully compatible with standard CMOS processes. However the system is limited by the accuracy of the sub-blocks comprising the StNCtUIe. vi- Yli 2.2 Current Mode Implementation The SI realization of the idea presented in figure I is given in tigure 2. The operation of the circuit is as follows: A front-end track and hold (T&H) amplifier samples the differential analog signal, which is then fed to a voltage to current (V/I) convener. The differential current supplied by the V/I convener is then compared to detect the maximum of the two. While the maximum one is steered to a determined output, the minimum is conveyed to the other output. This operation mainly performs full-wave rectification, realizing the functionality mentioned in (I). Once the maximum and minimum of the two are detected, the currents are level shifted by reference currents which scale in a binary fashion through the cascade stages. The resultant level shifted currents are then sampled and held by a differential current memory. One important feature to mention is that, as the signal propagates downstream, the amplitude scales by 0.5 after each stage, decreasing the dynamic range. However, the accuracy required from the stages also scale by the same factor. Therefore, the required absolute accuracy remains constant. I i Trln.lcr 1 Figure 3. Timing Diagram. Track Latch i The circuit operates with three-phase non-overlapping clocks of equal duty-cycle, figure 3. They are used to sample the input current, compare the sampled current and transfer the sampled current to the next ripple-folding stage according to the connection established by the four switches. Observe that the level shifts. provided by the currents can also he done after the current memory cells. However with such an implementation the current memory is forced to memorize a V2t M - Y Y larger current, which possibly increases the power consumption and degrades the settling performance due to the increased modulation index. Besides the comparator inputs experience different parasitic capacitances due to the inherent difference in the way the positive and negative level shifting currents are generated. 3. CIRCUIT DESIGN 3.1 The Front-End Track and Hold Circuit The front-end T&H circuit is the basic passive T&H circuit realized by same sized NMOS switches and PMOS capacitors, figure 4. C h L C h L 5 5 Figure 4. Passive track and hold. The linearity of the T&H circuit is about 10 bits, which IS sufficient for this application. Even though it doesn't cause harmonic distonion, to a first approximation, the gain error is compensated by a dummy switch configured as in ( The Voltage to Current Converter The conversion from the voltage domain to the current domain is accomplished by an OTA. The linearity of this conversion is vital since the overall performance depends on this conversion. 'he schematic of the OTA is provided in figure 5. The common mode control is accomplished by adjusting the currents I,-N. The main performance metrics of interest for the realization of the V/1 convener are the settling time and linearity. Closed loop architectures [9] can have better linearity, however the settling time and excess phase limits the overall conversion speed. As an alternative, the linearization is obtained by complementary differential pairs, whose sources are degenerated by a resistance of the same value; Rs. The curvature of the nonlinearity of the signal currents IocUp and IDKDown can be made to have the opposite sign; in such a case, non-linearity of one of the signal currents is partially compensated by the other resulting in a more linear output current

4 1. switches SI^ is partially compensated by the switches SS4 in the non-overlapping complementary phase. Simulation results show that this compensation is vital for the proper operation of the overall A/D converter. Without the compensation components, the linearity ofthe current memory cell is limited to about 48 db, which is not sufficient for this application. Besides, gain error that the current experiences during transition from sample mode to hold mode has to be limited to a proper value. Assume that each memory cell has an identical gain error of cq the current at the output ofthe last stage is given by: "ss V.. Figure 5. Fully differential complementav folded cascode OTA. 3.3 The Current Memory Cell To achieve a good settling performance, power consumption and to reduce the transconductance ratio errors, the fully differential telescopic cascode structure, depicted ~n figure 6 is used [2] (common mode feedback circuit is not shown). For an 8-bit AID converter, this equation reduces to: Where, I, = 2 I 1 - I,ef --I,e, -~ I,...+ Err) (3) 2 4 I I As a result, a must have less than 0.4% variation around unity to ensure differential non-linearity (DNL) figures less then 0.5 LSB. 3.4 The Current Comparator The comparator utilized in the circuit realization of the block given in figure 2, is a pseudo differential current comparator. The structure is mainly a modification of the solution in [IO]. To decrease the comparison time and limit the power dissipation several measures are taken. The complete schematic of the comparator is provided in figure 7. Main features of the designed comparator, which makes it feasible for this specific application, are as follows: First of all, the input voltage swing is small and nonlinearly depended on the input current. Thus, it gives the designer another degree of freedom to choose the maximum and minimum detectable current levels. Second, it has better immunity to transistor mismatch compared to dynamic latch based comparators [Ill. This immunity results in lower comparator offset which improves DNL. Figure 6. Fully differential current memory cell. v. The voltage sampling switches and the hold capacitors are organized in a similar manner as the front-end T&H circuitry. The necessity of the auxiliary switches and capacitor can he explained as follows: Even though the gain error caused by the charge injection from the voltage sampling switches S,,, to a first approximation, results in a linear variation in the held voltage, due to the non-linear relation between the gate to source voltage and the drain current of a MOS transistor, the memorized current is altered from its ideal value non-linearly. This nonlinearity degrades the spurious free dynamic range of the processed current unless some precautions to compensate the gain error in the held voltage are taken. The components in the dashed box serve this purpose; the charge injected by the 4. SIMULATION RESULTS According to the Spectre-S simulations the spurious free dynamic range of the converter is around 62 db with an input frequency of IMHz at a clock rate of IOOMHz. Figure 8 plots the specmm of the signal, which is generated from the digital word supplied by the AID with an ideal digital to analog converter. Furthermore figures 9 and 10 show the NL and the DNL of the converter, respectively. One important point to mention is that the simulated results do not include the error caused by the variations due to transistor mismatches. Transistor mismatches result in random variation in the reference currents and comparator offset. However during circuit design, the sizes of the critical transistors are selected to he large enough to have the required current reference matching and Comparator offset

5 Figure 7. Complete schematic of the current comparator CONCLUSION Design of an Wit current mode ripple folding AID converter in TSMC 0.35 pm CMOS process is discussed. The current mode approach makes the design fully compatible with digital CMOS processes. Several measures are taken to improve the performance of the sub-blocks, such as the V/I converter and current comparator, comprising the system. The AID converter achieves 62 db SFDR with an input signal of MHz at a clocking rate of IOOMHz. The INL and DNL figures are around 0.4 LSB. The converter operates from a symmetrical +/-1.65 V supply. me power consumed by the analog circuitry is around I 5OmW. s 81.II.me -SI.+ea ~ S d -me 6. REFERENCES [I] Moon, U. Temes, G. Bidari, E. Kcskin, M. Wu, L. Steensgaard, J. Maloberti. F. "Switched-capacitor circuit techniques in submicron low-voltage CMOS" VLSl n,id CAD, ICVC ' Pageis); [2] C. Toumazou, 1.B.Hughes & N.C. Battersby, "Switched- Currents an Analogue Technique for Digital Technology". Perer Peregrinus Lrd, [3] Bengt E. Johnson, "Switched-Current Signal Processing and AID conversion Circuits". Kluwer Academic Publishers, [4] N. Tan, "Switched-Current Design and Implementation of Oversampling AID Converters." Kluwer Academic Publishers, [SI Andreas Demosthenaus &John Taylor. "A 100-Mb/s 2.8-V CMOS Current-Mode Analog Viterbi Decoder, IEEE JSSC, 37, July 2002 Page: [6] Carl Moreland et al. "A Msamplds Subranging ADC', IEEE JSSC, 35, Dec 2000, pp [71 Moreland, C.W. "An 8b 150 MSamplels serial ADC" Solid-State Circuits Conference, Digest of Technical Papers. 41st ISSCC, 1995 IEEE Inrrmuiionul, 1995 Pagefs): [SI A. Boni, A. Pierazzi, and C. Morandi, '' A 10-b 185-MSk Track-and-Hold in 0.35-pm CMOS". IEEE JSSC, 36, Feb Page: [9] Franco Maloberli "Analog Design for CMOS VLSl Systems" Kluwer Academic Publishers, [IO] H. Traff, " Novel Approach to High Speed CMOS Current Comparators" Electronic Letters, 28, No:3, Jan [l I] B. Razavi, B. Wooley, "Design Techniques for High-speed. High-Resolution Comparators". IEEE JSSC. 27, Dec Page: m..o.li.l N"*l.i"..nC Figure 10. DNL