Low-Voltage Low-Power Switched-Current Circuits and Systems

Transcription

1 Low-Voltage Low-Power Switched-Current Circuits and Systems Nianxiong Tan and Sven Eriksson Dept. of Electrical Engineering Linköping University S Linköping, Sweden Abstract This paper presents low-voltage lowpower switched-current circuits and systems. Novel class AB configuration and common-mode feedforward are the essence. A delay line, oversampling A/D converter, and chopper-stabilized oversampling A/D converter were designed and implemented. Measurement results are presented as well. T P1 i -i T G1 T C1 T P2 ø 1 T G2 ø 1 TC2 M P1 M P2 ø 2 i o -i o I. INTRODUCTION The switched-current (SI) technique is a relatively new current-mode sampled-data signal processing technique that fully exploits digital CMOS process [1]. In SI circuits, signals are represented by current samples and linear capacitors or operational amplifiers are not needed. SI circuits as current-mode circuits are fully compatible with standard digital CMOS technology and thus a very good candidate for mixedmode VLSI systems on standard digital technology. This accounts for the increasing interest in the SI technique for filtering and data conversion applications [1-15]. As the power supply voltage for digital circuits keeps decreasing to save power, designing low-voltage low-power analog circuits in CMOS process significantly increases the performance/price ratio of mixed-mode VLSI systems. Therefore, low-voltage lowpower SI circuits and systems are of great importance. In this paper we will present low-voltage low-power SI circuits and systems. Following this Introduction, we will present the novel class-ab memory cell in Section II and the principle of common-mode feedforward (CMFF) in Section III. Section IV will present oversampling A/D converters with and without system level chopper stabilization. The test chip and experimental results will be presented in Section V. Finally, a brief conclusion will be given. II. NOVEL CLASS-AB SI MEMORY CELL Saving power is crucial in portable electronics systems. Class AB circuits offer the potential to realize power efficient SI filters and data converters. To have high performance, fully differential structures are highly preferred [1, 2]. In Fig. 1 we show the proposed fully differential class-ab SI memory cell. T N1 TN2 M N1 M N2 Fig. 1. Novel class AB memory cell. The input/output conductance ratio in SI circuits introduces transmission error [1]. Unlike the reported class AB memory cells that used circuit techniques to reduce output conductance [16, 17], this new class AB memory cell uses grounded gate amplifiers (GGAs) to increase the input conductance [4, 10, 11]. Increasing the input conductance is usually preferable as SI memory cells have a single input and often multiple outputs. The memory cell comprises two pairs of memory transistors and two GGAs. The memory transistor pair consist of transistors MN and MP, and the GGA consists of the grounded-gate transistor TG, current biasing transistor TP and cascoded current bias transistors TC and TN. The class AB memory cell bears some resemblance of the class A memory cells in [2, 8, 12], where the p-type memory transistor was used as a current biasing transistor. The class AB configuration as shown in Fig. 1 allows more power efficient realization of SI circuits, because the input current can be larger than the quiescent current in the memory transistor that can be designed to be small. Linearized small-signal analysis reveals that the input conductance is increased by the voltage gain of the ground-gate transistor TG. This provides a 'virtual ground' at the input and thus the transmission error due to the input/output conductance ratio is significantly reduced [2]. The class AB configuration itself reduces the charge injection error if we use an n-type transistor as the switch for the n-type memory transistor and a p- type transistor as the switch for the p-type memory transistor [16]. And the fully differential structure reduces the charge injection error as well [2]. The settling behavior is similar to the class A memory cells [2, 8, 12].

2 To ensure proper operation, every transistor should be in its saturation region. Therefore, the minimum power supply voltage is given by ( V gs V T ) P ( V gs V T ) G ( V gs V T ) C (1) ( V gs V T ) N ( 1m i 1) ( V gs V T ) and ( V T ) MP ( V T ) MN ( 1 m i ) ( V gs V T ) (2) where V gs V T ( ) P,( V gs V T ) G,( V gs V T ) C,( V gs V T ) N, and ( V gs V T ) are the saturation voltages of transistors TP, T G, TC, TN, and MN (or MP ), ( V T ) MP and V T respectively, ( ) MN are the threshold voltages of memory transistors MP and MN, and mi is the signal modulation index. From Eqs. (1) and (2) it is seen that the use of lowpower supply voltage, say 3.3 V, is possible, given the threshold voltages around 1V, even with large input currents. III. COMMON-MODE FEEDFORWARD Not addressed in the above discussion is the control of common-mode components. Common-mode feedback (CMFB) was used to control the common-mode components in [1, 2, 8, 12]. The traditional CMFB has following drawbacks while processing the commonmode components: 1) nonlinearity due to the use of inherent voltage-to-current and current-to-voltage conversions; and 2) speed limitation due to the use of feedback loop. Also noted is the limitation of the reduction in power supply voltage due to the larger than necessary drain voltage for the common-mode sense transistor [2], though level shifting can circumvent it [8, 12]. To eliminate all the drawbacks, we propose a general common-mode feedforward (CMFF) technique [4, 10, 11]. The essence is that we process the commonmode components in the true current-mode domain. In current-mode circuits, it is very easy to duplicate a current by a current mirror (this is also how currentmode circuits generate outputs). If we first duplicate and halve the fully differential outputs from a currentmode circuit block and summate them, we get the common-mode component current. Then, we subtract the common-mode current from the fully differential outputs. This is best illustrated in Fig. 2. (a) a model of a general current-mode circuit block during its output phase. I is the biasing current, Id and Id- are the differential output currents. Transistors Tn0 and Tn1 are matched. (b) a way of generating the common-mode current. Transistors Tn2 and Tn3 have the half size of transistors Tn0 and Tn1. Transistors Tp0, Tp1, and Tp2 have the same size, and J is the biasing current. Therefore, we get I cm = 1 ( 2 I I d d ), it is the common-mode component. (c) feeding to the following circuit block by wiring corresponding outputs together. The input currents to the following circuits are Id - Icm and Id- - Icm, rather than Id and Id-. Therefore, no common-mode component propagates to the following circuits. 1 2 T n0 3 5 I I 3 I 4 d I d- (a) T n1 T p T n2 T n3 I o I o- 4 6 (b) T p1 6 -I cm J Tp2 -I cm (c) Fig. 2. Illustration of the CMFF. The penalty of using CMFF is only the use of current mirrors, eliminating the drawbacks of using CMFB. And the CMFF technique can be applied to any current-mode circuits [4, 10, 11, 13-15]. IV. OVERSAMPLING A/D CONVERTERS Oversampling A/D converters are known to deliver high performance from relatively inaccurate analog components [18]. The SI technique makes it possible to realize analog circuits in a standard CMOS process [1]. Therefore, oversampling SI A/D converters are the best choice to realize real-time signal processing systems, fully utilizing inexpensive CMOS process [4, 10]. The interests in SI design and implementation of oversampling A/D converters are steadily increasing [4-15], especially with reduced power supply voltages [4, 8-15]. In Fig. 3, we show the second-order delta-sigma modulators. In Fig. 3 (a) is the SI modulator documented the optimum performance [4, 9, 10, 12] and in Fig. 3 (b) is the chopper-stabilized SI modulator [4, 10, 13]. The chopper stabilized modulator is known J

3 to be immune from the influence of low-frequency noise at the modulator input [19]. There is delay in both integrators of the SI modulator of Fig. 3 (a) to decouple settling chain and scaling is performed to have optimum signal swing. There is also delay in both differentiators of the chopper-stabilized SI modulator of Fig. 3 (b) to decouple settling chain between successive stages and scaling is performed to have optimum signal swing. This makes the chopper-stabilized structure for SI realization different from the one reported for SC realization [19]. x(t) z z 1 z 1 1 z 1 y(kt) delay line together with other test circuits is at the upper most, the SI modulator is in the middle, and the chopper-stabilized SI modulator is at the bottom. We measured the power spectra of the delay line using a spectrum analyzer. When the clock frequency was 5 MHz and the input was a 8-µA 5-kHz sinusoidal, the total harmonic distortion (THD) was less than - 50 db. When we further increased the input, the THD increased due to the slewing in the GGAs that can be improved by using larger bias current in the GGAs [2]. chopper (a) z x(t) 1 z 1 z 1 1 z 1 chopper y(kt) (b) Fig. 3. SI - modulators. (a) non-chopperstabilized, and (b) chopper-stabilized. Linear analysis and system-level simulation reveal that both circuits of Fig. 3 realize the second-order - modulators. That is Y( z)= z 2 X( z) ( 1 z 1 ) 2 Ez where Y(z) is the digital output, X(z) is the analog input, and E(z) is the linearized quantization error of the current quantizer, all expressed in the z domain. For VLSI realization, a major concern is the signal swing. System simulation indicates that both modulators of Figs. 3 (a) and 3 (b) only require a signal range in both integrators and differentiators slightly larger than twice the full-scale input range. Therefore, both modulators of Fig. 3 are good candidates for VLSI implementation where signal range is restricted. V. EXPERIMENTAL RESULTS ( ) (3) Both modulators of Fig. 3 were implemented in a 0.8-µm standard digital CMOS process. The memory cell of Fig. 1 and CMFF technique were used to construct the integrators and differentiators. The current quantizers were the one proposed in [20] because of its low input impedance. The converters were current sources controlled by the output of the current quantizers. Clocking and resetting were also considered due to the difference of SC and SI circuits [4, 10, 12]. Also implemented on the test chip was a delay line realized by cascading two memory cells. In Fig. 4 we show the photograph of the implemented test chip. The Fig. 4. Photograph of the test chip. The thermal noise in SI circuits is the dominant factor limiting SNR [1]. The thermal noise in SI circuits can be approximated by considering the thermal noise generated by the memory transistors and the noise bandwidth determined by the transconductance and gate capacitance of the memory transistors [1]. The calculated rms noise current in this design was about 33 na. With an input current of 16 µa, the delay line would deliver a SNR about 54 db. The measured SNR was about 50 db with a signal bandwidth of 2.5 MHz. It was quite close to the expected value. In Fig. 5, we show a measured power spectrum of the SI - modulator by performing a 64K-point FFT using a blackman window. The clock frequency was 2.45 MHz and the input was a 2-kHz 3-µA (- 6 db) sinusoidal. Large harmonic distortion can be seen in the plot. It was due to the saturation of the modulator when the input was approaching the full scale [18] and the distortion introduced by the SI circuits. The measured THD was - 61 db and the SNR was 58 db with a signal bandwidth of 10 khz. In Fig. 6, we show the measured power spectra of the chopper-stabilized SI - modulator by performing a 64K-point FFT using a blackman window. The clock frequency was 2.45 MHz and the input was a 2-kHz 3- µa (- 6 db) sinusoidal. In Fig. 6 (a) is the output power spectrum before the output chopper multiplication. It is

4 clear that the signal has been moved to high frequencies. In Fig. 6 (b) is the output power spectrum after the output chopper multiplication. The signal is at the low frequencies as seen in the figure. The measured THD was - 62 db and the SNR was 58 db with a signal bandwidth of 10 khz. Notice that the noise at low frequencies was mainly due to the input interface circuit. Fig. 5. Measured power spectrum of the SI modulator of Fig. 3 (a). sinusoidal, the clock frequency was 2.45 MHz, and the oversampling ratio (OSR) was 128. The measured dynamic range for both modulator was about 10.5 bits. If the quantization error had been the main reason, the second-order - modulator would have achieved a dynamic range over 13 bits [18]. The circuit noise played a major role in limiting the dynamic range. The calculated rms noise current in the SI circuits was about 33 na, with a peak input current 6 µa, the modulators would achieve a dynamic range of 45 db. Oversampling by a factor of 128 increased the dynamic range by 21 db. Therefore, the modulators could achieve a dynamic range of 66 db. The measured value was about 63 db, quite close to the expected value. Therefore it is confirmed that the dynamic range was mainly limited by the noise in the SI circuits not by the quantization noise. Large thermal noise in SI circuits is due to the small storage capacitance. On the contrary, the thermal noise in SC circuits is usually much smaller due to the larger storage capacitance. SC circuits can usually deliver higher dynamic range than SI circuits. But SC circuits need double-poly CMOS process that make them not completely compatible with the digital (single-poly) CMOS process [1]. The SI technique is an inexpensive alternative to the SC technique for medium accuracy applications [4]. Signal/(Noise THD) (db) Clock frequency = 2.45 MHz Signal frequency = 2 KHz OSR = 128 non-chopper chopper Signal Level (db) Fig. 6. Measured power spectra of the chopperstabilized SI modulator of Fig. 3 (b). (a) before the output chopper multiplication, and (b) after the output chopper multiplication. In Fig. 7 we show the measured signal/(noise THD) versus the input current. The signal was a 2-kHz Fig. 7. Measured SNR vs. input current of the SI modulators of Fig. 3. The 0-dB level is 6 µa. It is also seen from Fig. 7 that the chopper stabilized SI modulator did not offer the performance superiority. The reasons were 1) the circuits were secondgeneration SI circuits and correlated double sampling reduced the low-frequency noise; and 2) the thermal noise determined the noise floor on which the chopper stabilization had no effect. Not being able to demonstrate the advantages of the chopper stabilization at system level, the chopper-stabilized SI modulator was an interesting alternative to realizing oversampling A/D converters and there was no penalty in complexity except for some chopper switches.

5 We summarize the performance of the delay line in Table 1 and the performances of the SI modulators in Table 2. Table 1. Performance of the delay line Process 0.8 µ single-poly CMOS Chip area 0.06 mm 2 Power supply voltage 3.3 V Power dissipation 0.7 mw Sampling frequency 5 MHz THD (5 khz, 8-µA) - 50 db SNR (bandwidth 2.5 MHz) 50 db Table 2. Performance of the SI Modulators chopper-stabilized non chopper-stab. Process single-poly single-poly CMOS CMOS Chip area 0.26 mm mm 2 supply 3.3 V 3.3 V voltage Power diss. 3.2 mw 3.2 mw Clock freq MHz 2.45 MHz OSR Signal band. 9.6 KHz 9.6 KHz 0-dB level 6 µa 6 µa Dynamic range 10.5 bits 10.5 bits VI. CONCLUSIONS We have presented low-voltage low-power SI circuits and systems. The essence was the use of the fully differential class-ab memory cell and the common-mode feedforward technique. The class-ab configuration made possible power efficient realization of SI systems. The CMFF technique obviated the use of CMFB circuits, making low-voltage operation possible. Also presented have been the measurement results of the delay line, oversampling A/D converter, and chopper-stabilized oversampling A/D converter. The delay line sampled at 5 MHz gave a 50-dB SNR and a - 50-dB THD. The two oversampling SI A/D converters gave a 10.5-bit dynamic range in a 10-kHz bandwidth. The limitation in the dynamic range was mainly due to the thermal noise in the SI circuits. The measured power dissipation of the SI A/D converters was 3.2 mw and the supply voltage was 3.3 V. It has thus been proved that the SI technique is an inexpensive alternative to the SC technique. REFERENCES [1] C. Toumazou, J. B. Hughes, and N. C. Battersby, Switched-currents: an analogue technique for digital technology. Peter Peregrinus Ltd., [2] J. B. Hughes and K. W. Moulding, Switched-current signal processing for video frequencies and beyond, IEEE J. Solid-State Circuits, vol. 28, pp , Mar [3] J. B. Hughes and K. W. Moulding, A switched-current double sampling bilinear Z-transform filter technique, in Proc. IEEE International Symposium on Circuits and Systems, Vol. 5, pp , May [4] N. Tan, Oversampling A/D Converters and Current-Mode Techniques. Ph. D. Dissertation, Linköping University, Sweden, [5] S. J. Daubert and D. Vallancourt, A transistor-only current-mode - modulator, IEEE J. Solid-State Circuits, vol. 27, pp , May [6] P. J. Crawley and G. W. Roberts, Switched-current sigma-delta modulation for A/D conversion, in Proc. IEEE International Symposium on Circuits and Systems, pp , May [7] C. Toumazou and G. Saether, Switched-current circuits and systems, in Proc. IEEE International Symposium on Circuits and Systems, Vol. Tutorials, pp , May [8] N. Tan and S. Eriksson, A fully differential switchedcurrent delta-sigma modulator using a single 3.3-V power-supply voltage, in Proc. IEEE International Symposium on Circuits and Systems, Vol. 5, pp , May [9] N. Tan, B. Jonsson, and S. Eriksson, 3.3-V 11-bit deltasigma modulator using first-generation SI circuits, Electron. Lett., pp , Oct [10] N. Tan, Switched-current delta-sigma A/D converters, invited paper, in Proc. 12th Norchip Seminar, Gothenburg, Sweden, pp. 8-15, Nov [11] N. Tan and S. Eriksson, Low-voltage fully differential class-ab SI circuits with common-mode feedforward, to appear in Electronics Letters. [12] N. Tan and S. Eriksson, A low-voltage switched-current delta-sigma modulator, under revision for IEEE J. Solid- State Circuits. [13] N. Tan and S. Eriksson, A chopper-stabilized switchedcurrent delta-sigma A/D converter, , Report LiTH-ISY-R-1647, Linköping University, Sweden. [14] N. Tan and S. Eriksson, Low-voltage SI oversampling A/D converters for video frequencies and beyond, , Report LiTH-ISY-R-1674, Linköping University, Sweden. [15] N. Tan and S. Eriksson, A 1.2-V 0.8-mW switchedcurrent oversampling A/D converter, , Report LiTH-ISY-R-1675, Linköping University, Sweden.

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