DeepSubmicron CMOS Design Methodology for HighPerformance Low Power AnalogtoDigital Converters


 Sybil Howard
 1 years ago
 Views:
Transcription
1 DeepSubmicron CMOS Design Methodology for HighPerformance Low Power AnalogtoDigital Converters Abstract In this paper, we present a complete design methodology for highperformance lowpower AnalogtoDigital Converters in deep submicron CMOS. This methodology is demonstrated on two ADC architectures, Flash and Folding&Interpolating(F&I). The designs were implemented in 0.18µm CMOS technology, achieving a high conversion rate of 2.6 GSamples/s for the Flash converter, and a 1 GSample/s rate for the Folding and Interpolating converter. In addition, the devices achieved a power consumption of 47 mw and 8mW respectively. Compared to previously published designs, this represents a 62.5% improvement in speed and 86% drop in power consumption for the Flash design and 3 times improved sensitivity (DNL) and 3.2 times reduction in power for the F&I design. 1. Introduction With the advancement of SystemonChip (SOC) architectures, the demand for high performance lowpower designs is ever increasing. To meet these demands, designers are utilizing deep submicron technologies in order to achieve the high speed, and low power design requirements. The demand of Systemon Chip (SOC) architectures is forcing designers to cope with lowvoltage and lowpower design specifications for A/D converters. In addition, the frequency requirements are increasing. Thus, the use of deep submicron technology in creating high speed lowpower data converters is increasing. The voltage limitations of these technologies are making it more difficult to produce accurate conversion devices due to a reduced operating range. In this paper, we are presenting two common techniques for realizing highspeed data converters in 0.18 µm CMOS technology. While these devices are typically well known, the design methodologies in these technologies are not. 2. ADC Development Methodology 2.1 Component Design Comparator In developing a highspeed data converter, the main requirement is a well designed comparator. These devices provide the core operation of the converter and are required to have as large of operating range as possible. Some designs, such as the Folding converter discussed here, eases some of the requirements of the converter. However, for the Flash converter, also discussed, the comparator can be the bottleneck of the design for speed and power consumption. The comparator is the core component of A/D converters; it dictates the characteristics of the majority of the design including operating range and can possibly be the frequency limiting device in high speed designs. With a limited supply voltage, such as the ones used in deep submicron technologies, we have to consider the optimization of the available voltage range. Threshold voltages of the transistors in these technologies tend to consume 2/3rds of the operating range. To overcome this, we suggest the use of full swing differential gain stage for the comparator. While railtorail operation is not realistic to achieve for any highspeed converter, a much larger operating range can be realized using this stage. The negative effect of using this technique is that the input capacitance to the circuit effectively doubles. This implies that a large buffer amplifier may be needed to drive this circuit for SOC applications. The comparator consists of two differential pairs tied in parallel, a decision circuit, and a gain/buffer stage, and is depicted in Figure 1. In the first stage an NFET differential pair is tied to a PFET differential pair, and is biased so that this device has a larger operating range than either differential pair alone could produce (large swing design). Following the differential gain stage is the decision circuit.
2 Figure 1 Comparator Schematic The use of a decision circuit that has positive feedback is relatively simple to design and Baker et. al provides a standard technique for developing these devices for lowresolution applications [7]. While the decision circuit can be very fast, we followed it by an additional gain stage and a buffer. The gain stage is based upon a selfbiasing differential structure. A final buffer stage is implemented using a basic inverter. Sizing of the inverter depends upon the decoder design, and the methodology is typical of any standard digital circuit [7]. This comparator design is more complicated than typical designs, but is responsible for the high accuracy and speed of the converter. The large operating range created by the use of both a PFET and NFET differential pairs, compensates for the low voltage supply that deep submicron technologies require. While this is not necessarily the lowest power solution, we found that it provided a high degree of performance Folding Amplifiers The folding amplifiers are the main design consideration in this type of A/D converter. By increasing the folding factor, the number of comparators is reduced. Although, this initially seems inherently desirable, it also implies that the folding amplifiers must have a bandwidth proportional to the input frequency multiplied by the folding factor. In addition, using a 1.8 V supply limited our dynamic range. However, we were able to achieve a 1 V operating range (520mV 1.52 V). This is the commonmode range of our folding circuit. In this range, the folding amplifier behaves linearly. At the lower end, we were able to operate the folding circuit slightly above the threshold voltage of the current source transistors. At the higher end, we were limited by the voltage drop across the load resistors. This reduced the requirement of the comparator s operating range. Our folding amplifier design consisted of five identical differential pairs with the outputs crossconnected. In designing folding and interpolating A/D converters, the bias current is one of the most important issues to be dealt with. A high bias current is required in order to meet the specified bandwidth. The upper 3dB frequency is given by f 1/ ( 2*π * τ ) = (1) where τ = R * C. (2) L The total capacitance at the output of the folding circuit can be found by summing the load capacitance with the drainbase and gatedrain capacitances. The load resistance is given by R L = 1/ ( λ * I SS ) (3) where λ is the modulation effect. From these three equations, having a high bias current (I SS ) reduces the load resistance, which reduces the output time constant. This results in a higher 3dB frequency. Additionally, there must be an equal amount of bias current flowing in each differential pair [1]. Different bias current results in different gain in the folding amplifiers. This distorts the shape of folded signals and thus, changes the positions of their zerocrossings. Therefore, as can be seen in Figure 2 (See Note 1), we used a regulated cascode current source to provide the same amount of bias current.
3 Realizing that, if there are mismatch errors in the resistor loads, the position errors of the folded signals are further increased. This can be remedied by designing the differential pairs to have a small V GS close to the threshold voltage. When calculating this value, one first has to define the gatesource biasing voltage in terms of the excess gatesource voltage V as V GS = V + V TH. (4) In a standard cascode current source, the voltage seen at the gate in Figure 2 (See Note 4) is 2( V +V TH ). (5) If this voltage can be reduced to 2 (6) V +V TH then the voltage on the drain of gate in Figure 2 (See Note 5) becomes V GS = V (7) which is the desired value. We used large transistors in the differential pairs to avoid mismatch errors such as an offset. The value of the offset voltage is given by the following equation V OS = VTH1 + * I D1 * L1 / W1 VTH * I 2 * L2 / 2 W By increasing the size of the transistors (making them wider) in the differential pairs (See Note 2), we can reduce the offset voltage. Although there are five differential pairs, the fifth differential pair is used to eliminate the DC component from the output (See Note 3) Encoders Fat Tree encoders have excellent performance, over ROM encoding techniques in both speed and power [4]. Often this encoder can be faster than the Figure 2 Schematic of Folding Block 2 comparator and thus, low power techniques can be applied to the digital encoder logic to further reduce power consumption. There are a couple of techniques that can be used to reduce the power of this decoder to match the performance of the comparator, such as reducing the Vdd voltage and gate resizing. However, these techniques are often unnecessary as the encoder consumes only a small fraction of the power of the analog circuitry. In our Flash implementation, we were able to reduce the power consumed by 7% by reducing the operating voltage of the encoder to 1 V. At this voltage, the encoding circuit speed matched the Comparator operating speed. 2.2 Architecture Design Flash Converter Design Example The Flash converter is composed of a series of comparators connected in parallel biased to reference voltages that are created via a resistive ladder. A block diagram is depicted in Figure 3. On the left hand side of the figure is the typical resistive ladder that is used to fix the reference voltages for each of the comparators. The analog input is tied to each comparator input and is compared to the fixed reference voltage that is appropriate for each bit to be determined by the comparator. The output of each comparator is then latched using Dlatches on each clock cycle [5,6,10]. These latched outputs are passed into a Fat Tree encoding logic [4]. This logic takes the thermometer logic from the comparators and converts it into, a 6bit binary representation of the input signal. The encoding logic is based upon a Fat Tree encoder. This encoding methodology uses a NORNAND structure to generate the desired 6bit output [4]. The initial converter design consisted of a ROM logic encoder, which consisted of a Thermometer Decoder and then an ORgate tree structure that was used to generate the desired 6bit
4 representation. However, due to the lack of symmetry of the logic, this technique proved to be very slow. The maximum speed that the ORgate logic allowed the converter to run at was 1.67 GHz. In addition, the logic had asynchronous race conditions within its structure, which caused glitches on the output. In order to get around these glitches, we latched the output of the logic with a clock that was out of phase with the clock that was driving the Dlatch. We found that the Fat Tree encoder eliminated the asynchronous race conditions, and improved the speed of the converter to 2.6 GHz. Further simulations indicated that the decoder logic would have allowed the converter to run up to 5.5 GHz. Thus, it was determined that the comparator is the frequency limiting component in this design. Figure 4  Basic Block Diagram of a Folding and Interpolating ADC where in the fold the input voltage is and the course Flash ADC determines which fold the input is in. The number of comparators is reduced by the degree of folding [2]. For a 6bit implementation, the folding factor needs to be a multiple of two. As the folding factor is increased, each folding block must have a bandwidth of f input * folding factor. Therefore, increasing the folding factor limits the input signal bandwidth as well as deteriorates the linearity of the folded signals. It is for these reasons, that we were limited to a folding factor of four using the 0.18 micron process. Figure 3Flash Converter Block Diagram Folding and Interpolating It is well known that, Flash A/D converters offer extremely fast conversion rates at the expense of power consumption and large chip area. These disadvantages arise from the fact that the complexity of the Flash converter grows exponentially as resolution increases because the number of comparators increases by 2 n 1 (where n is the number of resolved bits). Most of the comparators are saturated, while only the ones near a given input voltage level are required to resolve a small difference. Folding and interpolating ADC s decrease the number of comparators to about 2 n/2 + 1 [8]. In Figure 4 is presented the basic block diagram of a folding and interpolating ADC. In our design, the fine Flash ADC resolves 4 bits by generating a triangular waveform, while the course Flash ADC determines if the output is above or below the midscale [3]. In other words, the fine Flash ADC locates Fig. 5a and 5b. The output characteristic of a Folding ADC using a saw tooth (a) and triangular waveform (b) respectively. Ideally, a sawtooth waveform would be used (see Figure 5a), however this tends to be difficult to implement. A triangular waveform is much more realistic to produce and that is what we have utilized here with folding amplifiers (see Figure 5b) [3]. There are 64 zerocrossings utilized in the folding/interpolating component (See Figure 6, and note the number of intersections along any horizontal line, particularly near 932mV). This comes from the 8 folding blocks * folding factor of 4 * interpolation factor of 2 = 64. For any input voltage within the specified range, only one differential pair is active, while all the others are saturated. The rounding of the folds is a result of the limited bandwidth of the
5 folding amplifiers. Each folder output is shifted by an approximately an LSB (17.12 mv). The final requirement in this design was to institute some delay in the course ADC, because these bits would be resolved much faster than the LSBs. Because the delay was so small, a simple implementation of a series of inverters was utilized. 3. Results Figure 6 Offset Folded Signals This allowed for a more robust design, because now our comparator only needs to detect the zerocrossings. Our final design included 19 comparators, 16 in the LSB encoder and 3 in the 2bit course Flash A/D converter. This design enables us to have a large operating range due to the reduced requirements on the comparator. The Flash reference levels are not at the extremes of the device, and the folding circuit only uses the comparator as a zero crossing detector. 3.1 Flash ADC The Flash converter that was designed operates at 2.6 GHz with the Fat Tree logic structure. Figure 8, depicts the output timing diagram of the converter with a ramp as the input signal. The clock was running at 2.6 GHz, and there are 20 samples per step of the output signal. As can be seen from inspection, the converter is fairly linear within its operating range. In fact, the INL for this converter was measured to be 0.1 LSB and the DNL was 0.2 LSB. Figure 7 Cyclic Code to Thermometer Code Conversion Thus, the required operating range of the comparator is less than the overall device. In both, the course and the fine Flash A/D converter, we used the fat tree implementation to encode the thermometer code [4]. However, in the fine encoder, cyclic thermometer code is produced. In order to go from cyclic thermometer code to thermometer code, we used the LSB of the Flash to toggle between the inverted and noninverted comparators output values (See Figure 7). Figure 8 Flash ADC Timing Diagram The Flash converter gains its speed from utilizing a simple architecture; however, this simplicity comes at a price. The architecture is highly repetitive, and a large number of comparators and latches are used. These items individually don t consume a large amount of power. However, in the numbers used to build a reasonable resolution converter their combined power consumption is at a significant amount. The converter consumed an average of 47 mw of power with a full swing sine wave input signal that was at the Nyquist frequency of the converter. The Fat Tree encoder s power consumption is higher than the ROM encoding architecture, but the performance is far superior. When the A/D converter was run at its maximum speed with the ROM encoder it consumed 30mW of power versus 43mW for that Fat Tree upgraded design (both were run at 1.67GHz). This performance of this converter is both lower in power and superior INL/DNL performance when compared to the work presented by Scholtens et al [10]. While Scholtens et al used extensive techniques to improve performance,
6 we focused on an improved comparator design, and utilized a more effective encoding circuit. This resulted in a simplified design that consumed less power and higher overall performance. Table III shows the overall performance versus the work done by [10] s performance for the Flash converter. Table III Performance Summary for Flash ADC Previous [10] Current Technology 0.18µ CMOS 0.18µ CMOS Max. Sampl. Rate 1.6 GSample 2.6 GSample Resolution 6 Bits 6 Bits Operating Range N/A mV INL 0.4 LSB 0.1 LSB DNL N/A 0.2 LSB Av. Power 328mW 47 mw Power Supply 1.95 Analog 2.35 Digital 1.8 V 3.2 Folding and Interpolating ADC The Folding and Interpolating converter appeared to have a significant amount of nonlinear behavior, which is due in part to the large operating range of this device. This nonlinearity can be observed in Figure 6 as the zerocrossings do not all occur at the same voltage. However, this nonlinearity was well within our 1 LSB constraint. Although this converter exhibited more nonlinearity than its flash counterpart, compared to previous implementations it performed far better with a reduction of 0.5 LSB as can be seen in Table IV below. This converter has a high degree of performance with over a 1 GSample/second conversion rate. Due to the intense analog nature of this device, it was difficult to achieve the gain and bandwidth necessary to make a viable device in this process, and this is directly reflected by a scarcity or recent publications in this area. Table IV summarizes the performance of this device against the most recent comparable device made by [2], and shows that this new device delivers excellent performance. This is directly reflected by the low power consumption of 8mW in conjunction with a high sampling rate. Table IV Performance Summary for F/I ADC Performance Metric Previous Achieved Technology 0.5µ BiCMOS 0.18µ CMOS Max. Sampl. Rate 400 MS/s 1 GS/s Resolution 6 Bits 6 Bits Operating Range N/A mV INL N/A 0.4 LSB DNL 0.9 LSB +0.3/0.2 LSB Av. Power 200mW 8mW Power Supply 3.2V 1.8 V 4. Conclusion A design methodology for highperformance lowpower A/D converters in deep submicron technology has been proposed. It was demonstrated on two ADC architectures. Clearly, one can conclude that the Flash converter is the fastest converter running at 2.6 GSamples/second, but at the expense of 47mW of power consumption. However, the folding converter though less accurate (higher INL and DNL), provides a 1 GSamples/second sampling rate at less than 1/5 th the power. Clearly the Folding device is more power efficient, and the Flash converter provides maximum performance. When both designs are compared to previously published works, we have achieved a significant improvement in speed, power and sensitivity for both type of architectures. We have achieved a 62.5% improvement in speed and 86% drop in power consumption and 4 times improved sensitivity (INL) for the Flash design and 3 times improved sensitivity (DNL) and 3.2 times reduction in power consumption and higher power efficiency for the F&I design. 5. References [1] T. Kim, J. Sung, S. Kim, W. Joo, S. You and S. Kim. A 10bit 40 MSamples/s Cascading Folding & Interpolating A/D Converter with Wide Range Error Correction, IEEE Circuits and Systems, [2] Michael P. Flynn and Ben Sheahan. A 400MSample/s, 6 b CMOS Folding and Interpolating ADC, IEEE Journal of SolidState Circuits, Vol. 33, NO. 12, pp , [3] Robert M. Senger, Paul M. Walsh, and Jerome Le Ny. A 150 Msamples/s Folding and Current Mode Interpolating ADC in 0.35µm CMOS. EECS Analog to Digital Integrated Circuits, 17, [4] D. Lee, J. Yoo, K. Choi, and J. Ghaznavi. Fat Tree Encoder Design For UltraHigh Speed Flash A/D Converters. IEEE Circuits and Systems, [5] Paul. G.A. Jespers. Integrated Converters D to A and A to D Architectures, Analysis, and Simulation. Oxford: New York, [6] Alfi Moscovici. High Speed A/D Converters Understanding Data Converters Through Spice. Kluwer Academic Publishers: Massachusetts, [7] R. Jacob Baker, Harry W. Li, and David E. Boyce. CMOS Circuit Design, Layout, and Simulation. IEEE Press: New York, [8] T. Kim, J. Sung, and S. Kim. A Low Power 10bit 40Msamples/s CMOS Folding and Interpolating ADC with a Novel Architecture. Korean Conference on Semiconductors, Jan [9] C. Lin and B. Liu. A New Successive Approximation Architecture for LowPower LowCost CMOS A/D Converter, IEEE Journal of SolidState Circuits, Vol. 38, NO. 1, pp.5462, [10] Peter C.S. Scholtens and Maarten Vertregt. A 6b 1.6 Gsample/s Flash ADC in 0.18µm CMOS Using Averaging Termination. IEEE Journal of SolidState Circuits, Vol. 37, No.12, pp , December 2002.
A Novel ROM Architecture for Reducing Bubble and Metastability Errors in High Speed Flash ADCs
1 A Novel ROM Architecture for Reducing Bubble and Metastability Errors in High Speed Flash ADCs Mustafijur Rahman, Member, IEEE, K. L. Baishnab, F. A. Talukdar, Member, IEEE Dept. of Electronics & Communication
More informationFig. 2. Schematic of the THA. M1 M2 M3 M4 Vbias Vdd. Fig. 1. Simple 3Bit Flash ADC. Table1. THA Design Values ( with 0.
A 2GSPS 4Bit Flash A/D Converter Using Multiple Track/Hold Amplifiers By Dr. Mahmoud Fawzy Wagdy, Professor And ChunShou (Charlie) Huang, MSEE Department of Electrical Engineering, California State
More informationTHE QUANTIZED DIFFERENTIAL COMPARATOR IN FLASH ANALOG TO DIGITAL CONVERTER DESIGN
THE QUANTIZED DIFFERENTIAL COMPARATOR IN FLASH ANALOG TO DIGITAL CONVERTER DESIGN Meghana Kulkarni 1, V. Sridhar 2, G.H.Kulkarni 3 1 Asst.Prof., E & C Dept, Gogte Institute of Technology, Bgm, Karnataka,
More informationDESIGN AND PERFORMANCE VERIFICATION OF CURRENT CONVEYOR BASED PIPELINE A/D CONVERTER USING 180 NM TECHNOLOGY
DESIGN AND PERFORMANCE VERIFICATION OF CURRENT CONVEYOR BASED PIPELINE A/D CONVERTER USING 180 NM TECHNOLOGY Neha Bakawale Departmentof Electronics & Instrumentation Engineering, Shri G. S. Institute of
More informationAnalogtoDigital i Converters
CSE 577 Spring 2011 AnalogtoDigital i Converters Jaehyun Lim, Kyusun Choi Department t of Computer Science and Engineering i The Pennsylvania State University ADC Glossary DNL (differential nonlinearity)
More informationA High Speed Encoder for a 5GS/s 5 Bit Flash ADC
A High Speed Encoder for a 5GS/s 5 Bit Flash ADC George Tom Varghese and K. K. Mahapatra Department of Electronics and Communication Engineering, National Institute of Technology, Rourkela, India Email:
More informationDAT175: Topics in Electronic System Design
DAT175: Topics in Electronic System Design Analog Readout Circuitry for Hearing Aid in STM90nm 21 February 2010 Remzi Yagiz Mungan v1.10 1. Introduction In this project, the aim is to design an adjustable
More informationChapter 5. Operational Amplifiers and Source Followers. 5.1 Operational Amplifier
Chapter 5 Operational Amplifiers and Source Followers 5.1 Operational Amplifier In single ended operation the output is measured with respect to a fixed potential, usually ground, whereas in doubleended
More informationDESIGN OF ULTRA HIGH SPEED FLASH ADC, LOW POWER FOLDING AND. INTERPOLATING ADC IN CMOS 90nm TECHNOLOGY
DESIGN OF ULTRA HIGH SPEED FLASH ADC, LOW POWER FOLDING AND INTERPOLATING ADC IN CMOS 90nm TECHNOLOGY A thesis submitted in partial fulfillment of the requirements for the degree of Master of Science in
More informationCmos Full Adder and Multiplexer Based Encoder for Low Resolution Flash Adc
IOSR Journal of Electronics and Communication Engineering (IOSRJECE) eissn: 22782834,p ISSN: 22788735.Volume 12, Issue 2, Ver. II (Mar.Apr. 2017), PP 2027 www.iosrjournals.org Cmos Full Adder and
More information10.1: A 4 GSample/s 8b ADC in 0.35um CMOS
10.1: A 4 GSample/s 8b ADC in 0.35um CMOS Ken Poulton, Robert Neff, Art Muto, Wei Liu*, Andy Burstein**, Mehrdad Heshami*** Agilent Technologies, Palo Alto, CA *Agilent Technologies, Colorado Springs,
More informationA 42 fj 8bit 1.0GS/s folding and interpolating ADC with 1 GHz signal bandwidth
LETTER IEICE Electronics Express, Vol.11, No.2, 1 9 A 42 fj 8bit 1.0GS/s folding and interpolating ADC with 1 GHz signal bandwidth Mingshuo Wang a), Fan Ye, Wei Li, and Junyan Ren b) State Key Laboratory
More informationHighSpeed Analog to Digital Converters. ELCT 1003:High Speed ADCs
HighSpeed Analog to Digital Converters Ann Kotkat Barbara Georgy Mahmoud Tantawi Ayman Sakr Heidi ElFeky Nourane Gamal 1 Outline Introduction. Process of ADC. ADC Specifications. Flash ADC. Pipelined
More informationA NEW APPROACH TO DESIGN LOW POWER CMOS FLASH A/D CONVERTER
A NEW APPROACH TO DESIGN LOW POWER CMOS FLASH A/D CONVERTER C Mohan¹ and T Ravisekhar 2 ¹M. Tech (VLSI) Student, Sree Vidyanikethan Engineering College (Autonomous), Tirupati, India 2 Assistant Professor,
More informationUniversity of Michigan, EECS413 Final project. A High Speed Operational Amplifier. 1. A High Speed Operational Amplifier
University of Michigan, EECS413 Final project. A High Speed Operational Amplifier. 1 A High Speed Operational Amplifier A. Halim ElSaadi, Mohammed ElTanani, University of Michigan Abstract This paper
More information4bit,6.5GHz Flash ADC for High Speed Application in 130nm
Australian Journal of Basic and Applied Sciences, 5(10): 99106, 2011 ISSN 19918178 4bit,6.5GHz Flash ADC for High Speed Application in 130nm 1 M.J. Taghizadeh.Marvast, 2 M.A. Mohd.Ali, 3 H. Sanusi Department
More informationIndex terms: Analog to digital converter, Flash ADC, Pseudo NMOS logic, Pseudo Dynamic CMOS logic multi threshold voltage CMOS inverters.
Low Power CMOS Flash ADC C Mohan, T Ravisekhar Abstract The present investigation proposes an efficient low power encoding scheme intended for a flash analog to digital converter. The designing of a thermometer
More informationChapter 2 Basics of DigitaltoAnalog Conversion
Chapter 2 Basics of DigitaltoAnalog Conversion This chapter discusses basic concepts of modern DigitaltoAnalog Converters (DACs). The basic generic DAC functionality and specifications are discussed,
More informationINTERNATIONAL JOURNAL OF ELECTRICAL ENGINEERING & TECHNOLOGY (IJEET)
INTERNATIONAL JOURNAL OF ELECTRICAL ENGINEERING & TECHNOLOGY (IJEET) International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 6545(Print), ISSN 0976 6545(Print) ISSN 0976 6553(Online)
More informationUMAINE ECE Morse Code ROM and Transmitter at ISM Band Frequency
UMAINE ECE Morse Code ROM and Transmitter at ISM Band Frequency Jamie E. Reinhold December 15, 2011 Abstract The design, simulation and layout of a UMAINE ECE Morse code Read Only Memory and transmitter
More informationAlgebraic Modeling of New Enhanced Linearity Threshold Comparator based Flash ADC
IOSR Journal of VLSI and Signal Processing (IOSRJVSP) Volume 4, Issue 6, Ver. II (Nov  Dec. 2014), PP 1119 eissn: 2319 4200, pissn No. : 2319 4197 Algebraic Modeling of New Enhanced Linearity Threshold
More informationVLSI Implementation of a Simple Spiking Neuron Model
VLSI Implementation of a Simple Spiking Neuron Model Abdullah H. Ozcan Vamshi Chatla ECE 6332 Fall 2009 University of Virginia aho3h@virginia.edu vkc5em@virginia.edu ABSTRACT In this paper, we design a
More informationInvestigation of Comparator Topologies and their Usage in a Technology Independent FlashADC Testbed
Investigation of Comparator Topologies and their Usage in a Technology Independent FlashADC Testbed Cand.Ing. Öner B. Ergin Prof. Dr.Ing. Klaus Solbach Department of Microwave and RFTechnology University
More informationDesign and Layout of Two Stage High Bandwidth Operational Amplifier
Design and Layout of Two Stage High Bandwidth Operational Amplifier Yasir Mahmood Qureshi Abstract This paper presents the design and layout of a two stage, high speed operational amplifiers using standard
More informationCMOS Operational Amplifier
The George Washington University Department of Electrical and Computer Engineering Course: ECE218 Instructor: Mona E. Zaghloul Students: Shunping Wang Yiping (Neil) Tsai Data: 05/14/07 Introduction In
More informationBootstrapped ring oscillator with feedforward inputs for ultralowvoltage application
This article has been accepted and published on JSTAGE in advance of copyediting. Content is final as presented. IEICE Electronics Express, Vol.* No.*,** Bootstrapped ring oscillator with feedforward
More informationA Compact 2.4V Powerefficient Railtorail Operational Amplifier. Strong inversion operation stops a proposed compact 3V powerefficient
A Compact 2.4V Powerefficient Railtorail Operational Amplifier Abstract Strong inversion operation stops a proposed compact 3V powerefficient railtorail OpAmp from a lower total supply voltage.
More informationAn Improved Bandgap Reference (BGR) Circuit with Constant Voltage and Current Outputs
International Journal of Research in Engineering and Innovation Vol1, Issue6 (2017), 6064 International Journal of Research in Engineering and Innovation (IJREI) journal home page: http://www.ijrei.com
More informationSCLK 4 CS 1. Maxim Integrated Products 1
19172; Rev ; 4/ Dual, 8Bit, VoltageOutput General Description The contains two 8bit, buffered, voltageoutput digitaltoanalog converters (DAC A and DAC B) in a small 8pin SOT23 package. Both DAC
More informationINTERNATIONAL JOURNAL OF ADVANCED RESEARCH IN ENGINEERING AND TECHNOLOGY (IJARET)
INTERNATIONAL JOURNAL OF ADVANCED RESEARCH IN ENGINEERING AND TECHNOLOGY (IJARET) International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN ISSN 09766480 (Print) ISSN 09766499
More informationA PSEUDOCLASSAB TELESCOPICCASCODE OPERATIONAL AMPLIFIER
A PSEUDOCLASSAB TELESCOPICCASCODE OPERATIONAL AMPLIFIER M. TaherzadehSani, R. Lotfi, and O. Shoaei ABSTRACT A novel classab architecture for singlestage operational amplifiers is presented. The structure
More informationActive Decap Design Considerations for Optimal Supply Noise Reduction
Active Decap Design Considerations for Optimal Supply Noise Reduction Xiongfei Meng and Resve Saleh Dept. of ECE, University of British Columbia, 356 Main Mall, Vancouver, BC, V6T Z4, Canada Email: {xmeng,
More informationTHE comparison is the basic operation in an analogtodigital
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 53, NO. 7, JULY 2006 541 Kickback Noise Reduction Techniques for CMOS Latched Comparators Pedro M. Figueiredo, Member, IEEE, and João
More informationCurrent Steering Digital Analog Converter with Partial Binary Tree Network (PBTN)
Indonesian Journal of Electrical Engineering and Computer Science Vol. 5, No. 3, March 2017, pp. 643 ~ 649 DOI: 10.11591/ijeecs.v5.i3.pp643649 643 Current Steering Digital Analog Converter with Partial
More informationDesign and Implementation of Low Power Dynamic Thermometer Encoder For Flash ADC
Design and Implementation of Low Power Dynamic Thermometer Encoder For Flash ADC Abstract: In the design of a low power Flash ADC, a major challenge lies in designing a high speed thermometer code to binary
More informationBasic Operational Amplifier Circuits
Basic Operational Amplifier Circuits Comparators A comparator is a specialized nonlinear opamp circuit that compares two input voltages and produces an output state that indicates which one is greater.
More informationSP 22.3: A 12mW Wide Dynamic Range CMOS FrontEnd for a Portable GPS Receiver
SP 22.3: A 12mW Wide Dynamic Range CMOS FrontEnd for a Portable GPS Receiver Arvin R. Shahani, Derek K. Shaeffer, Thomas H. Lee Stanford University, Stanford, CA At submicron channel lengths, CMOS is
More information10Bit 5MHz Pipeline A/D Converter. Kannan Sockalingam and Rick Thibodeau
10Bit 5MHz Pipeline A/D Converter Kannan Sockalingam and Rick Thibodeau July 30, 2002 Contents 1 Introduction 8 1.1 Project Overview........................... 8 1.2 Objective...............................
More informationDesign of HighSpeed OpAmps for Signal Processing
Design of HighSpeed OpAmps for Signal Processing R. Jacob (Jake) Baker, PhD, PE Professor and Chair Boise State University 1910 University Dr. Boise, ID 837252075 jbaker@ieee.org Abstract  As CMOS
More informationAtypical op amp consists of a differential input stage,
IEEE JOURNAL OF SOLIDSTATE CIRCUITS, VOL. 33, NO. 6, JUNE 1998 915 LowVoltage Class Buffers with Quiescent Current Control Fan You, S. H. K. Embabi, and Edgar SánchezSinencio Abstract This paper presents
More informationA 2.4 GHZ RECEIVER IN SILICONONSAPPHIRE MICHAEL PETERS. B.S., Kansas State University, 2009 A REPORT
A 2.4 GHZ RECEIVER IN SILICONONSAPPHIRE by MICHAEL PETERS B.S., Kansas State University, 2009 A REPORT submitted in partial fulfillment of the requirements for the degree MASTER OF SCIENCE Department
More informationSUCCESSIVE approximation register (SAR) analogtodigital
426 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 62, NO. 5, MAY 2015 A Novel Hybrid Radix/Radix2 SAR ADC With Fast Convergence and Low Hardware Complexity Manzur Rahman, Arindam
More informationRF transmitter with Cartesian feedback
UNIVERSITY OF MICHIGAN EECS 522 FINAL PROJECT: RF TRANSMITTER WITH CARTESIAN FEEDBACK 1 RF transmitter with Cartesian feedback Alexandra Holbel, FuPang Hsu, and Chunyang Zhai, University of Michigan Abstract
More informationAnalog I/O. ECE 153B Sensor & Peripheral Interface Design Winter 2016
Analog I/O ECE 153B Sensor & Peripheral Interface Design Introduction Anytime we need to monitor or control analog signals with a digital system, we require analogtodigital (ADC) and digitaltoanalog
More informationHigh Speed Communication Circuits and Systems Lecture 14 High Speed Frequency Dividers
High Speed Communication Circuits and Systems Lecture 14 High Speed Frequency Dividers Michael H. Perrott March 19, 2004 Copyright 2004 by Michael H. Perrott All rights reserved. 1 High Speed Frequency
More informationA Novel Design of Low Voltage,Wilson Current Mirror based Wideband Operational Transconductance Amplifier
A Novel Design of Low Voltage,Wilson Current Mirror based Wideband Operational Transconductance Amplifier Kehul A. Shah 1, N.M.Devashrayee 2 1(Associative Prof., Department of Electronics and Communication,
More information3Stage Transimpedance Amplifier
3Stage Transimpedance Amplifier ECE 3400  Dr. Maysam Ghovanloo Garren Boggs TEAM 11 Vasundhara Rawat December 11, 2015 Project Specifications and Design Approach Goal: Design a 3stage transimpedance
More informationTUTORIAL 283 INL/DNL Measurements for HighSpeed Analogto Digital Converters (ADCs)
Maxim > Design Support > Technical Documents > Tutorials > A/D and D/A Conversion/Sampling Circuits > APP 283 Maxim > Design Support > Technical Documents > Tutorials > HighSpeed Signal Processing > APP
More information10. Chapter: A/D and D/A converter principles
Punčochář, Mohylová: TELO, Chapter 10: A/D and D/A converter principles 1 10. Chapter: A/D and D/A converter principles Time of study: 6 hours Goals: the student should be able to define basic principles
More informationDesign & Analysis of Low Power Full Adder
1174 Design & Analysis of Low Power Full Adder Sana Fazal 1, Mohd Ahmer 2 1 Electronics & communication Engineering Integral University, Lucknow 2 Electronics & communication Engineering Integral University,
More informationComparative Study of Different Low Power Design Techniques for Reduction of Leakage Power in CMOS VLSI Circuits
Comparative Study of Different Low Power Design Techniques for Reduction of Leakage Power in CMOS VLSI Circuits P. S. Aswale M. E. VLSI & Embedded Systems Department of E & TC Engineering SITRC, Nashik,
More informationDesign of Continuous Time Multibit Sigma Delta ADC for Next Generation Wireless Applications
RESEARCH ARTICLE OPEN ACCESS Design of Continuous Time Multibit Sigma Delta ADC for Next Generation Wireless Applications Sharon Theresa George*, J. Mangaiyarkarasi** *(Department of Information and Communication
More informationA highefficiency switching amplifier employing multilevel pulse width modulation
INTERNATIONAL JOURNAL OF COMMUNICATIONS Volume 11, 017 A highefficiency switching amplifier employing multilevel pulse width modulation Jan Doutreloigne Abstract This paper describes a new multilevel
More informationAnalysis and Design of High Speed Low Power Comparator in ADC
Analysis and Design of High Speed Low Power Comparator in ADC 1 Abhishek Rai, 2 B Ananda Venkatesan 1 M.Tech Scholar, 2 Assistant professor Dept. of ECE, SRM University, Chennai 1 Abhishekfan1791@gmail.com,
More informationAn introduction to Depletionmode MOSFETs By Linden Harrison
An introduction to Depletionmode MOSFETs By Linden Harrison Since the midnineteen seventies the enhancementmode MOSFET has been the subject of almost continuous global research, development, and refinement
More informationIT has been extensively pointed out that with shrinking
IEEE TRANSACTIONS ON COMPUTERAIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 18, NO. 5, MAY 1999 557 A Modeling Technique for CMOS Gates Alexander Chatzigeorgiou, Student Member, IEEE, Spiridon
More informationA Compact Foldedcascode Operational Amplifier with ClassAB Output Stage
A Compact Foldedcascode Operational Amplifier with ClassAB Output Stage EEE 523 Advanced Analog Integrated Circuits Project Report Fuding Ge You are an engineer who is assigned the project to design
More informationLow Voltage SC Circuit Design with Low  V t MOSFETs
Low Voltage SC Circuit Design with Low  V t MOSFETs Seyfi S. azarjani and W. Martin Snelgrove Department of Electronics, Carleton University, Ottawa Canada K1S56 Tel: (613)7638473, Email: seyfi@doe.carleton.ca
More informationDesign of Low Noise 16bit CMOS Digitally Controlled Oscillator
Design of Low Noise 16bit CMOS Digitally Controlled Oscillator Nitin Kumar #1, Manoj Kumar *2 # Ganga Institute of Technology & Management 1 nitinkumarvlsi@gmail.com * Guru Jambheshwar University of Science
More informationDesign of a Low Power 5GHz CMOS Radio Frequency Low Noise Amplifier Rakshith Venkatesh
Design of a Low Power 5GHz CMOS Radio Frequency Low Noise Amplifier Rakshith Venkatesh Abstract A 5GHz low power consumption LNA has been designed here for the receiver front end using 90nm CMOS technology.
More informationHigh Efficiency Flash ADC Using High Speed Low Power Double Tail Comparator
High Efficiency Flash ADC Using High Speed Low Power Double Tail Sruthi James 1, Ancy Joy 2, Dr.K.T Mathew 3 PG Student [VLSI], Dept. of ECE, Viswajyothy College Of Engineering & Technology, Vazhakulam,Kerala,
More informationRadivoje Đurić, 2015, Analogna Integrisana Kola 1
OTAoutput buffer 1 According to the types of loads, the driving capability of the output stages differs. For switched capacitor circuits which have high impedance capacitive loads, class A output stage
More informationThe simplest DAC can be constructed using a number of resistors with binary weighted values. X[3:0] is the 4bit digital value to be converter to an
1 Although digital technology dominates modern electronic systems, the physical world remains mostly analogue in nature. The most important components that link the analogue world to digital systems are
More informationCopyright 2007 Year IEEE. Reprinted from ISCAS 2007 International Symposium on Circuits and Systems, May This material is posted here
Copyright 2007 Year IEEE. Reprinted from ISCAS 2007 International Symposium on Circuits and Systems, 2730 May 2007. This material is posted here with permission of the IEEE. Such permission of the IEEE
More informationDesign of Low Power High Speed Fully Dynamic CMOS Latched Comparator
International Journal of Engineering Research and Development eissn: 2278067X, pissn: 2278800X, www.ijerd.com Volume 10, Issue 4 (April 2014), PP.0106 Design of Low Power High Speed Fully Dynamic
More informationA 19bit columnparallel foldingintegration/cyclic cascaded ADC with a precharging technique for CMOS image sensors
LETTER IEICE Electronics Express, Vol.14, No.2, 1 12 A 19bit columnparallel foldingintegration/cyclic cascaded ADC with a precharging technique for CMOS image sensors Tongxi Wang a), MinWoong Seo
More informationCMOS Schmitt Trigger A Uniquely Versatile Design Component
CMOS Schmitt Trigger A Uniquely Versatile Design Component INTRODUCTION The Schmitt trigger has found many applications in numerous circuits, both analog and digital. The versatility of a TTL Schmitt is
More informationA low voltage railtorail operational amplifier with constant operation and improved process robustness
Graduate Theses and Dissertations Graduate College 2009 A low voltage railtorail operational amplifier with constant operation and improved process robustness Rien Lerone Beal Iowa State University Follow
More informationA 1 GS/s 6 bits TimeBased AnalogtoDigital Converter
A 1 GS/s 6 bits TimeBased AnalogtoDigital Converter By Ahmed Ali El Sayed Ali Ali El Hussien Ali Hassan Maged Ali Ahmed Ahmed Ghazal Mohammed Mostafa Mohammed Hassoubh Nabil Mohammed Nabil Gomaa Under
More informationAn energy efficient full adder cell for low voltage
An energy efficient full adder cell for low voltage Keivan Navi 1a), Mehrdad Maeen 2, and Omid Hashemipour 1 1 Faculty of Electrical and Computer Engineering of Shahid Beheshti University, GC, Tehran,
More informationDesign and Simulation of an Operational Amplifier with High Gain and Bandwidth for Switched Capacitor Filters
IOSR Journal of Electrical and Electronics Engineering (IOSRJEEE) eissn: 22781676,pISSN: 23203331, Volume 11, Issue 1 Ver. II (Jan. Feb. 2016), PP 4753 www.iosrjournals.org Design and Simulation
More informationDesign of a Sample and Hold Circuit using Rail to Rail Low Voltage Compact Operational Amplifier and bootstrap Switching
RESEARCH ARTICLE OPEN ACCESS Design of a Sample and Hold Circuit using Rail to Rail Low Voltage Compact Operational Amplifier and bootstrap Switching Annu Saini, Prity Yadav (M.Tech. Student, Department
More informationIJMIE Volume 2, Issue 3 ISSN:
IJMIE Volume 2, Issue 3 ISSN: 22490558 VLSI DESIGN OF LOW POWER HIGH SPEED DOMINO LOGIC Ms. Rakhi R. Agrawal* Dr. S. A. Ladhake** Abstract: Simple to implement, low cost designs in CMOS Domino logic are
More informationDESIGN, IMPLEMENTATION AND ANALYSIS OF FLASH ADC ARCHITECTURE WITH DIFFERENTIAL AMPLIFIER AS COMPARATOR USING CUSTOM DESIGN APPROACH
DESIGN, IMPLEMENTATION AND ANALYSIS OF FLASH ADC ARCHITECTURE WITH DIFFERENTIAL AMPLIFIER AS COMPARATOR USING CUSTOM DESIGN APPROACH 1 CHANNAKKA LAKKANNAVAR, 2 SHRIKANTH K. SHIRAKOL, 3 KALMESHWAR N. HOSUR
More informationChapter 12 Opertational Amplifier Circuits
1 Chapter 12 Opertational Amplifier Circuits Learning Objectives 1) The design and analysis of the two basic CMOS opamp architectures: the twostage circuit and the singlestage, folded cascode circuit.
More informationEFFICIENT LOW POWER DYNAMIC COMPARATOR FOR HIGH SPEED ADC s
EFFICIENT LOW POWER DYNAMIC COMPARATOR FOR HIGH SPEED ADC s B.Padmavathi, ME (VLSI Design), Anand Institute of Higher Technology, Chennai, India krishypadma@gmail.com Abstract In electronics, a comparator
More informationLOW SUPPLY VOLTAGE, LOW NOISE FULLY DIFFERENTIAL PROGRAMMABLE GAIN AMPLIFIERS
LOW SUPPLY VOLTAGE, LOW NOISE FULLY DIFFERENTIAL PROGRAMMABLE GAIN AMPLIFIERS A. Pleteršek, D. Strle, J. Trontelj Microelectronic Laboratory University of Ljubljana, Tržaška 25, 61000 Ljubljana, Slovenia
More informationDesign of Pipeline Analog to Digital Converter
Design of Pipeline Analog to Digital Converter Vivek Tripathi, Chandrajit Debnath, Rakesh Malik STMicroelectronics The pipeline analogtodigital converter (ADC) architecture is the most popular topology
More informationA LowPower SRAM Design Using QuietBitline Architecture
A LowPower SRAM Design Using uietbitline Architecture ShinPao Cheng ShiYu Huang Electrical Engineering Department National TsingHua University, Taiwan Abstract This paper presents a lowpower SRAM
More informationLecture 3 SwitchedCapacitor Circuits Trevor Caldwell
Advanced Analog Circuits Lecture 3 SwitchedCapacitor Circuits Trevor Caldwell trevor.caldwell@analog.com Lecture Plan Date Lecture (Wednesday 24pm) Reference Homework 20170111 1 MOD1 & MOD2 ST 2, 3,
More informationMultiplying DACs. Flexible Building Blocks.
Multiplying DACs Flexible Building Blocks Analog Devices has a comprehensive family of 8/10/12/14/16bit multiplying digitaltoanalog converters. As a result of manufacture on a CMOS submicron process,
More informationSubthreshold Leakage Current Reduction Using Variable Gate Oxide Thickness (VGOT) MOSFET
Microelectronics and Solid State Electronics 2013, 2(2): 2428 DOI: 10.5923/j.msse.20130202.02 Subthreshold Leakage Current Reduction Using Variable Gate Oxide Thickness (VGOT) MOSFET Keerti Kumar. K
More informationEECE2412 Final Exam. with Solutions
EECE2412 Final Exam with Solutions Prof. Charles A. DiMarzio Department of Electrical and Computer Engineering Northeastern University Fall Semester 2010 My file 11480/exams/final General Instructions:
More informationTechniques for High Speed and Low Power DigitaltoAnalog Converters
POLITECNICO DI MILANO Dipartimento di Elettronica e Informazione DOTTORATO DI RICERCA IN INGEGNERIA DELL INFORMAZIONE Techniques for High Speed and Low Power DigitaltoAnalog Converters Doctoral Dissertation
More information2. Single Stage OpAmps
/74 2. Single Stage OpAmps Francesc Serra Graells francesc.serra.graells@uab.cat Departament de Microelectrònica i Sistemes Electrònics Universitat Autònoma de Barcelona paco.serra@imbcnm.csic.es Integrated
More informationDue to the absence of internal nodes, inverterbased GmC filters [1,2] allow achieving bandwidths beyond what is possible
A ForwardBodyBias Tuned 450MHz GmC 3 rd Order LowPass Filter in 28nm UTBB FDSOI with >1dBVp IIP3 over a 0.7to1V Supply Joeri Lechevallier 1,2, Remko Struiksma 1, Hani Sherry 2, Andreia Cathelin
More informationINL PLOT REFIN DAC AMPLIFIER DAC REGISTER INPUT CONTROL LOGIC, REGISTERS AND LATCHES
ICm ictm IC MICROSYSTEMS FEATURES 12Bit 1.2v Low Power Single DAC With Serial Interface and Voltage Output DNL PLOT 12Bit 1.2v Single DAC in 8 Lead TSSOP Package UltraLow Power Consumption Guaranteed
More informationLow Power CMOS Digitally Controlled Oscillator Manoj Kumar #1, Sandeep K. Arya #2, Sujata Pandey* 3 and Timsi #4
Low CMOS Digitally Controlled Oscillator Manoj Kumar #1, Sandeep K. Arya #2, Sujata Pandey* 3 and Timsi #4 # Department of Electronics & Communication Engineering Guru Jambheshwar University of Science
More informationTuesday, March 1st, 9:15 11:00. Snorre Aunet Nanoelectronics group Department of Informatics University of Oslo.
Nyquist Analog to Digital it Converters Tuesday, March 1st, 9:15 11:00 Snorre Aunet (sa@ifi.uio.no) Nanoelectronics group Department of Informatics University of Oslo 3.1 Introduction 3.1.1 DAC applications
More informationAn Overview of Static Power Dissipation
An Overview of Static Power Dissipation Jayanth Srinivasan 1 Introduction Power consumption is an increasingly important issue in general purpose processors, particularly in the mobile computing segment.
More information9Bit, 30 MSPS ADC AD9049 REV. 0. Figure 1. Typical Connections FUNCTIONAL BLOCK DIAGRAM
a FEATURES Low Power: 00 mw OnChip T/H, Reference Single +5 V Power Supply Operation Selectable 5 V or V Logic I/O Wide Dynamic Performance APPLICATIONS Digital Communications Professional Video Medical
More informationLow Cost 10Bit Monolithic D/A Converter AD561
a FEATURES Complete Current Output Converter High Stability Buried Zener Reference Laser Trimmed to High Accuracy (1/4 LSB Max Error, AD561K, T) Trimmed Output Application Resistors for 0 V to +10 V, 5
More informationFeatures. Key Specifications. n Total unadjusted error. n No missing codes over temperature. Applications
ADC10061/ADC10062/ADC10064 10Bit 600 ns A/D Converter with Input Multiplexer and Sample/Hold General Description Using an innovative, patented multistep* conversion technique, the 10bit ADC10061, ADC10062,
More informationDesign of a High Speed Mixed Signal CMOS Mutliplying Circuit
Brigham Young University BYU ScholarsArchive All Theses and Dissertations 20040312 Design of a High Speed Mixed Signal CMOS Mutliplying Circuit David Ray Bartholomew Brigham Young University  Provo
More informationA Serial Link Transceiver Based on 8 GSa/s A/D and D/A Converters
A Serial Link Transceiver Based on 8 GSa/s A/D and D/A Converters in 0.25µm m CMOS William Ellersick 1,3, ChihKong Ken Yang 2 Vladimir Stojanovic 1, Siamak Modjtahedi 2, Mark A. Horowitz 1 1 Stanford
More informationANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS
ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS Fourth Edition PAUL R. GRAY University of California, Berkeley PAUL J. HURST University of California, Davis STEPHEN H. LEWIS University of California,
More informationComparator Design for Delta Sigma Modulator
International Conference on Emerging Trends in and Applied Sciences (ICETTAS 2015) Comparator Design for Delta Sigma Modulator Pinka Abraham PG Scholar Dept.of ECE College of Engineering Munnar Jayakrishnan
More informationIN targeting future batterypowered portable equipment and
1386 IEEE JOURNAL OF SOLIDSTATE CIRCUITS, VOL. 34, NO. 10, OCTOBER 1999 A 1V CMOS D/A Converter with MultiInput FloatingGate MOSFET Louis S. Y. Wong, Chee Y. Kwok, and Graham A. Rigby Abstract A lowvoltage
More informationChapter 13: Introduction to Switched Capacitor Circuits
Chapter 13: Introduction to Switched Capacitor Circuits 13.1 General Considerations 13.2 Sampling Switches 13.3 SwitchedCapacitor Amplifiers 13.4 SwitchedCapacitor Integrator 13.5 SwitchedCapacitor
More informationLow Noise, Matched Dual PNP Transistor MAT03
a FEATURES Dual Matched PNP Transistor Low Offset Voltage: 100 V Max Low Noise: 1 nv/ Hz @ 1 khz Max High Gain: 100 Min High Gain Bandwidth: 190 MHz Typ Tight Gain Matching: 3% Max Excellent Logarithmic
More information