ISSCC 2004 / SESSION 25 / HIGH-RESOLUTION NYQUIST ADCs / 25.3

Transcription

1 ISSCC 2004 / SESSION 25 / HIGH-RESOLUTION NYQUIST ADCs / A 96dB SFDR 50MS/s Digitally Enhanced CMOS Pipeline A/D Converter K. Nair, R. Harjani University of Minnesota, Minneapolis, MN Analog-to-digital (A/D) converters for "universal" base-stations have stringent spurious-free dynamic range (SFDR) and speed requirements. High speed pipelined data converters can be combined with digital resolution enhancement techniques as ideal candidates for this application. In our design, the linearity of the overall pipeline converter has been improved by increasing the linearity of the input sample-and-hold (S/H) and then digitally post-processing the raw output for improved performance. The gain, offset and nonlinearity of each of the individual blocks in the pipeline converter affect the linearity of the overall converter. Among them the non-linearity of the input S/H block cannot be corrected by post-processing as it is not possible to distinguish it from the input signal. For this reason we use circuit techniques including bottom plate sampling, bootstrapped switches and appropriate sizing of the switches, to reduce the impact of tracking and charge injection errors. The enhanced bootstrapped circuit shown in Fig improves on previous techniques [1] and increases the overdrive voltage of the input S/H transistor to be above V DD, so as to reduce its non-linearity. Channel charge injection related non-linearity is modeled by an analytical charge injection model [2], which is extended to model the structure shown in Fig There is a tradeoff between charge injection and tracking error on the size of the input-sampling transistor S 1. Our analytical model allows us to evaluate this tradeoff and select an optimal size for S 1. Detailed analysis of the non-linearity of the input S/H block has led to an improved S/H design with the degeneration capacitor, Cd. Cd compensates for the signal dependent resistance of S 1 when S 3 is being turned off, so as to make its charge injection signal independent. Simulations, suggest that the SFDR increases by 6dB using Cd for low supply voltages. In a pipeline A/D converter, non-idealities in the D/A sub-converter cannot be corrected by digital error correction. Subtractive dither [3] can reduce these non-idealities. Analog and digital calibration techniques can also be used to correct for the gain error in the D/A sub-converter. However, these techniques correct for either nonlinearity or gain error separately. The DFCA method [4] corrects for both non-linearity and gain error but increases the complexity in the analog domain and provides limited improvement to SFDR. The subtractive dither-continuous gain correction (SD-CGC) technique introduced in this design is an in-line digital technique that corrects for both nonlinearity and gain error in the D/A sub-converter. For the pipeline converter shown in Fig , this technique has been applied only to the first stage, as the overall ADC performance is most sensitive to non-ideal behavior in the first stage and the sensitivity decreases along the pipeline. Here the first stage, resolves 4 bits, the eight 1.5 bit (with digital error correction) stages provide 8 bits, and an external flash provides the final 3 bits. The D/A sub-converter is configured such that pseudorandom orthogonal codes randomly change the capacitors connected to the D/A [3]. The subtractive dither logic generates estimates of the error components in the first pipeline stage arising from the noise generated by the randomized D/A sub-converter bits. The estimated error is subtracted from the output sequence to give the non-linearity corrected output sequence. The CGC block with the help of two averagers calculates the gain error. This error is then subtracted from the digital error corrected output of the pipeline to give the final SD-CGC output. The SD-CGC architecture was validated via a design fabricated in the TSMC 0.25µm CMOS process. The chip includes the input S/H stage with bootstrapped switches, a 4-bit first stage followed by eight 1.5-bit stages, and a clock generator. The chip also includes the butterfly randomization logic needed for the first stage D/A sub-converter. The input to the first stage is between +/-0.5V centered at 0.8V. The digital subtractive dither, digital error correction and continuous gain correction blocks are programmed into a Xilinx series XC4000 FPGA using logic gates. Figure shows the measured two-tone (5 & 6MHz) power spectral density (PSD) of the converter running at 50MS/s. The top graph shows the PSD with only dither turned on, the 2nd graph shows the PSD with subtractive dither activated and the 3rd graph shows the PSD with SD-CGC activated. We note that the SNDR increases from 49dB to 74dB and that the SFDR increases from 62dB to 93dB in comparison to the raw dithered output. Figure shows the SNDR and SFDR for different clock rates. The same two-tone inputs at 5 & 6MHz are used for this experiment. We note that SFDR remains above 93dB till about 50MS/s then drops more rapidly at higher frequencies. We suspect this is due to finite settling errors. For comparison purposes we also include SFDR numbers for some previous work [4,5]. In Fig we show the SNDR and SFDR as a function of the input signal frequency. The sample rate is 50MS/s and a single tone signal is used for this experiment. We note that the SFDR is slightly higher than for a two-tone test as expected and that it remains relatively independent of input frequency. The SNDR remains constant around 74dB, which we believe is kt/c limited. We note that only SD-CGC increases both SNDR and SFDR sufficiently for our application. Figure summarizes the measurement performance for the SD-CDC design whose die photo is shown in Fig In this paper we have presented the design for a high SFDR pipelined A/D converter. Digital calibration techniques were combined with circuit level modifications to enhance SFDR. Measurement results from a 0.25µm TSMC fabricated chip shows an SNDR of 75dB and a SFDR of 96dB for an input frequency of 15MHz, running at a clock frequency of 50MS/s. This is over 40dB increase in SFDR compared to the non-calibrated output. The calibration technique is done digitally and does not increase the complexity of the analog chip. There is a short initial ramp-up (< 5sec) needed for the averagers in the pipeline to fill up, after which the output is continuous. References: [1] Hui Pan, M. Segami, et al., A 3.3 V, 12b, 50MSample/s A/D Converter in 0.6µm CMOS with over 80dB SFDR, ISSCC Dig. Tech. Papers, pp , Feb [2] Y. Ding and R Harjani, A Universal Analytic Charge Injection Model, IEEE ISCAS Proceedings, vol. 1, pp , May [3] I. Galton, Digital Cancellation of D/A Converter Noise in Pipelined A/D Converters, IEEE Trans. CAS II, vol. 47, no. 3, pp , March [4] P. Yu et al., A 14b 40MS/s Pipelined ADC with DFCA, ISSCC Dig. Tech. Papers, Feb [5] Myung-Jun Choe, Bang-Sun Song, K. Bacrania, A 13b 40Msample/s CMOS Pipelined Folding ADC with Background Offset Trimming, ISSCC Dig. Tech. Papers, pp , Feb

2 ISSCC 2004 / February 18, 2004 / Salon 8 / 2:30 PM Figure : S/H circuit with bootstrapped switch. Figure : Pipeline A/D with SD-CGC calibration. Figure : PSD with dither, subtractive dither and SD-CGC techniques. Figure : SNDR & SFDR vs. clock frequency. Figure : SNDR & SFDR vs. input frequency. Figure : Performance summary.

3 Figure : Chip microphotograph.

4 Figure : S/H circuit with bootstrapped switch.

5 Figure : Pipeline A/D with SD-CGC calibration.

6 Figure : PSD with dither, subtractive dither and SD-CGC techniques.

7 Figure : SNDR & SFDR vs. clock frequency.

8 Figure : SNDR & SFDR vs. input frequency.

9 Figure : Performance summary.

10 Figure : Chip microphotograph.