EE247 Lecture 23. Advanced calibration techniques. Compensating inter-stage amplifier non-linearity Calibration via parallel & slow ADC

Transcription

1 EE247 Lecture 23 Pipelined ADCs Combining the bits Stage implementation Circuits Noise budgeting Advanced calibration techniques Compensating inter-stage amplifier non-linearity Calibration via parallel & slow ADC Figures of merit (FOM) and trends for ADCs How to use/not use FOM EECS 247 Lecture 23: Data Converters 2005 H. K. Page 1 Summary Pipelined A/D Converters V in B 1 bits 2 B1 B 2 B2 B 3 bits 2 B3 2 bits ADC ADC DAC - + Cascade of low resolution stages Stages operate concurrently- trades latency for complexity & conversion speed Throughput limited by speed of one stage Fast Errors and correction Built-in redundancy compensate for sub-adc inaccuracies Digital calibration compensates: Inter-stage gain inaccuracy Sub-DAC error EECS 247 Lecture 23: Data Converters 2005 H. K. Page 2

2 Combining the Bits Example: Three 2-bit stages, no redundancy B 1 B 1eff B 2 B 2eff B 3 V in Stage 1 Stage 2 Stage D 1 2 D 2 2 D 3 D out + + 1/2 2 1/2 2 1 D out = D1 + D D 3 EECS 247 Lecture 23: Data Converters 2005 H. K. Page 3 Combining the Bits D 1 XX D 2 XX D 3 XX D out DDDDDD Only bit shifts No arithmetic circuits needed B 1 B 1eff B 2 B 2eff B 3 V in Stage 1 Stage 2 Stage 3 MSB LSB D out[5:0] EECS 247 Lecture 23: Data Converters 2005 H. K. Page 4

3 Combining the Bits Example: Three 2-bit stages, one bit redundancy in stages 1 and 2 B 1 =3 B 1eff B 2 =3 B 2eff B 3 V in Stage 1 Stage 2 Stage 3 8 Wires??? 6 Wires D out[5:0] EECS 247 Lecture 23: Data Converters 2005 H. K. Page 5 Combining the Bits 1 D out = D1 + D D 3 B 1 =3 B 1eff D 1 XXX D 2 XXX D 3 XX D out DDDDDD B 2 =3 B 2eff Bits overlap Need adders B 3 V in Stage 1 Stage 2 Stage 3 HADD HADD FADD HADD HADD D out[5:0] EECS 247 Lecture 23: Data Converters 2005 H. K. Page 6

4 Stage Implementation CLK φ 1 φ 2 φ 1... φ 1 φ 2 acquire convert convert acquire V in Stage 1 Stage 2 Stage n V in T/H +- G V res ADC DAC Each stage needs T/H hold function Track phase: Acquire input/residue from previous stage Hold phase: sub-adc decision, compute residue EECS 247 Lecture 23: Data Converters 2005 H. K. Page 7 Stage Implementation V in T/H T/H +- G V res T/H ADC DAC Usually no dedicated T/H amplifier in each stage (Except first stage why?) T/H implicitely contained as passive samplers in stage building blocks EECS 247 Lecture 23: Data Converters 2005 H. K. Page 8

5 Stage Implementation V in T/H + - G V res T/H ADC DAC MDAC Multiply-DAC-subtract function can be lumped into a single switched capacitor circuit "MDAC" EECS 247 Lecture 23: Data Converters 2005 H. K. Page Bit Stage Implementation D1,D0 V DAC Ref: A. Abo, "Design for Reliability of Low- voltage, Switched-capacitor Circuits," UCB PhD Thesis, 1999 EECS 247 Lecture 23: Data Converters 2005 H. K. Page 10

6 1.5-Bit Stage Implementation Acquisition Cycle D1,D0 V DAC Ref: A. Abo, "Design for Reliability of Low- voltage, Switched-capacitor Circuits," UCB PhD Thesis, 1999 EECS 247 Lecture 23: Data Converters 2005 H. K. Page Bit Stage Implementation Conversion Cycle D1,D0 V DAC Ref: A. Abo, "Design for Reliability of Low- voltage, Switched-capacitor Circuits," UCB PhD Thesis, 1999 EECS 247 Lecture 23: Data Converters 2005 H. K. Page 12

7 1.5 Bit Stage Implementation Ref: A. Abo, "Design for Reliability of Low- voltage, Switched-capacitor Circuits," UCB PhD Thesis, 1999 EECS 247 Lecture 23: Data Converters 2005 H. K. Page 13 Pipelined ADC Stage Scaling Example: Pipeline using 1-bit eff stages V in Stage 1 Stage 2 Stage 3 C 1 /2 C 2 /2 C 3 /2 V in C 1 C 2 C 3 Total input referred noise power: N tot kt C1 4C2 16C3 EECS 247 Lecture 23: Data Converters 2005 H. K. Page 14

8 Pipelined ADC Stage Scaling Example: Pipeline using 1-bit eff stages V in Stage 1 Stage 2 Stage 3 V in V n1 G G G V n2 V n3 C 1 /2 C 2 /2 C 3 /2 V in C 1 C 2 C 3 Total input referred noise power: Ntot kt C1 4C2 16C3 EECS 247 Lecture 23: Data Converters 2005 H. K. Page 15 Pipelined ADC Stage Scaling C 1 /2 C 2 /2 C 3 /2 V in C 1 C 2 C 3 N tot kt C1 4C2 16C3 If all caps made the same size, backend stages contribute very little noise Wasteful, because: Power ~ Speed ~ /C Power ~ C EECS 247 Lecture 23: Data Converters 2005 H. K. Page 16

9 Pipelined ADC Stage Scaling C 1 /2 C 2 /2 C 3 /2 V in C 1 C 2 C 3 N tot kt C1 4C2 16C3 How about scaling caps down by 2 2 =4x per stage? Same amount of noise from every stage All stages contribute significant noise Noise from first few stages must be reduced Power ~ ~ C goes up! EECS 247 Lecture 23: Data Converters 2005 H. K. Page 17 Stage Scaling Example: 2-bit eff /stage Optimum capacitior scaling lies approximately midway between these two extremes Ref: D. W. Cline, P.R Gray "A power optimized 13-b 5 MSamples/s pipelined analog-to-digital converter in 1.2um CMOS," JSSC 3/1996 EECS 247 Lecture 23: Data Converters 2005 H. K. Page 18

10 Stage Scaling Power minimum is "shallow" Near optimum solution in practice: Scale capacitors by stage gain E.g. for effective stage resolution of 1bit (Gain): C/2 C/4 C/8 V in C C/2 C/4 EECS 247 Lecture 23: Data Converters 2005 H. K. Page 19 Stage Scaling Ref: D. W. Cline, P.R Gray "A power optimized 13-b 5 MSamples/s pipelined analog-to-digital converter in 1.2um CMOS," JSSC 3/1996 EECS 247 Lecture 23: Data Converters 2005 H. K. Page 20

11 Pipelined ADC Error Correction/Calibration V OS a 3 V 3 V IN V RES1 ADC DAC ε gain +ε ADC +ε DAC D 1 ε ADC, V os ε gain Error Digital adjustment Correction/Calibration Redundancy either same stage or next stage ε DAC Inter-stage amplifier non-linearity Either sufficient capacitor matching or digital calibration? EECS 247 Lecture 23: Data Converters 2005 H. K. Page 21 Inter-stage Gain Nonlinearity Invert gain stage non-linear polynomial Express error as function of V RES1 Push error into digital domain through backend Ref: B. Murmann and B. E. Boser, "A 12-b, 75MS/s Pipelined ADC using Open-Loop Residue Amplification," ISSCC Dig. Techn. Papers, pp , 2003 EECS 247 Lecture 23: Data Converters 2005 H. K. Page 22

12 Inter-stage Gain Nonlinearity a 3 V X 3 V X 2 3 ε gain V RES1 + Backend p 2 D B a = (2 + ε gain ) (...) + D B,corr - ε(d B, p 2 ) ε(db,p2) = p2db 3p2 DB + 12p2 DB +... Pre-computed table look-up p 2 continuously estimated & updated (account for temp. & other variations) Ref: B. Murmann and B. E. Boser, "A 12-b, 75MS/s Pipelined ADC using Open-Loop Residue Amplification," ISSCC Dig. Techn. Papers, pp , EECS 247 Lecture 23: Data Converters 2005 H. K. Page 23 Inter-stage Gain Nonlinearity Compensation Proof of Concept Evaluation Prototype Re-used 14-bit ADC in 0.35μm from Analog Devices [Kelly, ISSCC 2001] Modified only 1 st stage with 3-b eff open-loop amplifier built with simple diff-pair + resistive load instead of the conventional feedback around high-gain amp Conventional 9-b eff backend, 2-bit redundancy in 1 st stage Real-time post-processor off-chip (FPGA) Ref: B. Murmann and B. E. Boser, "A 12-b, 75MS/s Pipelined ADC using Open-Loop Residue Amplification," ISSCC Dig. Techn. Papers, pp , 2003 EECS 247 Lecture 23: Data Converters 2005 H. K. Page 24

13 Measurement Results 12-bit ADC w Extra 2-bits for Calibration (a) without calibration INL [LSB] RNG=0 RNG= Code (b) with calibration (b) with calibration INL [LSB] Code C d EECS 247 Lecture 23: Data Converters 2005 H. K. Page 25 Least Mean Square Adaptive Digital Background Calibration of Pipelined Analog-to- Digital Converters Slow, but accurate ADC operates in parallel with pipelined (main) ADC Slow ADC samples input signal at a lower sampling rate (f s /n) Difference between corresponding samples for two ADCs (e) used to correct fast ADC digital output via an adaptive digital filter (ADF) based on minimizing the Least-Mean-Squared error Ref: Y. Chiu, et al, Least Mean Square Adaptive Digital Background Calibration of Pipelined Analog-to-Digital Converters, IEEE TRANS. CAS, VOL. 51, NO. 1, JANUARY 2004 EECS 247 Lecture 23: Data Converters 2005 H. K. Page 26

14 Example: "A 12-bit 20-MS/s pipelined analogto-digital converter with nested digital background calibration" Pipelined ADC operates at has 1.5bit/stage Slow ADC Algorithmic type operating at 20Ms/32=625kS/s Digital correction accounts for bit redundancy Digital error estimator minimizes the mean-squared-error Ref: X. Wang, P. J. Hurst, S. H. Lewis, " A 12-bit 20-Msample/s pipelined analog-to-digital converter with nested digital background calibration, IEEE JSSC, vol. 39, pp , Nov EECS 247 Lecture 23: Data Converters 2005 H. K. Page 27 Alogrithmic ADC Used for Calibration of Pipelined ADC Uses replica of pipelined ADC stage Requires extra SHA in front to hold residue Undergoes a calibration cycle periodically prior to being used to calibrate pipelined ADC Ref: X. Wang, P. J. Hurst, S. H. Lewis, " A 12-bit 20-MS/s pipelined analog-to-digital converter with nested digital background calibration, IEEE JSSC, vol. 39, pp , Nov EECS 247 Lecture 23: Data Converters 2005 H. K. Page 28

15 12-bit 20-MS/s Pipelined ADC with Digital Background Calibration Sampling capacitors scaled: Input SHA: 6pF Pipelined ADC: 2pF,0.9,0.4,0.2, 0.1,0.1 Algorithmic ADC: 0.2pF Chip area: 13.2mm 2 Does not include digital calibration circuitry estimated ~1.7mm 2 Ref: X. Wang, P. J. Hurst, S. H. Lewis, " A 12-bit 20-MS/s pipelined analog-to-digital converter with nested digital background calibration, IEEE JSSC, vol. 39, pp , Nov EECS 247 Lecture 23: Data Converters 2005 H. K. Page 29 Measurement Results 12-bit 20-MS/s Pipelined ADC with Digital Background Calibration Without Calibration INL <4.2LSB With Calibration INL <0.5LSB Ref: X. Wang, P. J. Hurst, S. H. Lewis, " A 12-bit 20-MS/s pipelined analog-to-digital converter with nested digital background calibration, IEEE JSSC, vol. 39, pp , Nov EECS 247 Lecture 23: Data Converters 2005 H. K. Page 30

16 Measurement Results 12-bit 20-MS/s Pipelined ADC with Digital Background Calibration Nyquist rate Ref: X. Wang, P. J. Hurst, S. H. Lewis, " A 12-bit 20-MS/s pipelined analog-to-digital converter with nested digital background calibration, IEEE JSSC, vol. 39, pp , Nov EECS 247 Lecture 23: Data Converters 2005 H. K. Page 31 Measurement Results 12-bit 20-MS/s Pipelined ADC with Digital Background Calibration Does not include digital calibration circuitry estimated ~1.7mm 2 Alg. ADC SNDR dominated by noise Ref: X. Wang, P. J. Hurst, S. H. Lewis, " A 12-bit 20-MS/s pipelined analog-to-digital converter with nested digital background calibration, IEEE JSSC, vol. 39, pp , Nov EECS 247 Lecture 23: Data Converters 2005 H. K. Page 32

17 How Many Bits Per Stage? Many possible architectures E.g. B 1eff =3, B 2eff =1,... Vs. B 1eff =1, B 2eff =1, B 3eff =1,... Complex optimization problem, fortunately optimum tends to be shallow... Qualitative answer: Maximum speed for given technology Use small resolution-per-stage (large feedback factor) Maximum power efficiency for fixed, "low" speed Try higher resolution stages Can help alleviate matching requirements in front-end Ref: Singer VLSI 96, Yang, JSSC 12/01 EECS 247 Lecture 23: Data Converters 2005 H. K. Page & 12-Bit State-of-the-Art Implementations Reference Bits Architecture SNR/SFDR Speed Power Yang (JSSC 12/2001) 0.35μ/3V ~73dB/88dB 75MS/s 340mW Loloee (ESSIRC 2002) 0.18μ/3V ~66dB/75dB 80MS/s 260mW EECS 247 Lecture 23: Data Converters 2005 H. K. Page 34

18 10 & 8-Bit State-of-the-Art Implementations Reference Bits Architecture SNR/SFDR Speed Power Yoshioko et al (ISSCC 2005) 0.18μ/1.8V bit/stage ~55dB/66dB 125MS/s 40mW Kim et al (ISSCC 2005) 0.18μ/1.8V ~48dB/56dB 200MS/s 30mW EECS 247 Lecture 23: Data Converters 2005 H. K. Page 35 ADC Figures of Merit Objective: Want to compare performance of different ADCs Can use FOM to combine several performance metrics to get one single number What are reasonable FOM for ADCs? How can we use and interpret them? Trends? EECS 247 Lecture 23: Data Converters 2005 H. K. Page 36

19 ADC Figures of Merit FOM 2 1 = f s ENOB This FOM suggests that adding a bit to an ADC is just as hard as doubling its bandwidth Is this a good assumption? Ref: R.H. Walden, "Analog-to-digital converter survey and analysis," IEEE J. Selected Areas Comm., April 1999 EECS 247 Lecture 23: Data Converters 2005 H. K. Page 37 Survey Data 1bit/Octave Ref: R.H. Walden, "Analog-to-digital converter survey and analysis," IEEE J. Selected Areas Comm., April 1999 EECS 247 Lecture 23: Data Converters 2005 H. K. Page 38

20 ADC Figures of Merit FOM 2 = fs 2 Power ENOB Sometimes inverse of this metric is used In typical circuits power ~ speed, FOM 2 captures this tradeoff correctly How about power vs. ENOB? One more bit 2x in power? Ref: R.H. Walden, "Analog-to-digital converter survey and analysis," IEEE J. Selected Areas Comm., April 1999 EECS 247 Lecture 23: Data Converters 2005 H. K. Page 39 ADC Figures of Merit One more bit means... 6dB SNR, 4x less noise power, 4x bigger C Power ~ ~ C increases 4x Even worse: Flash ADC Extra bit means 2x number of comparators Each of them needs double precision Transistor area 4x, Current 4x to keep same current density Net result: Power increases 8x EECS 247 Lecture 23: Data Converters 2005 H. K. Page 40

21 ADC Figures of Merit FOM 2 seems inappropriate, but somehow still standard in literature, papers "Tends to work" because: Not all power in an ADC is "noise limited E.g. Digital power, biasing circuits, etc. Avoid comparing different resolution ADCs using FOM 2! EECS 247 Lecture 23: Data Converters 2005 H. K. Page 41 ADC Figures of Merit FOM = 3 Power Speed Compare only power of ADCs with approximately same ENOB Useful numbers: 10b (~9 ENOB) ADCs: 1 mw/msample/sec Note the ISSCC 05 example: 0.33mW/MS/sec! 12b (~11 ENOB) ADCs: 4 mw/msample/sec EECS 247 Lecture 23: Data Converters 2005 H. K. Page 42

22 10-Bit ADC Power Yoshioko ISSCC 05 EECS 247 Lecture 23: Data Converters 2005 H. K. Page Bit ADC Power Loloee (ESSIRC 2002) EECS 247 Lecture 23: Data Converters 2005 H. K. Page 44

23 1.0E+12 Performance Trend Bandwidth x Resolution [Hz-LSB] 1.0E E+10 2x/5 years 1.0E EECS 247 Lecture 23: Data Converters 2005 H. K. Page 45 The Dream Transceiver "Software Radio" e.g.: SNR 100dB BW 30MHz Frequency few GHz Ref: Schreier, "ADCs and DACs: Marching Towards the Antenna," GIRAFE workshop, ISSCC 2003 EECS 247 Lecture 23: Data Converters 2005 H. K. Page 46

24 ADC for Software Radio Bandwidth x Resolution [Hz-LSB] 1.0E E E E+10 Software Radio Poulton, 8-bit 20GS/s ISSCC 03, Power=10W 1.0E EECS 247 Lecture 23: Data Converters 2005 H. K. Page 47 Today's Transceiver... Ref: Schreier, "ADCs and DACs: Marching Towards the Antenna," GIRAFE workshop, ISSCC 2003 EECS 247 Lecture 23: Data Converters 2005 H. K. Page 48