Fundamentals of Data Conversion: Part I.1

Transcription

1 Fundamentals of Data Conversion: Part I.1 Sebastian Hoyos Several of these slides were provided by Dr. Jose Silva-Martinez and Dr. Jun Zhou

2 Outline Fundamentals of Analog-to-Digital Converters Introduction Sampling and Quantization Quantization noise and distortion INL and DNL Technological related issues Sample and Hold Switching issues S/H Accuracy Active S/H Switch around S/H

3 The Smartphone market Global smartphone market projected to grow Anticipated global unit sales to approach 400 millions in 2013 (market research report from Forward Concepts Co) Projected revenue in 2012: $32.2 billion (source: In-Stat Group)

4 Multi-standard Wireless Systems Multiple services Reuse circuits as much as possible Power Area Competitiveness GSM WiFi Smaller Cell phone, stronger function, longer battery duration WCDMA Bluetooth Use of digital (analog unfriendly) nanometric tecnologies FM WiMax & GPS

5 Multi-standard Wireless Systems Exponential growth in mobile computing and broadband wireless Major need for high dynamic range, wide-bandwidth, low power ADCs.

6 Bandwidth requirements for higher connectivity Specturm > 45 db DTV IS-95 GSM DECT Bluetooth, b and g UMTS a Frequency (GHz) Higher flexibility on operational frequency and bandwidth, higher blocker rejection, higher dynamic range Receiver Architectures: Super-heterodyne, Low-IF, Direct Conversion, High-IF, Digital Radio

7 What is an Analog-to-Digital Converter (ADC)? Analog Digital Continuous with no apparent discontinuities The way we interpret our surroundings: sound, light, temperature etc ADC Discrete with limited range; based on binary numbers with limited number of bits. The way we mathematically represent and process our world using electronic brain power

8 R. Walden, 1999

9 How does an ADC work? Analog Digital Continuous with no apparent discontinuities x(t) Sampling The way we interpret our surroundings: sound, light, δ(t-nt S ) temperature etc x(nt S ) ADC Quantization x(nt S )+q(nt S ) Discrete with limited range; based Decoding on binary numbers with limited number N bits of bits The 1 way 001 we mathematically represent and process our world using electronic brain power

10 How does an ADC work? Analog x(t) ADC x(n) Digital t nt S x(t) Sampling δ(t-nt S ) x(nt S ) Quantization Quantization noise x(nt S )+q(nt S ) x(n) Decoding N bits δ(n) 2 N Levels separated by 1LSB, 1LSB = V FS* / 2 N nt S nt S * V FS = full scale range, V max -V min

11 ADCs: Yesterday vs. Today 2000 Example: Digital photography (8-12b ADCs) 2009 CCD/ CMOS Image Array AMP Balance Control ADC DSP (black level compensation, encoding...etc) CCD/ CMOS Image Array AMP ADC DSP (balance control, black level compensation, image stabilization, exposure levels, noise reduction, lens shading correction, encoding...etc) µm CMOS with 5V supply (moderate gate density and speed in DSPs) 2M pixel CCD sensor (low pixel scanning speed) Some pre-adc analog conditioning ~ 2.5mV / LSB 90nm-180nm CMOS with V supplies (high gate density and speed in DSPs) 12M pixel CCD sensor (high pixel scanning speed) Minimal pre-adc analog conditioning ~ 0.5mV / LSB Faster DSPs capable of performing numerous complex functions are developed thanks to advanced CMOS ADCs are indispensable, but now need to handle smaller signals at higher speeds with similar or higher resolutions. ADCs are becoming the bottleneck for advancement, and new design techniques need to be developed.

12 ADCs: Tomorrow? ADC IEEE literature survey: Resolution (bits) Sigma-Delta Pipelined Flash Signal Bandwidth (MHz) Pipeline ADC is currently most published architecture Pipeline ADC is breaking the trend set by Sigma- Delta and Flash ADCs Pipeline ADC is breaking the trend set by Sigma- Delta and Flash ADCs, and driven by consumer electronics Pipeline ADC is expected to be a key ADC architecture in future applications Pipeline ADC Applications Today Tomorrow 15M? 20M? From 1080P to 4K (2160P)? 4G? HDTV? The development of new design techniques for high speed, low voltage and low power Pipeline ADCs is crucial to stay on the future applications roadmap

13 Design Challenges of Pipeline ADCs in Advanced CMOS Technologies (Summary) High Speed Low Voltage Low Power Digital Camera Example CCD/ CMOS Image Array AMP ADC DSP (balance control, black level compensation, image stabilization, exposure levels, noise reduction, lens shading correction, encoding...etc) With the added speed of new generations of DSPs, the ADC is becoming the bottleneck for overall system speed in addition to increased speed, the DSP ability to perform more complex tasks will require higher ADC resolutions Reduction of Device size allows for denser integration, but device reliability dictate lower supply voltages Reduced supplies means reduced signal range, which requires a higher ADC accuracy for the same number of bits Many applications are portable and operated from a battery As a potentially power hungry component, the ADC power needs to be reduced to help prolong battery life

14 Super-heterodyne Receiver Antenna RF ( GHz) High IF ( MHz) BPF LNA BPF VGA Baseband (< 20 MHz) LPF Baseband ADC Digital Output LO1 LO2 Invented by Armstrong in 1918 Hardware specific radio architecture Extensive filtering to relax ADC specs Suitable for narrow-band applications

15 Design issues for multi-standard solutions Antenna RF ( GHz) High IF ( MHz) BPF LNA VGA BPF Baseband (< 20 MHz) LPF Baseband ADC Digital Output Limited by flicker noise Not flexible Hardware intensive LO1 LO2 Excessive power at the front-end (Linearity issues) Extensive down conversions: LO and mixers increase both noise and power consumption Extensive filtering: Area, Power and Noise issues Not fully compatible for the Telecoms roadmap

16 Current Multi-standard designs Antenna RF (1-2 GHz) Receiver for standard 1 IF ( MHz) BPF LNA VGA BPF Minimum sharing of blocks Area and power consumption overhead LO1 LO2 Not Flexible at all RF Switch RF (1-2 GHz) Receiver for standard 2 IF ( MHz) BPF LNA VGA BPF Limited number of standards can be accommodated LO1 LO2

17 Introduction to Analog-to-Digital Converters Analog-to-Digital Converters (ADC) are necessary to convert real world signals (which are analog in nature) to their digital equivalents for easy processing. Common applications for ADCs are communication systems, TV receivers, Digital Oscilloscopes, Audio applications.. Analog

18 Efficient radio transceiver: Direct Conversion Antenna Frequency Synthesizer 16-Channel Multiband Digital Receiver RF signal Antenna IF Filter 1 RF Filter 1 LNA & VGA Mixer 80 MHz ADC 1 Optional 4- channel digital receiver 4- channel digital receiver Software Platform DSP RF signal RF Filter 2 LNA & VGA Mixer IF Filter 2 ADC 2 4- channel digital receiver or FPGAs 4- channel digital receiver Direct conversion + broadband ADC (1 receiver per service) Lowpass filter is required (~ mw) bits 80 MHz Lowpass ADC (500 mw from ADI) Bank of receivers, filters and ADCs

19 Recent Approaches to Broadband Receivers Sample rate, downsampling and filtering R. Crochiere and L. Rabiner, Multirate Digital Signal Processing. Englewood Cliffs, NJ: Prentice Hall, Sampling with built-in anti-aliasing Y. S. Poberezhskiy et.al. Sampling and signal reconstruction circuits performing internal antialiasing filtering and their influence on the design of digital receivers and transmitters, TCASI, Jan A discrete-time RF sampling receiver R. B. Staszewski, et. al. All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS, IEEE J. Solid-State Circuits, Dec SDR receiver Abidi, The path to software-defined radio receiver, IEEE JSSC, May 2007 Frequency-domain-sampling receivers S. Hoyos and B. M. Sadler, Ultra-wideband analog to digital conversion via signal expansion, IEEE Transactions on Vehicular Technology, Sept

20 UCLA SDR receiver Direct conversion with tunable LO in the freq. range 800 MHz to 6 GHz. Cascade of sinc N filters followed by decimation to achieve the initializing needed. Good for narrowband signals as a single ADC can handle the bandwidth. But SDR should also be good for wideband and ultra-wideband signals. Need parallel ADC to sample at a fraction of Nyquist rate. Parallelization of the front-end will be needed if want to keep the ADC sampling rate down. A. Abidi, The path to software-defined radio receiver, IEEE JSSC, May 2007

21 Frequency-Domain ADC Based on Fourier Coefficients x A/D 1 Tc F0 F1 F2 FN-1 x ( 1 m Mixers and integrators. Lower frequency sample and hold requirements. A/D R 1 R 2 R 0 No signal reconstruction. Parallel digital processing. Optimal bit allocation minimizes quantization error. Some samples may not be quantized at all. S. Hoyos and B. M. Sadler, Ultra-wideband analog to digital conversion via signal expansion, IEEE Transactions on Vehicular Technology, Sept RN 1

22 Software radio transceiver: Design Issues Antenna RF signal RF Filter LNA & VGA Vin BP-Σ -ADC Dout Makes it sense to have a multi-standard solution based on this architecture? Bandwidth required? Dynamic range required? DTV SNRsignal=25 db; Blockers > 45 db; Crest factor > 20 db LNA+VGA+ADC Dynamic Range over 90 db (practical?) Can you use tracking filters? (back to the past)

23 Ultimate goal: Reality or Dream Antenna RF signal T/R switch Linear RF Power amplifier Filter + LNA DAC ADC Reconfigurable programs DSP Concept introduced in 1991 Modulation/demodulation waveforms in software Flexible multi-standard software architecture

24 Roadmap for high-resolution Receivers 1 RF A/D DSP RF Filter Anti- Aliasing Filter SCF, G m C OP-RC BB DR 2 RF A/D DSP RF Filter Anti- Aliasing Filter Dig. Filter IF or BB DR 3 G A/D DSP RF Filter LNA Dig. Mod. Dig. Filter RF How much RF processing should be done before the ADC? The front-end must be scalable and configurable to fit multiple standards

25 25 The single-chip Transceiver Paradigm Modern technologies: Digital intensive System-on-Chip (SOC) environment Scaling of transistor dimensions in digital CMOS technologies Increased intra-die variability from device scaling Defect densities increase in newer technologies Yields decrease as SOC chip sizes increase Yield impact on analog specifications leads to process corner-based overdesign to allow for analog parameter variations Increased test cost Critical Analog components must be minimized M. Onabajo, 2011

26 Fast CMOS ADC s: State of the art Specturm Trends: Extensive use of parallelism Time interleaved Freq (GHz) Reduced supply voltages make analog more challenging Resolution 16 Calibrate Headroom for amplifiers d Research Goal Little room for cascoding 14 Pipeline Poor devices if V DS is further 12 BP Sigma-delta reduced 10 Pipeline Pipeline Interleaved Use techniques that take advantage 8 of digital trends 6 Flash Digital circuitry is cheap and fast 4 Tendency is Digitally Assisted Analog 10 MS/s 100MS/s 1GS/s 10GS/s 100GS/s Circuits Sampling rate

27 R. Walden, 1999

28 Where we were in 99? Where we are? LTE

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30 A Little bit of History

31 A Little bit of History

32 Jitter and noise limitations on ENOB

33 Classic FoM to compare ADCs Recent Σ modulators

34 Bandwidth (Nyquist) vs. SNDR BW [Hz] 1.E+11 1.E+10 1.E+09 1.E+08 1.E+07 1.E+06 1.E+05 1.E+04 1.E SNDR [db] ISSCC VLSI ISSCC 2009 Jitter=1psrms Jitter=100fsrms B. Murmann, "ADC Performance Survey ,

35 Energy per conversion at Nyquist rate 1.E+07 1.E+06 1.E+05 P/f s [pj] 1.E+04 1.E+03 1.E+02 1.E+01 1.E+00 1.E SNDR [db] ISSCC 2010 ISSCC VLSI FOM=100fJ/conv-step FOM=10fJ/conv-step B. Murmann, "ADC Performance Survey ,

36 Data Converters: The main issue The quantized signal presents a finite number of output values that are associated with digital codes

37 What the problem is?

38 Issues: Sampling, Holding and conversion The quantized signal presents a finite number of output values that are associated with digital codes

39 Properties of the Fourier Series

40 Properties of the Fourier Series Modulation properties Convolution in time

41 Relevant properties of the Fourier Series Product in time

42 Relevant properties of the Fourier Series

43 Additional properties of the Fourier Series

44 Define the problem: Sampling Operation

45 Sampling Operation: Nyquist Rate According to the sampling theorem: If no alias issues, then Ideal sampling does not add distortion but replicas of the original spectrum

46 Signal Sampling Theorem Time domain sampling Frequency Spectrum

47 Signal Sampling employing a train of pulses Time domain sampling with pulses Spectrum

48 Alias issue if undersampling

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50 Under-sampling of a broadband signal

51 S/H and Quantization errors The sampling and Held operations generate alias frequency components and (sinc) signal distortion, respectively Error is an odd function (no even harmonic distortions, why?) Quantization generates harmonic distortion components when sinusoidal input signals are used S ( t) = S ( t) Error( t) in q + Error signal Quantized signal Freq Freq

52 Distortion due to quantization errors

53 ADC metrics: Quantization error Signal is sampled at given instants Signal is encoded to a limited number of codes resulting in quantization noise (random signals) and distortion (periodic signals)

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55 What the fundamental problem is? Mapping an infinite resolution analog signal into a digital but finite resolution representation

56 Quantization noise for Random (Ramp) input signal

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58 ADC metrics: SQNR The maximum Signal-to-Quantization Noise ratio (SQNR) for an N-bit ADC: SQNR P A P / 2 ( N / ) db 2 signal ideal = = Pnoise noise = 2 / 12 = 6. 02N For an ADC with a measured SNDR, the effective number of bits is defined as: ENOB = SNDR(dB)

59 Quantization noise density The dynamic range of a system is equal to the signal to noise ratio measured over a bandwidth equal to half of the sampling (Nyquist) frequency Then, σ 2 = 2 q 12 Is the total while the quantization noise density (quantization noise measured in a bandwidth of 1 Hz) Noise density = 2σ f s 2 = 2 q 6f s -fs/2 fs/2

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61 Incommensurate f s and f in Sampling frequency f s is fixed. Input frequency f in is chosen to satisfy (a) integer number of cycles C and (b) N / C = f s / f in is incommensurate. An easy way is to make N a power of 2 and C a prime number. Additionally to guarantee that the input frequency falls on a DFT freq. bin use f in = f s /2-kf s /N, where k is an integer. Then check inconmesurate requirement. Windowing lifts the need to have an integer number of cycles. Good for measurements. Pick N depending on noise floor requirements: The DFT noise floor is 10*log10(N/2) below the noise floor. Then DFT noise floor = -SNR_ 0dFS -10*log10(N/2).

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64 Practical Limitations

65 Digital to Analog Converters

66 Practical Definitions

67 Practical Limitations

68 Practical Limitations Quite critical issue! Usually not a major issue

69 Practical Limitations: Offset error

70 Practical Limitations Usually not a major issue Quite critical issue!

71 Practical Limitations: Gain error

72 Practical Limitations: Differential Error

73 Practical Limitations

74 Practical Limitations: Integral error

75 Practical Limitations

76 Practical Limitations: Absolute Accuracy

77 Analog to Digital Converters Usually the effects of the systematic offsets can be minimized through calibration or accounted in digital domain

78 Digital to Analog Converters

79 Practical Limitations

80 Practical Limitations

81 Practical Limitations DNL must be smaller or equal to 1 LSB

82 Practical Limitations

83 Offset Voltages

84 Practical Limitations

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