Cascaded Noise Shaping for Oversampling A/D and D/A Conversion Bruce A. Wooley Stanford University

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2 Outline Oversampling modulators for A-to-D conversion Cascaded ΣΔ modulators Low-voltage ΣΔ modulator design for MHz-bandwidth signals Cascaded noise shaping for bandpass oversampling D-to-A conversion Bruce A. Wooley Stanford University, 2005

3 Analog-to-Digital Conversion Digital Processor Filtering Sampling Quantization Processing Quantizer model: e Q [n] p(e Q ) Σ 1/Δ -Δ/2 Δ/2 Bruce A. Wooley Stanford University, 2005

4 Quantization Noise Shaping N B S Q (f) -f S /2 -f B f B f S /2 Quantizer resolution increased by 3 db per octave of OVERSAMPLING S Q (f) N B -f S /2 -f B f B f S /2 Quantizer resolution increased through NOISE SHAPING Bruce A. Wooley Stanford University, 2005

5 Oversampling Modulators Embed quantizer in a feedback loop to achieve larger improvement in resolution with increased oversampling Feedback can be used for PREDICTION (Δ modulation) or NOISE SHAPING (ΣΔ modulation) Noise shaping modulators are more robust and easier to implement than predictive modulators Bruce A. Wooley Stanford University, 2005

6 Sigma-Delta (or Delta-Sigma) Modulation E Q (z) Integrator X(z) Σ z -1 1 z -1 A/D Y(z) D/A Y(z) = z "1 X(z) (1" z "1 )E Q (z) N E (f) = [ 2sin ( "f / f S )] 2 N Q (f) Bruce A. Wooley Stanford University, 2005

7 ΣΔ Modulator Response 0.6 Modulator Input, Quantizer Output Time (t/t) Bruce A. Wooley Stanford University, 2005

8 Noise Shaping Ideal Digital Lowpass Filter First-Order Noise Shaping f B f N f S /2 Frequency Bruce A. Wooley Stanford University, 2005

9 Higher-Order Noise-Shaping Modulators The order of the noise shaping can be increased using either or Single quantizer modulators Multi-loop noise differencing Single loop with multi-order filtering Cascaded (multistage) modulators Bruce A. Wooley Stanford University, 2005

10 Noise-Differencing ΣΔ Modulators Y(z) = z 1 X(z) (1 z 1 ) L E(z) Noise Shaping LP Filter L=3 L=2 L=1 f B f N f S /2 Frequency Bruce A. Wooley Stanford University, 2005

11 ΣΔ Modulator Dynamic Range (with 1-bit quantization) Dynamic Range (db) L=3 L=2 L= Oversampling Ratio Bruce A. Wooley Stanford University, 2005

12 Single-Quantizer ΣΔ Modulator E(z) X(z) A(z) Y(z) F(z) Y(z) = H X (z)x(z) H E (z)e(z) where and H X (z) = A(z) 1 A(z)F(z), H E (z) = 1 1 A(z)F(z) A(z) = H X(z) H E (z), F(z) = 1" H E(z) H X (z) Bruce A. Wooley Stanford University, 2005

13 Noise Differencing Modulators Y(z) = z 1 X(z) (1 z 1 ) L E(z) Can implement with a single quantizer and L nested loops Limit cycle instability for L > 2 For L = 2 z "1 A(z) = (1" z "1 ) 2 and F(z) = 2 " z "1 Integrator 1 Integrator 2 Integrator L E X 1 1 z!1 " 1!z!!1 " " " 1!z!1 1!z!1!! Y Bruce A. Wooley Stanford University, 2005

14 2nd-Order Modulator Implementation X! " " z!1 A(z) " z!1 E " Y F(z) "! " z!1! E X! " " z!1! " " z!1 " Y Unity Transfer Function z!1 " "! z!1 Bruce A. Wooley Stanford University, 2005

15 Bruce A. Wooley Stanford University, nd-Order ΣΔ Modulator X! Y E " " " z!1 " z!1 "! X! Y E " " " z!1 " z!1 "! "!

16 Bruce A. Wooley Stanford University, nd-Order ΣΔ Modulator X! Y E " " " z!1 " z!1 " 2! X! Y E " " " z!1 "! 2 1 " z!1 2!

17 2nd-Order Noise-Differencing ΣΔ Modulator * (with 1-bit quantization) Can scale only w/ 1-bit quantizer x(nt)! 1 2 INTEGRATOR 1! DELAY! 1 2 INTEGRATOR 2! DELAY QUANTIZER 1-bit A/D y(nt) q(nt) D/A * B. Boser, JSSC, Dec.1988 Bruce A. Wooley Stanford University, 2005

18 Cascaded ΣΔ Modulators Quantizer error quantized by subsequent stage and then digitally filtered and subtracted from output of preceding stage Cancellation of lower-order noise-shaping terms depends on matching of analog and digital paths No potential instability if use first- and second-order stages Bruce A. Wooley Stanford University, 2005

19 Cascaded Noise-Shaping Modulator Analog In x!" e y Delay! Digital Out ADC Digital Difference Matches noise shaping of quantization error in first-stage Bruce A. Wooley Stanford University, 2005

20 Maximum Improvement in Dynamic Range Simulation Closed form equation Independent of OSR Coefficient Mismatch (%) Bruce A. Wooley Stanford University, 2005

21 Third-Order (2-1) Cascaded Modulator x 2 nd order!" y 1 Error Cancellation y e 1 1 st order!" y 2 Y 1 (z) = z "2 X(z) (1" z "1 ) 2 E 1 (z) Y 2 (z) = z "1 E 1 (z) (1" z "1 )E 2 (z) Y(z) = z "1 Y 1 (z) " (1" z "1 ) 2 Y 2 (z) = z "3 X(z) (1" z "1 ) 3 E 2 (z) Bruce A. Wooley Stanford University, 2005

22 2-1 Cascaded ΣΔ Modulator x $ # $ # y b "! $ - $ - # y 2 Bruce A. Wooley Stanford University, 2005

23 Matching Error in 2-1 Cascade 10 Loss in Dynamic Range (db) Calculated Simulated Matching Error (%) Bruce A. Wooley Stanford University, 2005

24 Spectrum of 2-1 Cascade w/ Mismatch 0 Spectral Power (db) Frequency (khz) Bruce A. Wooley Stanford University, 2005

25 Matching Error in Cascade 35 Loss in Dynamic Range (db) Calculated Simulated Matching Error (%) Bruce A. Wooley Stanford University, 2005

26 Spectrum of Cascade w/ Mismatch 0 Spectral Power (db) Frequency (khz) Bruce A. Wooley Stanford University, 2005

27 Advantages of 2-1 Cascade Low sensitivity to precision of analog circuits Suppression of spurious noise tones resulting for correlation of quantization noise with input Considerable design flexibility No potential instability Bruce A. Wooley Stanford University, 2005

28 Analog Integration in CMOS Continuous Time (tune g m or MOS-R) g m -C MOSFET-C Sampled Data Switched current Switched capacitor Bruce A. Wooley Stanford University, 2005

29 Analog Integration in CMOS Continuous-time (g m -C or MOSFET) Tune g m or MOS resistor Performance limited by timing jitter, waveform asymmetry and integrator linearity Switched-current Limitations: current sources must be cascoded to increase output resistance high supply voltage large V GS V T needed to reduce sensitivity to V T mismatch high power dissipation sensitive to switch parasitics and charge injection noise introduced into compressed signal Switched-capacitor approach preferable for obtaining high resolution at low supply voltage and low power dissipation Bruce A. Wooley Stanford University, 2005

30 Low-Power ΣΔ Modulator Design * C i x 1 2 C s 1 2! H(z) Q y High-resolution converters should by limited by thermal noise kt/c noise in switched-capacitor circuits First stage limit performance and therefore dissipates a large fraction of power Minimize power by minimizing capacitor size in switched-c implementations * S. Rabii, JSSC, June 1997 Bruce A. Wooley Stanford University, 2005

31 ΣΔ Modulator Implementation 1/5 1/6 x 1/5 "!! # 1/3 " # y 1 H 1 (z) 1/20 3/4! "! y 2 # H 2 (z) "! 1/5 y Bruce A. Wooley Stanford University, 2005

32 First Stage of Modulator 1.8V 0V 1.8V 0V S2 S5 S6 0.3V 0.3V 20pF 0.9V S7 Vi() S1 4pF S3 S4! S5 S6 S8! Vi(!)!! S1 4pF S3 S4 S5 S6 S8 0.3V 20pF 0.9V S7 S2 S5 S6 0.3V 1.8V 0V 1.8V 0V S1, S5:!1 delayed, CMOS S3, S7:!1, NMOS S2, S6:!2 delayed, CMOS S4, S8:!2, NMOS Bruce A. Wooley Stanford University, 2005

33 2-Stage Class A/AB Amplifier 1.8 V V cmfb1 M 8 M 13 V bz V bz M 9 M 7 M 10 V out () M z V in () M 1 M 2 V in (!) M z V out (!) C C C C V bias V o1 (!) V o1 () M 11 M 5 M 3 M 4 M 6 M 12 Bruce A. Wooley Stanford University, 2005

34 Die Photo of 1.8-V CMOS ΣΔ Modulator Bruce A. Wooley Stanford University, 2005

35 Measured SNR and SNDR 100 SNR 80 SNDR Input Level (db) Bruce A. Wooley Stanford University, 2005

36 Measured Baseband Output Spectrum !20 db, 2 khz Input Frequency (khz) Bruce A. Wooley Stanford University, 2005

37 Dynamic Range vs. Oversampling Ratio Oversampling Ratio Bruce A. Wooley Stanford University, 2005

38 Dynamic Range & Power vs. Supply Voltage Power Dynamic range Supply Voltage (V) 2.0 Bruce A. Wooley Stanford University, 2005

39 1.8-V CMOS ΣΔ Modulator Performance Dynamic range Peak SNR Peak SNDR Bandwidth Oversampling ratio Power dissipation Active area Technology Threshold voltages 99 db 99 db 95 db 25 khz mw 1.5 mm µm CMOS 0.65 V, 0.75 V Bruce A. Wooley Stanford University, 2005

40 Power Efficiency Figure of Merit Power efficiency as a Figure of Merit: FoM = DynamicRange " Bandwidth Power = 22N " BW Power (MHz / mw) where Dynamic Range is a POWER, not voltage, ratio N = effective # of bits of resolution For circuits in which the dynamic range is limited by thermal noise and the bandwidth is not limited by technology: Quadratic dependence on voltage dynamic range Linear dependence on bandwidth Bruce A. Wooley Stanford University, 2005

41 ADC Power Efficiency Bruce A. Wooley Stanford University, 2005

42 Low-Voltage Broadband ΣΔ Modulation * Target objective is low-voltage, high-resolution broadband A/D conversion for applications such as ADSL, CDMA 2000, IS-95, and GSM Objectives Conversion rate 2.5 MSample/s Dynamic range 92 db (15 bits) Power supply 1.2V Power dissipation ~ 80 mw Technology 0.25-µm CMOS * K. Nam, 2004 CICC Bruce A. Wooley Stanford University, 2005

43 Analog Low V DD Reduced voltage headroom Limited choice of op amp topologies Dynamic range decreases unless noise floor is reduced Low-voltage analog high power In this work consider architecture and circuits needed to achieve low voltage and low power Bruce A. Wooley Stanford University, 2005

44 Low-Voltage, Low-Power Strategies Low oversampling ratio & high-order modulator Maximize the full-scale input amplitude for a given V DD Multi-bit quantization Single-stage op amps Linear integrator settling allows use of slower op amps Bruce A. Wooley Stanford University, 2005

45 Architectural Decisions Single-bit or multi-bit quantization multi-bit single-bit feedback causes op amp slew need fast op amp single-bit quantization results in larger quantization noise leakage into the output in cascaded modulators Single-quantizer or cascade cascade Even with multi-bit quantization op amp slewing can limit performance of a high-order single-quantizer modulator use 2nd-order modulator for first stage 2-2 cascade with 5-bit and 3-bit quantizers Bruce A. Wooley Stanford University, 2005

46 Conventional First-Order ΣΔ Modulator X U 1 V 1 Y 1 z -1 N-bit z -1 DAC Y = z 1 X (1 z 1 )E U 1 = (1 z 1 )X (1 z 1 )E magnitude depends on input amplitude and frequency V 1 = z 1 X z 1 E magnitude depends on input Op amps designed to ensure minimum SNDR degradation for large signals inefficient power allocation Bruce A. Wooley Stanford University, 2005

47 Reduced Integrator Swing-Range ΣΔ Modulator X U 1 V 1 W 1 Y 1 z -1 N-bit z -1 Y = X (1 z 1 )E DAC U 1 = (1 z 1 )E U 1 LSB V 1 = z 1 E V LSB U 1 & V 1 are DECOUPLED from the input X attractive at low V DD W 1 = X z 1 E swing-range burden is moved to W 1 Approach can be extended to higher-order modulators Bruce A. Wooley Stanford University, 2005

48 Second-Order RISR ΣΔ Modulator X U z -1 z -1 1 V 1 V 2 W 1 1 z -1 Y 1 z -1 N-bit 2 Y = X (1 z 1 ) 2 E DAC U 1 = (1 z 1 ) 2 E U 1 2 LSB V 1 = z 1 (1 z 1 )E V 1 LSB V 2 = z 2 E V LSB W 1 = X z 1 (z 1 2)E * J. Silva, Elec Letters, June 2001 Bruce A. Wooley Stanford University, 2005

49 Trade-Offs in RISR ΣΔ Modulators L=1 L=2 L=3 L=4 U 1 = (1 z 1 ) L E L = 2 & N = 5 for first stage For V REF = 1.2V, X FS = 1.1V U 1 max = 150mV V 1 max = 75mV V 2 max = 37.5mV Number of quantizer bits # X FS = 2N " (2 L " 1) & % $ 2 N ( V REF " 1 ' Bruce A. Wooley Stanford University, 2005

50 Implementation Issues Integrator op amp: requirements are greatly relaxed small input signal range linear settling dominates slow op amp can be used power saving relaxed dc gain requirement small output range Quantizer: more stringent requirements multiple signals summed at quantizer input offset increases swing ranges need offset cancellation very fast regeneration needed since latch must be strobed after sampling of the input is complete Bruce A. Wooley Stanford University, 2005

51 Experimental Prototype X U z -1 z -1 1 V 1 V 2 Y 1 1 z -1 1 z -1 5-bit 2 DWA-DAC Y out V 2 z -1 z -1 z -1 1 z bit Y 2 2 DAC Bruce A. Wooley Stanford University, 2005

52 First-Stage Implementation * DWA-DAC RefP RefN X S4P j S4N j S1 j C S1j j=1,...,32 S2 S3 C I1 S5 C S2 S8 S6 S7 C I2 5-bit Y 1! 1,! 1d! 2,! 2d S1 j, S3, S5, S7 S4P j or S4N j, S2, S6, S8 * actual implementation is fully differential Bruce A. Wooley Stanford University, 2005

53 Low Distortion Input Sampling *! 1 V DD V DD V DD M4 M2 C boost M5 M3 M1 X! 1 M Sj C S1j j=1,...,32 * M. Dessouky, JSSC, March 2001 Bruce A. Wooley Stanford University, 2005

54 First Op Amp V DD V DD V DD V B1 2.4 ma 2.4 ma V B2 V in1 M1 M2 V in2 V out1 V out2 0.4 V 9.8 ma 9.8 ma V B3 Dc gain 57dB g m1 96mS CMFB Power 29mW BW CL 122MHz V CM (in) 0.15mV V CM (out) 0.65V Bruce A. Wooley Stanford University, 2005

55 Quantizer Comparator (1 of 32) X! 1 C q! 1d V Ri! 2d! 2! 2d V 1! 1 C q! 1d V os! latch -V 1 V 2! 2d! 1 C q! 2! 1d C P A 1 A 2 CM! 2d! 2! 1,! 1d! 2,! 2d! latch Bruce A. Wooley Stanford University, 2005

56 Prototype Die Photo Intg4 Quant2 Intg3 Intg2 Quant1 Intg1 DWA & Logic CLK Bruce A. Wooley Stanford University, 2005

57 Measured SNR and SNDR f in =366KHz SNR SNDR Input Level (db) Bruce A. Wooley Stanford University, 2005

58 Measured Output Spectrum 0 4-dB, 109-kHz Input -50 SFDR = 97dB Frequency (MHz) Bruce A. Wooley Stanford University, 2005

59 Performance Summary Analog Supply Voltage Sampling Rate Signal Bandwidth Dynamic Range Peak 366-kHz input Analog Power Digital Power Active Area Technology 1.2 V 40 MHz 1.25 MHz 96 db 89 db 44 mw 43 mw * 8.6 mm µm CMOS * Estimate 10 mw digital power in 0.13-µm CMOS Bruce A. Wooley Stanford University, 2005

60 Bandpass Oversampling D/A Conversion * Consider the use of cascaded noise shaping for bandpass D/A conversion in RF transmitters Move IF into the digital domain to eliminate dc offset I & Q mismatch Merge D/A conversion, noise shaping, reconstruction and mixing to IF Explore the use of cascaded noise shaping with semidigital filtering * D. Barkin, 2003 VLSI Ckts Symp Bruce A. Wooley Stanford University, 2005

61 Traditional Wireless Transmitter Architecture cos!t I M FIR/ROM DAC LPF Out Q M FIR/ROM DAC LPF sin!t Digital Analog Bruce A. Wooley Stanford University, 2005

62 Bandpass Oversampling DAC cos(!t) = [ 1, 0, -1, 0,... ] I M Noise Shaping DAC Filtering Analog IF Output Q M Noise Shaping Digital Analog sin(!t) = [ 0, 1, 0, -1,... ] Mix to IF (at f S /4) following cascaded noise shaping Error cancellation performed at IF Bruce A. Wooley Stanford University, 2005

63 Lowpass Cascaded Noise Shaping Digital Input 2 nd Order!" Modulator 1 Signal Stage 1 Error 3 rd Order!" Modulator Noise Estimate 4 (1 - z -1 ) 2 2nd-order differentiator matches noise shaping in first stage Bruce A. Wooley Stanford University, 2005

64 Bandpass DAC Architecture I Cascaded "# Modulator 1 4 (1 - z -1 ) 2-1,1! 1! 1 DAC Filtering Q Cascaded "# Modulator 1 4 (1 - z -1 ) 2 1,-1! 2! 2 f s /2 f s I and Q modulators operate at f S /2, saving power Bruce A. Wooley Stanford University, 2005

65 Discrete Time - Continuous Time Interface Signal 1-1,1 Semi-Digital Filter Noise Estimate -1,1 Digital (1 - z -1 ) Filter Digital Analog Semi-digital filtering for reconstruction of signal Good for 1-bit signal path, but not multi-bit noise estimation path Digital filter reduces out-of-band quantization noise Digital filter transfer function matches that of semi-digital filter Bruce A. Wooley Stanford University, 2005

66 Semi-Digital Filter * Digital Input 1 z -1 z -1 z -1 a 1 a 2 a N Analog Output Mismatch among current sources alters the transfer function but doesn t introduce nonlinearity Area limits number of taps and precision of coefficients Good for 1-bit signal path but not multi-bit noise estimation path * D. Su, JSSC, Dec Bruce A. Wooley Stanford University, 2005

67 Bandpass Data Weighted Averaging * 1 Semi-Digital Filter -1,1-1,1 Digital (1 - z -1 ) 2 4 Filter 11 6 BP DWA Pointer Calc f s /2 Notch f s /4 Notch I & Q pointer calculations are independent I Q Time --> * T. Shui, et al., ISCAS, 1998 Bruce A. Wooley Stanford University, 2005

68 Bandpass DAC Die Photo Noise Shapers Digital Filters Current Source Array Bias Bruce A. Wooley Stanford University, 2005

69 DAC Output Spectrum Power Spectral Density (db) (4 bit) Digital Noise Shaper Output Measured DAC Output 46 db Frequency (MHz) Bruce A. Wooley Stanford University, 2005

70 SNR and SNDR 100 SFDR & SNDR (db) Measured SFDR Measured SNDR Signal Power (db) Bruce A. Wooley Stanford University, 2005

71 Bandpass DAC Performance Technology Center frequency Bandwidth Peak SNDR Dynamic range Minimum out-of-band suppression Mirror for 6 db Input Active area Power (except for current sources) 0.25-µm CMOS 50 MHz 6.25 MHz 76 db 85 db 80 db 90 db 2.1 mm mw Bruce A. Wooley Stanford University, 2005

72 Summary Cascades of first- and second-order noise-shaping modulator stages can be used for A/D and D/A conversion lowpass and bandpass data conversion If properly designed, advantages include no potential instability decorrelation of quantization noise and input low sensitivity to analog precision Still room for architectural and circuit innovation to meet the challenges presented by technology scaling to sub-100nm dimensions performance demands of new applications Bruce A. Wooley Stanford University, 2005

73 References I OVERSAMPLING A-to-D CONVERSION 1. B. E. Boser and B. A. Wooley, The Design of Sigma-Delta Modulation Analog-to- Digital Converters, IEEE J. Solid-State Circuits, vol. 23, pp , Dec W. R. Bennett, Spectra of Quantized Signals, Bell Sys. Tech. Journal, vol. 27, pp , July F. de Jager, Delta Modulation, a Method of PCM Transmission Using the 1-Unit Code, Philips Res. Report, vol. 7, pp C. Cutler, Transmission Systems Employing Quantization, U.S. Patent No. 2,927,962, Mar. 8, H. Inose and Y. Yasuda, A Unity Bit coding Method by Negative Feedback, Proc. IEEE, vol. 51, pp , Nov J. C. Candy, A Use of Limit Oscillations to Obtain Robust Analog-to-Digital Converters, IEEE Trans. Commun., vol. COM-22, pp , Mar S. K. Tewksbury and R. W. Hallock, Oversampled, Linear Predictive and Noise- Shaping Coders of Order N>1, IEEE Trans. Circuits and Sys., vol. CAS-25, pp , July R. M. Gray, Spectral Analysis of Quantization Noise in a Single-Loop Sigma-Delta Modulator with DC Input, IEEE Trans. Commun., vol. 37, pp , Sept Bruce A. Wooley Stanford University, 2005

74 References II 9. J. C. Candy, A Use of Double Integration in Sigma Delta Modulation, IEEE Trans. Commun., vol. COM-33, pp , Mar B. P. Brandt, D. E. Wingard, and B. A. Wooley, Second-Order Sigma-Delta Modulation for Digital-Audio Signal Acquisition, IEEE J. Solid-State Circuits, vol. 26, pp , Apr J. C. Candy and G. C. Temes, Oversampling Delta-Sigma Converters, IEEE Press, S. R. Norsworthy, R. Schreier, G. C. Temes, Delta-Sigma Data Converters: Theory, Design and Simulation, IEEE Press, CASCADED ΣΔ MODULATION 9. L. Longo and M. Copeland, A 13 bit ISDN-band Oversampled ADC using Two- Stage Third Order Noise Shaping, IEEE Proc. Custom IC Conf., pp , Jan Y. Matsuya, et al., A 16-bit Oversampling A-to-D Conversion Technology Using Triple Integration Noise Shaping, IEEE J. Solid-State Circuits, vol. SC-22, pp , Dec L. A. Williams III and B. A. Wooley, Third-Order Cascaded Sigma-Delta Modulators, IEEE Trans. Circuits and Sys., vol. 38, pp , May Bruce A. Wooley Stanford University, 2005

75 References III 16. L. A. Williams III and B. A. Wooley, A Third Order Sigma-Delta Modulator with Extended Dynamic Range, IEEE J. Solid-State Circuits, vol. 29, pp , Mar B. P. Brandt and B. A. Wooley, A 50-MHz Multibit Sigma-Delta Modulator for 12-b 2- MHz A/D Conversion, IEEE J. Solid-State Circuits, vol. 26, pp , Dec S. Rabii and B. A. Wooley, A 1.8-V Digital-Audio Sigma-Delta Modulator in 0.8-µm CMOS, IEEE J. Solid-State Circuits, vol. 32, pp , June S. Rabii and B. A. Wooley, The Design of Low-Voltage, Low-Power Sigma-Delta Modulators, Kluwer Academic Publishers, 187 pp., T. B. Cho and P. R. Gray, A 10-b, 20 Msample/s Pipelined CMOS ADC, IEEE J. Solid-State Circuits, vol. 30, pp , Mar K. Vleugels, S. Rabii, and B. A. Wooley, A 2.5-V Sigma-Delta Modulator for Broadband Communications Applications, IEEE J. Solid-State Circuits, vol. 36, pp , Dec A. Tabatabaei and B. A. Wooley, A Two-Path Bandpass Sigma-Delta Modulator with Extended Noise Shaping, IEEE J. Solid-State Circuits, vol. 35, pp , Dec A. K. Ong and B. A. Wooley A Two-Path Bandpass ΣΔ Modulator for Digital IF Extraction at 20 MHz, IEEE J. Solid-State Circuits, vol. 32, pp , Dec Bruce A. Wooley Stanford University, 2005

76 References IV DECIMATION & INTERPOLATION FILTERS 24. B. P. Brandt and B. A. Wooley, A Low-Power, Area-Efficient Digital Filter for Decimation and Interpolation, IEEE J. Solid-State Circuits, vol. 29, pp , June R. E. Crochiere and L. R. Rabiner, Interpolation and Decimation of Digital Signals A Tutorial Review, Proc. IEEE, vol. 69, pp , Mar OVERSAMPLING D-to-A CONVERSION 26. D. K. Su and B. A. Wooley, A CMOS Oversampling D/A Converter with a Current- Mode Semi-Digital Reconstruction Filter, IEEE J. Solid-State Circuits, vol. 28, pp , Dec K. Falakshahi, C.-K. K. Yang and B. A. Wooley, A 14-bit 10-Msamples/s D/A Converter Using Σ-Δ Modulation, IEEE J. Solid-State Circuits, vol. 34, pp , May D. B. Barkin, A. C. Y. Lin, D. K. Su, and B. A. Wooley, A CMOS Oversampling Bandpass Cascaded D/A Converter with Digital FIR and Current-Mode Semi- Digital Filtering, IEEE J. Solid-State Circuits, vol. 39, pp , Apr Bruce A. Wooley Stanford University, 2005

Cascaded Noise-Shaping Modulators for Oversampled Data Conversion

Cascaded Noise-Shaping Modulators for Oversampled Data Conversion Bruce A. Wooley Stanford University B. Wooley, Stanford, 2004 1 Outline Oversampling modulators for A/D conversion Cascaded noise-shaping