A 25MS/s 14b 200mW Σ Modulator in 0.18µm CMOS

Transcription

1 UT Mixed-Signal/RF Integrated Circuits Seminar Series A 25MS/s 14b 200mW Σ Modulator in 0.18µm CMOS Pio Balmelli April 19 th, Austin TX

2 2 Outline VDSL specifications Σ A/D converter features Broadband Σ modulator architecture Design description Measurement results Conclusion

3 3 VDSL 1mile Internet Telephone PC 30Mbps Local loop Local exchange Public telephone network VDSL Signal Bandwidth: A/D Specifications: Resolution 12-14bit [MHz] Conversion rate >24MS/s

4 4 Σ vs. Nyquist A/D Converters Advantages: No precise sample&hold stage No complex anti-aliasing filter Better untrimmed linearity Disadvantage: Reduced conversion rate Broadband architecture: Low OSR + High sampling frequency

5 5 Broadband Architecture Discrete time: Low jitter sensitivity No excess loop delay problem x[k] f S a1 z-1 a2 z-1 Single-loop: Low capacitor matching specifications Relaxed settling accuracy DAC Q y[k] Loopfilter feed-forward topology: Small noise contribution of internal stages

6 6 Single-Bit Quantizer [db] L=7 NQ = 1b Constraints: Peak SNR L=5 L=3 L :Filter order NQ:Quantizer resolution OSR=8 Result: Single-bit quant. achieves poor SNR at low OSR [dbref] Maximum Input Level

7 7 Quantizer Resolution and Filter Order Peak SNR [db] L =4 NQ=5b L =5 NQ=4b 75 L :Filter order L =9 NQ:Quantizer NQ=3b resolution [dbref] Maximum Input Level Constraints: OSR=8 SNR > 95dB Architecture: 5 th order loopfilter and 4b quantizer, best tradeoff

8 8 Block Diagram x[k] 15 1/3 1/13 z-1 8 1/6 5 1/7 z-1 z /7z 2 z /3z z-1 1/13z z z /6z z-1 1/7z z y[k] 16 level DAC z bit Quantizer 5/9 OSR Max input SNR 8-4dB 96dB

9 9 Noise and Signal Transfer Function [db] 0 Signal transfer function Noise transfer function MHz MHz 100k 1M 10M [Hz] 100M

10 10 Switch Level Diagram x[k] 4 bit DAC 15C1 To neg. path 13C1 3C2 4C2 C2/6 5C3 7C3 To neg. 2C4 path 7C4 2C4 C5 3C5 y[k] VR ϕ2 VR 9CFF 15 Logarithmic shifter 4 4 DWA 9CFF ϕ2 15 Dynamic element matching 8CFF ϕ1 4 bit quantizer 15x rst ϕ2 ϕ1: ϕ2: 8CFF CQ 2CFF Gain stage 7

11 11 Data Weighted Averaging [Baird95] Quantizer Logarithmic shifter Q[k] s counter A[k] 4 4 ϕ2 Modulo 15 adder DAC Q*[k] DWA logic 1 st order shaping DAC elements used at maximum rate Each element selected same number of times DWA logic: # std. cells Delay 96 4ns ϕ2 y[k] Power <1mW

12 12 DWA Performance [db] 0-40 Simulated Output Power Spectrum w.o. DWA DWA σ C1 =0.23% [Hz] 100k 1M 10M 100M

13 13 Input Stage S1 S2 ϕ1 Cu1 Cu2 Shared capacitors for x[k] and V R : Ch Ch VR VR ϕ1 S15 ϕ1 ϕ2 Cu15 x[k] ϕ2 ϕ1 13Cu 3dB less kt/c noise Reduced amp. load Fast reference buffer needed Reference buffer Q1[k] Q2[k] Q15[k] S1 S2 S15 Buffer charge: [ ] d 2Q k Ch [ k] = 15C1 VR x[ k] 1 15

14 14 Reference Buffer VB M2 M1 VR IB VB M1 M2 IB VR [Piessens02] M2 reduces low freq. Impedance IB not modulated by VR Low voltage drop over M2 needed log( Zout ) Z DC g m g g m2 o2 Z MAX 1 g m1 freq. VR ZDC ZMAX Power 1.2V 1Ω 18Ω 37mW

15 15 Operational Transconductance Amplifier ϕ1 ϕ1 ϕ2 C3 C1 ϕ2 Vout M5 M7 OP2 VB M8 M6 ϕ2 C2 C4 ϕ2 ϕ1 ϕ1 Vcm Telescopic cascode for low power Regulated cascode for high DC gain High current for speed M3 M4 G DC 90dB GBW (70 o ) 1.9GHz Vin M1 OP1 M2 Swing 0.75V IB Power Pow. Scaling 53mW 2, 4, 4, 8

16 16 Gain Stage Vout CCM ϕ1 ϕ 1 ϕ 2 ϕ 2 V Bp M3 V CM R 2 R3 Vout Transistors always in saturation Const. gain over temp. and process variation Vin R1 Vin A M1 M2 Good linearity Low input capacitance IB1 Low output impedance gmr-constant bias [Opris97] IB2 Gain 3dB BW Output Load Gain var. (0.6V) Power ~7 2GHz 500fF < 5% 16.2mW

17 17 Comparator VQ VQ M1 A rst M4 M3 M5 VB1 VB2 Q Q Minimized load at node A: High tracking speed Short regeneration time ϕ2 M2 NMOS-Latch ϕ1 σoffset BW3dB 3.4mV 2.1GHz (6dB) Bootstrapped signal: ϕ H 2 =Vdd+VT tlatch Power <1ns (1µV) ~1mW

18 18 SNR, SNDR, and DR [db] MHz signal Noise power integrated up to 11.14MHz Peak SNR: 82dB Peak SNDR: 72dB Dynamic Range: 84dB Signal Power [dbfs]

19 19 Measured Spectrum Mag. [dbfs] M FFT 2.5MHz 0 Mag. [dbfs] MHz Frequency [MHz]

20 20 Chip Micrograph Separate analog/digital pad rings 0.95mm 2 core area

21 21 Performance Summary Conversion Rate Sampling frequency Oversampling ratio Dynamic range* Peak SNR* Peak SNDR* Input range Power Consumption Voltage Supply Process Core area 25MS/s 200MHz 8 84dB (82dB) 82dB (80dB) 72dB (70dB) 1.6Vpp (differential) 200mW 1.8V 0.18µm 1P6M CMOS 0.95mm 2 *Signal frequency at 2.5MHz and noise bandwidth based on main and optional (in brackets) symmetric spectral plans of VDSL.

22 22 Power Distribution 6% 3% 8% 19% 8% 3% 7% 7% 26% 13% Ref. buffer OTA 1 OTA 2 OTA 3 OTA 4 OTA 5 Gain stage Quantizer DWA Clock

23 23 Result Comparison Dynamic Range [db] [5] [1] [3] [4] [2] [7] This Work 1M 10M Input Signal Bandwidth [Hz] [6] JSSC: [1] Geerts, 2000/12 [2] Vleugels, 2001/12 [3] Fujimori, 2000/12 [5] Feldman, 1998/10 ISSCC: [4] Reutemann, 2002 ESSCIRC: [6] Di Giandomenico, 2003* [7] Luh, 2000* * Continuous time modulator

24 24 Conclusions VDSL critical ADC specifications Oversampling limits Σ ADC speed Broadband Σ ADC Low OSR + high sampling frequency Measured 82dB SNR at 25MS/s Best Σ ADC performance