Design Examples. MEAD March Richard Schreier. ANALOG DEVICES R. SCHREIER ANALOG DEVICES, INC.

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1 Design Examples MEAD March 008 Richard Schreier ANALOG DEVICES Catalog nd -Order Lowpass Architecture: Single-bit, switched-capacitor Application: General-purpose, low-frequency ADC 5 th -Order Lowpass Architecture: Multi-bit switched-capacitor Application: Audio 3-0 Cascade Architecture: (Multibit MOD, pipeline) Cascade Application: Wideband communications 4 6 th -Order Bandpass Architecture: Single-loop with LC, Active-RC and switchedcapacitor resonators Application: High-dynamic-range radio receiver

2 . MOD Specifications Parameter Symbol Value Units Bandwidth f B ~ khz Sampling Frequency f s MHz Signal-to-Noise Ratio SNR 00 db Supply Voltage VDD 3 V Assumptions Single-bit switched-capacitor realization Input voltage range is 0-VDD (single-ended) Reference voltage is VDD Op-amp swing is V pp (differential) 3 Toolbox Design OSR = 500; H = synthesizentf(,osr,0,); [snr amp] = simulatesnr(h,osr); plot(amp,snr,'bd',amp,snr,'b-'); SQNR (db) Very high SQNR Quantization noise will be negligible. Maximum input signal dbfs Let s not worry about instability Input Amplitude (db) 4

3 Block Diagram & DR Scaling U z b c X X z Q V a a form = 'CIFB'; [a,g,b,c] = realizentf(h,form); b(:end) = 0; ABCD = stuffabcd(a,g,b,c,form); [ABCDs umax] = scaleabcd(abcd); [a,g,b,c] = mapabcd(abcds,form); Code yields a = [0.7, 0.4], b = [0.7], c = [ ], u max = 0.9 Quantize to a = b = a = /4, c = /3 for convenience. 5 Simulated Spectrum PSD (dbfs/nbw) NBW =.8x0 4 f s Normalized Frequency ( f s ) STF NTF (scaled) Coefficient change has negligible performance impact Peak SQNR = 5 db, H =.. 6

4 Simplified Schematic x x L D Q C v Difference Equations x ( n + ) = x ( n) + b un ( ) a vn ( ) x ( n + ) = x ( n) + c x ( n) a vn ( ) vn ( ) = Qx ( ( n) ) Timing x (n) x (n+) x (n) x (n+) v(n) Verify that the circuit follows the difference equations. Check the quantizer and feedback timing carefully! 7 V in VDD VSS V d V d V d VDD VSS V d First Integrator C C Want input (full-scale) range = [0,3] V and want op-amp swing = [,+] V differential x = V x / V, u =(V in.5 V)/.5 V C C = b 3 = V x 0, V x = C /C (V in V DD v d ) Homework: Verify timing & polarity 8

5 Absolute Capacitor Values Absolute capacitor values are determined by thermal noise considerations Capacitor ratios are set by the desired dynamics. For example, assume noise is purely kt/c noise i.e. device noise is negligible. Since thermal noise is white, we get a factor of OSR reduction in the in-band noise i.e. v n = OSR kt C v n = 0 µv rms C = 83 ff C = pf These capacitor values are quite reasonable! C gets smaller if the output swing of the op-amp is increased. 9 V d VSS V d VDD Second Integrator C C 4C V x V x VDD VSS V d V d In-band noise of second integrator is greatly attenuated ( OSR) By a factor of (approximately). 0 6 Capacitor sizes dictated by charge injection errors and desired ratio accuracy 0 Homework: Verify capacitor ratios ± Hint: V x = (4C/C) V x (C/C) V DD v)

6 Building Block Op Amp bias4 VDD bias3 VON VIP VIN VOP vocm bias vocm bias x bias Folded-cascode op-amp with switched-capacitor common-mode feedback Op-Amp Specifications 50% of T/ = 0.5 µs; Q max = C VDD = 0.5 pc I slew = µa is sufficient T/ = 0τ; τ = C g m ; C = 0. pf g m = µa/v Power consumption can be very low! As a rule of thumb, A min OSR for negligible SQNR reduction Assumes that the op amps are linear and that the integrator gain factors are close to. SQNR margin can be traded for reduced op-amp gain requirements. In this implementation, the integrator gain factors are /3 and /, and the gain requirements are relaxed For example, A = 40 db is sufficient for 0 db SQNR and the width of the deadband around 0 V is only 4 µv if A = 40 db.

7 Building Block Latched Comparator VDD V+ V S To DFF R S R VSS Falling phase initiates regenerative action S and R connected to a Set/Reset latch 3 Building Block Clock Generator CLK * * * * D D CLK D D 4 * = Delay Control

8 . MOD5 Specifications Parameter Symbol Value Units Signal Bandwidth f B 50 khz Sampling Frequency f s 8 MHz Signal-to-Noise Ratio SNR 0 db Supply Voltage VDD 3 V Assumptions Single-bit switched-capacitor realization Input voltage range is ± V (differential) Reference voltage is V (differential) and Op amp swing is 4 V pp (differential) 5 SQNR (db) Toolbox Design OSR = 8e6/(*50e3); % OSR = 80 H = synthesizentf(5,osr,,.5); amp = [-40:5: :0]; snr = simulatesnr(h,osr,amp); plot(amp,snr,'bd',amp,snr,'b-'); Input Amplitude (db) 6 Very high peak SQNR Quantization noise will be negligible. Maximum input signal 4 dbfs Scale such that input range is 50% of full-scale.

9 First Integrator VREFP VREFN C C C V in V x VREFN VREFP Input-referred differential noise power is P n = kt C Peak signal power is P s = ( V) = V 8kT SNR 0 db SNR requires C = = pf OSR This is a big capacitor! P s 7 Dynamic Range Scaling & Topology Selection form = 'CRFB'; % or CRFF [a,g,b,c] = realizentf(h,form); b(:end) = 0; % for CRFB only ABCD = stuffabcd(a,g,b,c,form); [ABCDs umax] = scaleabcd(abcd); [a,g,b,c] = mapabcd(abcds,form); form = CRFB yields b = 0., i.e. C = 0C! The integrating capacitor is VERY large! form = CRFF yields b = 0.39, i.e. C =.5C The integrating capacitor is still large, but is more reasonable. 8

10 PSD (dbfs/nbw) Simulated Spectrum 0 dbfs input SQNR = db 40 NBW = 370 Hz Frequency (Hz) Used k derived from simulation to calculate true NTF Need to set b 6 = /k to maintain unity STF. 9 He ( πif ) N STF Block Diagram b 6 u(n) c, c, g c 3, c 4, g Integrator Resonator Resonator Q v(n) b a a a 3 a 4 a 5 -g b z - x (n) c z z - x (n+) c z - x 3 (n) a a a 3 Summation is usually performed by a single passive switched-capacitor network 0

11 Timing Check x x x5 S Desired Difference Equations Timing x ( n + ) = x () n + b un () c vn () x ( n + ) = c x () n + x () n g x 3 () n x (n) x (n+) x 3 ( n + ) = c 3 x ( n + ) + x 3 () n x (n) x (n+) x 4 ( n + ) = c 4 x 3 () n + x 4 () n g x 5 () n x x 3 (n) x 3 (n+) 5 ( n + ) = c 5 x 4 ( n + ) + x 5 () n yn () = a x () n + a x ( n + ) + a 3 x 3 () n x 4 (n) x 4 (n+) + a 4 x 4 ( n + ) + a 5 x 5 () n + b 6 un () x 5 (n) x 5 (n+) y a () n = ( a + a c )x () n + a x () n + ( a 3 a g + a 4 c 4 )x 3 () n y(n) + a 4 x 4 () n + ( a 5 a 4 g )x 5 () n + b 6 un ( ) vn () = Qyn [ ()] v(n) [ y a = y+ b 6 ( un ( ) un ()) STF a () z = STF() z ( z )NTF() z ] Behavioral Schematic

12 Impulse Response Verification Expected Impulse Response Simulated Impulse Response Time, µs 3 Potential Improvements Clock faster Reduces modulator order. Reduces the size of all capacitors whose values are dictated by noise. Use multi-bit quantization Reduces modulator order. Increases b (after performing voltage scaling), thereby reducing total capacitor area. 4

13 3. -0 Cascade Specifications Parameter Symbol Value Units Bandwidth f B.5 MHz Sampling Frequency f s 0 MHz Signal-to-Noise Ratio SNR 90 db Supply Voltage VDD 5 V Simplified Block Diagram U 5-bit MOD V 5 E V Pipeline ADC 7 ( z - ) V 5 Toolbox Evaluation BW =.5e6; Fs = 0e6; OSR = Fs/(*BW); M = 3; nlev = M+; nb = 7; kpipe = ^nb; Ha = zpk([ ],[0 0],,); amp = [-0:5:-5 -::-6-5:0]; sqnr = zeros(,length(amp)); N = 89; ftest = round(0.6/osr*n); u = M*sin(*pi*ftest/N*[0:N-]); for i = :length(amp) [v junk junk y] = simulatedsm(undbv(amp(i))*u,ha,nlev); v = ds_quantize(kpipe*(v-y),kpipe+); v = v - filter([ - ],, v/kpipe); spec = fft(v.*hann(n))/(m*n/4); sqnr(,i) = calculatesnr(spec(:ceil(n//osr)),ftest); spec = fft(v.*ds_hann(n))/(m*n/4); sqnr(,i) = calculatesnr(spec(:ceil(n//osr)),ftest); end plot(amp,sqnr(,:),'m^','markersize',0,'linewidth',); hold on; plot(amp,sqnr(,:),'m--','linewidth',3); plot(amp,sqnr(,:),'bs','markersize',0,'linewidth',); plot(amp,sqnr(,:),'b-','linewidth',3); figuremagic([-0 0],0,, [0 0],0,); 6

14 0 Ideal SQNR Curve 00 Overall SQNR SQNR (db) db SQNR of MOD Input Amplitude (db) Simulated peak SQNR = 05 db Again, there is a lot of margin, so quantization noise should be small. 7 Gain Mismatch (Capacitor Ratio Error) v = ds_quantize(kpipe*(v-y)*(+gain_mismatch),kpipe+); 0 Peak SQNR (db) Gain Mismatch Need gain error < ~0.5% Not a problem if moderately large capacitors are used. 8

15 Peak SQNR (db) NTF Zero Error (Due to Finite Op-Amp Gain) Ha = zpk([ ]*(-/gain),[0 0],,); Op-Amp Gain (db) Need op-amp gain > 65 db Again, not an unreasonable requirement. 9 Vin Block Diagram [Brooks 997] z z - z DAC DAC 4-b 3-b 3-b 5-b Correction/Cancellation Logic Has bit of overlap at each stage Dout 30

16 An Integrator Stage V ip V refp b0 b0 C P,0 b3 b3 b3 b3 C P,3 C N,3 C V x V in b0 b0 V refn C N, Bandpass Modulator Vin 3 MHz IF 300 khz BW BP Σ ADC LO 4 MHz CLK Want high dynamic range (~90 db) with low power consumption (~50 mw) Desire a continuous-time architecture for its inherent anti-aliasing properties Σ Toolbox indicates we should use a 6 th -order, 8-level modulator Use a FB topology to get a clean STF. 3

17 Simplified Architecture LC Tank Feedback DAC More Resonators and Feedback DACs Flash ADC LO IF V-I Converter LNA+Mixer ADC Front End Bandpass Σ ADC ADC Back End 33 Features of the Architecture The mixer output current is processed by passive components which yield gain without adding noise or distortion, and without consuming power More front-end gain makes back-end noise less important. The first feedback DAC cancels the bulk of the in-band portion of the mixer output, effectively passing only a residue to the ADC backend Large signal-handling capability is not compromised. Only the LNA, Mixer and ADC front end have to deal with the full dynamic range of the signal. 34

18 Choices for the Second Resonator? FLASH A second LC tank would require the least power, but would also need more pins Active-RC: ma for 50 nv/ Hz i.r. noise Switched-C:Estimate >0 ma for same i.r.n. g m -C:Tough to get linearity and stability Use Active-RC Tuning implemented with 8-bit capacitor arrays : tuning range, regardless of process. 35 Choices for the Third Resonator? 3-bit Active-RC:Q and drift are uncertain; might need a fourth resonator Switched-C:Q is high (>00) and drift is low Use Switched-C Consumes ma and has an i.r.n of 300 nv/ Hz. 36

19 SC Resonator 9C 4C φ 7C φ φ φ 3C φ φ φ φ φ φ f = acos = f s 7C Center frequency is set by capacitor ratios LDI structure guarantees pole on unit circle ( A = ). 37 AGC For a 8 dbm input, the mixer output is ma pp, so DAC needs to sink ma Power consumption can be reduced at low signal levels (the usual case) by reducing DAC s full-scale Reduces the FS of the ADC and thus gives the ADC more gain. Lowering DAC s full-scale also reduces the output current noise of the DAC Includes mismatch-induced and dynamic errors as well as thermal noise. Placing a variable-gain element after the LC tank compensates for the reduced signal level and also saves current by minimizing the i.r.n. of the ADC s backend 38

20 Full ADC External LC Tank Tunable Elements f CLK = 3-6 MHz RC Reson. SC Reson. 9-level Flash LO DAC ESL IFIN MHz LNA V-I Converter Full-Scale Adjust To Decimation Filter Achieves NF = 8 db and IIP3 = 0 dbm with P = 50 mw 39 Noise Density (db relative to a 370-ohm resistor) RC Noise vs. AGC 50 khz BW Total LNA/Mixer DAC Mismatch DAC Thermal Full-Scale (dbm) 40 Quantization SC Backend

21 Spectrum of Undecimated Output f CLK = 8 MHz 0 0 dbfs Output f CLK = 8 MHz IF = MHz dbfs/nbw Theoretical PSD Measured PSD NBW = 3.3kHz Frequency (MHz) Spectrum of Decimated Output BW = khz f CLK = 6 MHz Dec-by-48 dbfs/nbw No signal INF = 87 dbfs 8 dbm 03.5 MHz + 5 khz dbfs output INF = -83 dbfs 0 40 NBW=00 Hz Frequency Offset (khz) 4

22 0 0 Spectrum of Decimated Output BW = 5 khz, 4-bit data f CLK = 6 MHz dec-by-900 dbfs/nbw No signal INF = 04 dbfs 7 dbm 03.5 MHz + khz 0.5 dbfs output INF = -95 dbfs 0 NBW= Hz Frequency Offset (khz) 43 Measured SNR f IF = 73 MHz, f LO = 69 MHz, f CLK =3MHz OSR =900 SNR (db) OSR =48 AGC range P in (dbm) 44

23 Summary Design OSR DR (db) Lessons MOD MOD Cascade 8 90 CT BP (LC) High OSR is helpful. Σ can yield a very robust design. FF topology has lower cap. area than FB. Multi-bit quantization is needed to get high SNR at low OSR. Must be watchful of gain mismatch and NTF zero error in a cascaded system. An LC tank enables a power-efficient bandpass Mixer+ADC. The loop filter can use both continuoustime and discrete-time resonators. Many design choices: Σ/Σ, single-loop/multi-loop, single-bit/multi-bit, lowpass/bandpass, discrete-time/ continuous-time, real/quadrature 45