Proposing. An Interpolated Pipeline ADC

Transcription

1 Proposing An Interpolated Pipeline ADC Akira Matsuzawa Tokyo Institute of Technology, Japan Matsuzawa & Okada Lab.

2 Background 38GHz long range mm-wave system

3 Role of long range mm-wave Current Optical fiber Base stations for WiFi and WiMAX Not flexible Future Optical fiber Connect with mm-wave Very flexible

4 38GHz long range mm-wave system realized 1Gbps long range mm-wave systems Current system: 80Mbps!!

5 System configuration Compatible with Gbit Ethernet Hole system is integrated with planar antenna Ethernet Cable Gigabit Ethernet Transceiver Baseband SoC LPF BPF LNA BPF RX ANT RJ-45 Surge Protector PoE Interface LPF LPF PA BPF TX ANT RJ-45 Surge Protector PoE Interface RJ-45

6 Mixed signal BB SoC A mixed signal SoC has been developed to realize 64QAM (1Gbps) with BW of 260MHz. Base band SoC Co-developed with JRC ADC & DAC 90nm CMOS 40M Transistors

7 Developed ADC Developed new 10b ADC to address 64 QAM. Interpolated pipeline scheme No need of high gain OP amps 10b, 320 MSps, 40mW ADC Suitable for low gain and low V DD scaled CMOS M. Miyahara, A. Matsuzawa, VLSI-CS, 2011.

8 BER vs. SNR BER for 64QAM has been reduced to the ideal BER 1.E-02 1.E-03 1.E-04 1.E-05 1.E-06 1.E-07 1.E-08 1.E-09 1.E-10 1.E-11 1.E-12 1.E-13 1.E-14 C/N vs 64QAM_BER on B-B pair C/N [db] ENOB of ADC is increased Measurement ENOB=6.0 (600Mbps version) ENOB=6.25 ENOB=6.5 (1Gbps version 2009) ENOB=6.75 ENOB=7.0 ENOB=7.4 ENOB=8.5 (ADC design target) ENOB=7.15 (1Gbps version 2010)

9 Tokyo Tech. Model Network 9 Ten mm-wave base stations in our campus Tokyo Tech. O-Okayama Campus M1 #8 #3 #9 #4 #1 W8 #5 I6 #6 I1 #2 S3 #10 H #7 100

10 Expand the area to NEC (4km) Challenge for 4km mm-wave communication NEC 4km Tokyo Tech 1km

11 Outline Introduction Interpolation Techniques Circuit Implementation Measurement Results Conclusions 11

12 Conventional Pipelined ADC Conventional pipelined ADC requires accurate MDAC 12

13 Pipelined ADC Conversion V FS Residue 3 Input V MDAC1 4 1 V 2 1 V 4 0 FS FS FS V in V o1 V o1 1 2Vin V 2 Output CODE 1 FS Threshold x2 x2.1 MDAC2 Vo2 V o 3 Vo2 2V o1 0 V x2 o3 MDAC3 1 2Vo2 V FS 13

14 Conventional MDAC High DC gain OpAmp Difficult to realize in scaled technology Closed-loop MDAC leads to lower speed V in C mc V out G 0 G0(dB) 6N GBW NF S 10 D out m bit MDAC Implementation N: Number of bits F s : Sampling freq. 14

15 OpAmp gain and conversion error ( LSB ) 3 2 G N G 3 2 N ( LSB ) G 6N 10 ( db Gain>70dB ) bit ADC U1-VOUT / mv Large error occurs dB gain VOUT / mv VOUT / mv Time/mSecs 200uSecs/div

16 Recent Works Digital compensation technique [1, 2] Capacitor mismatch, gain error and opamp nonlinearity can be corrected Simple analog circuit design Foreground compensation PVT variation degrade the performance Long compensation time Increase of test cost [1] B. Murmann and B. E. Boser, Dec., [2] A. Verma and B. Razavi, Nov.,

17 Proposed ADC Target : 10bit, F s > 300 MS/s Interpolation and pipelined operation Moderate relative gain G/G < 5% for 10bit Open-loop amplifiers can be used No need of linearity compensation Insensitive to settling time High speed Low power 17

18 Interpolation Architecture 1a V oa V out Interpolator CMP V oa 1b V ob CMP V in V ob 18

19 Interpolation Architecture 1a V oa V out Interpolator CMP V oa V oa : V ob = 1 : 1 1b V ob CMP V in 1a 1b R R CMP Interpolator example [3,4] V ob [3]A. Matsuzawa, et al. Feb [4]C. Mangelthdolf, et al., Feb

20 Interpolation Architecture 1a V oa V out V oa : V ob = 3 : 1 Interpolator CMP V oa V oa : V ob = 2 : 2 1b V ob V oa : V ob = 1 : 3 CMP V in 1a 1b 3R 1R CMP Interpolator example V ob Conversion error is not occurred by changing gain 20

21 Interpolated Pipeline ADC Structure Interpolation technique is used for 2-4 th stage. Each stage has an 1-bit redundancy. 1 st stage 2 nd stage 3 rd stage 4 th stage Pipeline Stage Pipeline Stage 21

22 Interpolation methods Static current Good linearity Imbalance settling No static current C p causes nonlinearity No static current Good linearity Heavy load 1a 1a C u 1a C ua1 C ub1 1b Ex. 3bit C p C p 2a 1:8 V in 2a 2a 2:6 C p 2b 2b 2b 3:5 1b Resistive (Series) [3,4] 1b Capacitive (Series) C u C uan C ubn Capacitive (Weighted) 8:1 Total:36Cu 22

23 Proposed Weight Controlled Capacitor Array Sub-ADC controls the capacitor weight. Load capacitance is reduced from 36C u to 16C u (3bit). 1a V oa 2a 1a V xa 2a 16C u 16C u 1b V ob 2b 1b V xb 2b Total:16Cu 23

24 Weight Controlled Capacitor Array Offset voltage can be cancelled in interpolation phase V x m m n G a V V G V V in ra n m n b in rb V V oa ob V ' V ' oa ob G G a b G G a b V V in in V V V V ra rb off_a off_b V V off_a off_b G a, G b : Gain of A 1a and A 1b V oa, V ob : Output voltage V off_a, V off_b : Offset voltage V ra, V rb : Reference voltage m, n : Capacitor weight 24

25 Interpolated Output V oa V xa 1bit redundancy V x V xa V xb V oa V ob V xb CMP2 V ob 1 37 mc nc mc nc V oa V ob V in V xa 25

26 Sub-ADC Structure Gate-width-weighted interpolation comparators with capacitive offset calibration is used. Offset voltage < 2 mv () 1a CLK DD OUTP W a W b W a W b OUTN V INPa V INPb V INNa V INNb 1b 2nd 1 st stage Sense 2 nd stage Latch [1] V. Giannini, ISSCC 2008 [5] Y. Asada, A-SSCC

27 Requirements for An Amplifier Absolute Gain error No error Offset voltage DNL error Offset voltage < 1LSB Offset voltage can be negrected by output offset cancel technique. Gain mismatch DNL error Linearity DNL and INL error 27

28 Amplifier : Schematic 1st stage amplifier require good linearity =>CMOS input with source degenerations Gain mismatch < 2.1%(3) 28

29 Amplifiers : Simulation results V out a 1 V in a 3 V 3 in 1st stage a 3 /a 1 < 1.3 2nd stage a 3 /a 1 <

30 Gain matching requirement Gain mismatch of 1st stage amplifiers < 2.1%(3s) ENOB [bit] G-G G+G G/G (%) 30

31 Linearity Requirement ENOB [bit] st stage a 3 /a 1 < 1.3, 2nd stage a 3 /a 1 < in a3/a1 V out a 1 V in a 3 V 31

32 Chip photo 90 nm 10M1P CMOS technology Chip area of 0.46mm m Timing generator & Clock lines 415 m 5 th Logic 4 th stage 3 rd stage 2 nd stage 1 st stage 32

33 DNL, INL This periodical error is due to bad layout, not essential issue. DNL [LSB] INL [LSB] OUTPUT CODE OUTPUT CODE DNL +0.9/-0.6 INL +1.4/

34 Sampling Frequency vs. SNDR Input Frequency = 1 MHz 34

35 Input Frequency vs. SNDR Sampling Frequency = 320 MS/s 35

36 Performance summary This Work [2] [6] [7] Resolution (bit) F sample (MS/s) V DD (V) Power (mw) ENOB peak (bit) FoM Fs / FoM ERBW (pj/c.-s) 0.35 / /0.44 Technology (nm) Active Area (mm 2 ) Amplifier type Open Closed Closed Closed Linearity Compensation No Yes No Yes [2] A. Verma and B. Razavi, IEEE J. Solid-State Circuits, vol. 44, Nov., [6] S. Lee, Y. Jeon, K. Kim, J. Kwon, J. Kim, J. Moon, and W. Lee, ISSCC, [7] H. Chen, W. Shen, W. Cheng, and H. Chen, A-SSCC,

37 Conclusions An interpolated pipelined ADC using open-loop amplifier has been proposed. Interpolation architecture G/G < 5% for 10bit Using simple open-loop amplifiers enables high speed operation No need of a linearity compensation Weight Controlled Capacitor Array Load capacitance is reduced from 36C u to 16C u Offset voltage of the amplifier can be cancelled 10bit, 320MS/s, 40 mw ADC has been realized 37

38 Future Prospect Issue: Need twice larger circuits Same capacitance as for the conventional pipeline ADC can be used by modifying circuits. Area and power can be reduced, since lower bandwidth is acceptable. Still need the pipelined ADC? SAR ADC: lowest FoM, but low f s and low resolution. SAR-Pipeline: higher resolution, but lower f s due to multi step conversions. Interleaving: effective for low resolution ADC, but need totally large capacitance.