A 0.55 V 7-bit 160 MS/s Interpolated Pipeline ADC Using Dynamic Amplifiers

Transcription

1 A 0.55 V 7-bit 160 MS/s Interpolated Pipeline ADC Using Dynamic Amplifiers James Lin, Daehwa Paik, Seungjong Lee, Masaya Miyahara, and Akira Matsuzawa Tokyo Institute of Technology, Japan Matsuzawa & Okada Laḃ

2 Outline Motivation Prior Arts Circuit Design Measurement Results Conclusion 2

3 Supply voltage (V) Motivation Ultra-low-voltage (ULV) operation Immediate power saving potential Explore new circuit techniques for future technology [1] Key Challenges Reduced SNR Reduced headroom Reduced gain Increased mismatch Year [1] ITRS,

4 Outline Motivation Prior Arts Circuit Design Measurement Results Conclusion 4

5 Prior Arts Successfully demonstrated very good energy efficiency but all suffer in speed Body-Driven [2] Sub-threshold [3] SAR-based [4],[5] V in CLK V in CDAC V biasn V in SAR Logic [2] S. Chatterjee et al., JSSC [4] A. Shikata et al., JSSC [3] D. C. Daly et al., JSSC [5] P. Harpe et al., ISSCC

6 Outline Motivation Prior Arts Circuit Design Measurement Results Conclusion 6

7 Circuit Techniques Overview ADC architecture Dynamic amplifier Interpolation technique Sub-ADC structure Self-clocking scheme 7

8 Dynamic Amplifier Minimally stacked amplifier achieves high speed at low supply voltage [6] V outp CMD V outn CLK Pre-charge Phase Amplification Phase V outp V inp V inn Voltage Vout CLK V oc V outn Vout CLK CMD: Common-mode voltage detector Time P d = fcv DD 2 [6] J. Lin, et al., ISCAS

9 ADC Block Diagram Ultra-low-voltage interpolated pipeline ADC Dynamic Amplifiers STAGE1 STAGE2 PS-RDAC STAGE3 V in Sample & CDAC A1a IntCaps A2a CMP1 CMP2 CMP3 V ref Sample & CDAC A1b IntCaps A2b D 1st (3b) D 2nd (2b+1b) Correction Logic D 3rd (2b) 7b 9

10 Interpolation Technique Interpolation shifts the gain requirement: absolute relative gain accuracy [7], [8] V oa V out V oa :V ob = 3:1 V oa :V ob = 1:1 V oa :V ob = 1:3 V in V oa V out V in V ob V ob Different absolute gain, same decision levels! [7] A. Matsuzawa, et al., ISSCC [8] C. Mangelsdorf, et al., ISSCC

11 Interpolated Pipeline Same path for both signal and references Conventional Interpolation V refp 4X V refp Any Gain V in 4X V in V refn V refn Fixed references Embedded references 11

12 High-Speed Dynamic Amplifier Dynamic amplifier with an inverter-based CMD for high-speed operation Inverter-based CMD from PS-RDAC from PS-RDAC CLK CLK V out V inp V inn V xn V xp IntCaps IntCaps Gain = a(v DD -V oc )/V eff, 1<a<2 12

13 Next Stage Pseudo-Static RDAC Pseudo-static RDAC is proposed to calibrate the common-mode voltage during startup V PS-RDAC CMP + Counter V RDAC A1a A1b V xa V xb V RDAC IntCaps IntCaps V oa V oc = (V oa +V ob )/2 V ob V COM Target (V com ) AMP V oc CMP Interpolate Time 13

14 Capacitive Interpolation [9] Absolute gain relative gain accuracy Interpolation is controlled by the sub-adc from PS-RDAC from PS-RDAC V ia A1a V xa to A2a V ia A1a V xa to A2a V ib A1b V xb to A2b V ib A1b V xb to A2b Sampling Phase Interpolation Phase [9] M. Miyahara, et al., VLSI Circuits

15 Sub-ADC Gate-weighted interpolation comparators with a time-based offset calibration A1a V DD CLK V DD Timing cal. V DD D out - + V DD CLK P CLK N A1b W a W b W a W b V inpa V inpb V inna V innb Gate-weighted interpolation 3-bit sub-adc Dynamic Comparator [10] Y. Asada, et al., A-SSCC [11] M. Miyahara, et al. A-SSCC

16 Self-Clocking Internal signals trigger the subsequent stages to maximize speed performance [12], [13] Generated CLK2 AMP CMP Hold Reset AMP1 AMP1's Trigger 1 Start CMP2 Start CMP2 CMP2 CMP2's Trigger Output of STAGE2 2 Start AMP2 Generated CLK3 AMP2 Reset STAGE3 Reset STAGE3 AMP2's Trigger 3 Start CMP3 Time [12] J. Yang, et al., JSSC [13] R. Kapusta, et al., ISSCC

17 Outline Motivation Prior Arts Circuit Design Measurement Results Conclusion 17

18 INL (LSB) DNL (LSB) Measured DNL and INL Startup calibration: timing cal. + common-mode cal Uncalibrated Timing Cal. V cm Cal / -1 LSB +1.7/ LSB / LSB / -3.1 LSB / LSB / LSB Digital code 18

19 SFDR and SNDR (db) SFDR and SNDR (db) Measured SFDR and SNDR >38 db of SNDR is measured up to 160 MS/s with an ERBW >80 MHz Consumes 2.43 mw at 160 MS/s, FoM=240 fj/c.-s. SFDR & SNDR vs. f s SFDR & SNDR vs. f in f in = 1 MHz SFDR SNDR Conversion rate (MS/s) f s = 160 MS/s SFDR SNDR Input frequency (MHz) 19

20 Power consumption (mw) Clock-Scalable Power Performance Dynamic amplifier enables clockscalability in ADC s power performance Conversion rate (MS/s) 20

21 STAGE1 STAGE2 STAGE3 Chip Photo Prototype ADC is fabricated in 90 nm CMOS with the low threshold and deep N-well options Occupied area is 0.25 mm mm DEC 320 mm 21

22 Performance Comparison Fastest ULV ADC compared to other stateof-the-art ULV high-speed ADCs [14] [15] [16] [17] This work Architecture Flash Pipeline Pipeline Pipeline Pipeline Resolution (bit) Supply voltage (V) /0.5* f s (MS/s) Power (mw) ENOB (bit) FoM (fj/c.-s.) Technology (nm) Active area (mm 2 ) [14] J. E. Proesel, et al., CICC [16] Y. J. Kim, et al., CICC *Analog V DD = 0.55 V, Digital V DD = 0.5 V [15] J. Shen, et al., JSSC [17] S. Lee, et al., JSSC

23 Conversion rate (MS/s) Summary of ULV Pipeline ADC Proposed ADC demonstrates the feasibility of ULV high-speed analog circuit design This work CICC 2008 [14] JSSC 2008 [15] A-SSCC 2006 V DD =0.6 V V DD =0.55 V V DD =0.5 V V DD =0.4 V JSSC 2009 [3] CICC 2007 [16] JSSC 2012 [17] JSSC 2012 [4] ISSCC 2013 [5] JSSC SNDR (db) 23

24 Outline Motivation Prior Arts Circuit Design Measurement Results Conclusion 24

25 Conclusion 0.55 V, 7-bit, 160 MS/s, 2.43 mw pipeline ADC is realized using dynamic amplifiers and interpolation Demonstrates the feasibility of ultra-lowvoltage high-speed analog circuit design Proposed techniques are suitable for ULV and nominal-voltage high-speed circuits 25

26 Acknowledgement This work was partially supported by NEDO, Huawei, Berkeley Design Automation for the use of the Analog FastSPICE (AFS) Platform, and VDEC in collaboration with Cadence Design Systems, Inc. 26

27 Thank you for your interest! James Lin, 27