Workshop ESSCIRC. Low-Power Data Acquisition System For Very Small Signals At Low Frequencies With12-Bit- SAR-ADC. 17. September 2010.
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1 Workshop ESSCIRC Low-Power Data Acquisition System For Very Small Signals At Low Frequencies With12-Bit- SAR-ADC 17. September 2010 Christof Dohmen
2 Outline System Overview Analog-Front-End Chopper-Amplifier Anti-Aliasing-Filter Measurement Results Charge Scaling SAR-ADC ADC-Concept Measurement Results System Summary 2
3 Data Acquisition System Overview Purpose: sensor frontend of the Ultrasponder-implant Problems with biomedical signals: - at very low frequencies 1/f noise dominates in amplifiers and overlays very small signals - dc-offsets in amplifiers at very high gain distort or even destroy these signals living tissue electrodes low frequency amplifier anti-aliasing low pass 12-bit SAR- ADC digital IO 3
4 Solution: use a chopping amplifier non-overlapping pulse clock, f CH =4kHz f C,LP =70Hz, 80dB/dec V in A=40dB GBW=10MHz V out Input Signal below expected 1/fnoise floor modulation of input signal up to higher frequency by a square-wave chopping amplification => high bandwidth required due to squarewave spectrum demodulation by the same square-wave output signal contains the amplified input and undesired signals at high frequencies => low-pass filtering required! V V V V V f f f f f 4
5 Realization of Chopper-Elements Modulator / Demodulator phi 1 TMG TMG phi 2 phi 2 TMG phi 1 TMG Non-overlapping clock generator clk in phi 1 phi 2 5
6 Active LP- Filter Fully Differential Multiple Feedback Anti-Aliasing-Low-Pass-Filter Requirements - 20dB gain in pass-region - cut-off-frequency f C,3dB =70Hz => large external passive elements required - filter suppression of 72.24dB at least required for 12 bit resolution in ADC 36.25MΩ 7.5MΩ noisy signal from chopperamplifier 3.57MΩ 10MΩ 27pF 7.5MΩ 10.7MΩ 56pF V in 265pF A=10dB 500pF A=10dB V out 3.57MΩ 10MΩ 27pF 7.5MΩ 10.7MΩ 56pF cap. load of ADCinput 36.25MΩ 7.5MΩ 6
7 Anti-Aliasing-Filter: frequency plot from lab-results Verification of parameters by measurement - 20dB Gain in pass-region - cut-off-frequency f C,3dB =70Hz - cut-off-steepness 80dB/decade due to 4 th filter order Gain [db] SE Gain [db] Trend Logarithmisch (Trend) y = -34,608Ln(x) + 166,44-70 Freq. [Hz] ext. filter-elements on testboard 7
8 Chopping in time domain: lab results 1) pulse-clock source 2) chopped & amplified sine-signal 3) demodulated amplified sine-signal 4) filtered amplified sine-signal 8
9 Outline System Overview Analog-Front-End Chopper-Amplifier Anti-Aliasing-Filter Measurement Results Charge Scaling SAR-ADC ADC-Concept Measurement Results System Summary 9
10 Overview of ADC-Concepts: Speed vs Resolution Targeted: 12bit, f S <50kS/s, V ref =1.5V, f clk =1MHz - Very fast (one step conversion) - Low resolution - High power consumption - Still one-step converter - Improvements to save space and power, to increase resolution but also maintaining speed => fast low power ADC chargescaling ADC optimum properties for ultra low power at medium speed/medium resolution - Very high resolution at low noise due to oversampling (fast clock required!) - low power ADC for high resolution - can be very accurate but very slow Source: Sansen, Analog Design Essentials, p
11 Successive-Approximation-Register-ADC (SAR) General SAR-structure V in f S S&H output B f S V in V DAC =B*V ref General SAR-algorithm Example: find 0.4 V ref DAC SAR-logic + Comp - b 0 b 1 b N-1 V ref f clk =N*f S here the DAC is realized as a chargescaling capacitorarray advantage: DAC also acts as S&H, very low power Source: Johns/Martin, Analog Integrated Circuit Design axis normalized to V ref /2 11
12 SAR-ADC with Charge Scaling DAC (1) 1. Sample Mode MSB 2. Hold Mode MSB Source: Sansen, Analog Design Essentials 12
13 SAR-ADC with Charge Scaling DAC (2) 3. Bit Cycling MSB V comp Cycling principle: If V x >V ref /2 i : b i = 1 leave C bi to V ref if V x <V ref /2 i : b i = 0 leave C bi to GND Source: Sansen, Analog Design Essentials V in =0V results in B=
14 SAR-ADC with Charge Scaling DAC (3) V in =1.8V results in B= V in =1.0V results in B=
15 Design Improvements of the ADC for Ultrasponder V refp V refn V in,p Main-DAC V refp V refn V in,p Sub-DAC regenerative amplifiers and latch in comparator: reduces power use topplates as floating nodes: less parasitics C S differential input: better CMRR size of single capacitor not too small due to mismatch V in,n V refn V refp AZ Main-DAC auto-zeroing: increases accuracy V in,n V refn V refp Sub-DAC C S separation into 2 nearly identical Main- and Sub- DACs: better accuracy 6 bit 6 bit Sleep SAR control Digital Output Comp. out clk start 15
16 Design of the Comparator with Autozero - single-stage preamplifiers increase V in -sensitivity to 180uV (= V LSB settling-time t settle < 500ns (maximum system-clock f clk =1MHz) purge purge purge latch V in preamp AZ preamp AZ preamp AZ V out,com p purge purge purge sleep reset A 4-step autozero-cycle is preceding every conversion: 1. Each preamp is shorted at its input. A short closing of the purge-switches discharges the autozero-capacitors 2/3/4. On opening the AZ-switches from back to front the autozerocapacitors store offset from preamplifiers 16
17 ADC Lab-Results: Time-Domain-Signal Test signal for ADC-performance-check: clean sine (negligible distortion & noise) perfect full-scale amplitude long conversion period to acquire enough data time domain signal (blue) with Sine Wave Fitting (red) from 512kSamples, f S =20kS/s 17
18 ADC Lab-Results: FFT Performance parameters can be calculated from the FFT of the conversion data: Calculated parameters: Frq.: 39,9399Hz A: 0,99976 SINAD: 51,2632 db ENOB: 9,1009 SNR: 51,2905 db THD: -53,2483 db SFDR: 53, FFT (512k Samples, 20kS/s) 18
19 ADC Lab-Results: Differential Nonlinearity (DNL) DNL: deviation in step sizes differing from ideal +1 LSB step here: 6 LSBs costs 3 bits of resolution undesirable Reason: mandatory metal-fillstructures on chip increases capacitance of the single elements (C nom =104fF) the scaling capacitor of the Sub-DAC is too small DNL of the ADC (512k Samples) single capacitor element with fill structure 19
20 ADC Lab-Results: Integral Nonlinearity (INL) INL: deviation from the ideal step value here: 6 LSBs in either direction costs 4 bits of resolution possibly worse than in reality due to measurement errors INL of the ADC (512k Samples) 20
21 ADC-Performance Comparison: Figure of Merit (FOM) Relation of power, resolution and input frequency: Source: IEEE, ISSCC 2006, session 12.5 FOM for the Ultrasponder-ADC: 21
22 Summary: Ultrasponder Data Acquisition Chip - process technology 130nm 22
23 Performance summary 23
24 Questions?
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