Analog to Digital in a Few Simple. Steps. A Guide to Designing with SAR ADCs. Senior Applications Engineer Texas Instruments Inc

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1 Analog to Digital in a Few Simple Steps A Guide to Designing with SAR ADCs Miro Oljaca Senior Applications Engineer Texas Instruments Inc Tucson, Arizona USA moljaca@ti.com Miro Oljaca Feb 2010

2 SAR ADC s Block Diagram Sample & Hold Ampliier Sampling Signal

3 Equivalent Input Circuit SAR ADC Sample & Hold Ampliier V IN S1 S2 R S1 + C SH V SH0 From the Data Sheet or ADS8326: - Sampling capacitor is 48pF - Sampling switch resistance is 50Ω

4 Sample and Conversion Process S1 S2 V IN R S1 V IN R S1 S1 S2 + V SH0 C SH + V SH0 C SH

5 Sample and Conversion Timing

6 Voltage Ripple on The Input o ADC Sampling Signal V IN S1 R S1 C SH Analog Input Signal

7 V IN Voltage Across Sampling Capacitor V CSH V IN S1 R S1 t=0 C SH V SH0 V CSH (t) t 0 t AQ Time V CSH ( t) = V CSH ( t0) + [ V IN V CSH ( t0)] (1 e t τ ) τ S C SH R = 1 1/2 LSB

8 Settling Time as a Function o Time Constant V V ( t AQ) 1 IN CSH 2 LSB V CSH (t AQ ) is voltage across the C SH, at the end o the sampling period t AQ is acquisition time, the time rom the beginning o the sampling period (t 0 ) to the end o the sampling period 1 2 FSR = N+ 1 LSB 2 (LSB = Least Signiicant Bit, FSR is the ull-scale range o the N-Bit converter) t AQ k 1 τ k1 = ( N+ 1) ln(2)

9 Time-Constant-Multiplier (k 1 ) or SAR ADC k1 ADC time-constant-multiplie Resolution 1/2 LSB accuracy, 1/2 N *note using worst case values: V IN = ull-scale voltage or 2 N, V SH0 = 0V

10 SAR ADC With Input RC Filter SAR ADC V CSH R F V IN R S1 S1 S2 C F + C SH V SH0 R F C F t AQ ( N + 1) ln(2)

11 ADC Input With Proper RC Filter Start Acquisition End Acquisition

12 ADC Input With Wrong RC Filter Start Acquisition End Acquisition

13 Op Amp Driving RC Filter - R O R F + V OA C F

14 Modiied Open-Loop Voltage Gain PX, G PX -40dB/Dec ZX, G ZX -20dB/Dec U -20dB/Dec C k 10k 100k 1M 10M Frequency (Hz) Voltage Gain (db)

15 Added Pole and Zero Frequency o added pole Frequency o added zero PX ZX = 2 π = 2π ( R 1 R F O 1 + R C F F Gain o added pole G PX = 20 log PX U Gain o added zero G ZX = G PX 40 log ) C F ZX PX

16 Good Design Guideline db G or ZX U ZX C ZX U C O F ZX PX R R > db G or ZX U ZX C ZX U C

17 Final Circuit OP AMP - R O R F V IN + C F SAR ADC V CSH S1 S2 R S1 + C SH V SH0

18 Minimum Acquisition Time and Op Amp s GBW Calculate time-constant multiplier k = ( N+ 1) ln(2) Determine minimum time-constant τ t AQ k Calculate requency o added zero ZX π τ = 2 1 Find Unity Gain Bandwidth GBW =4 ZX

19 Minimum Acquisition Time or Dierent Op Amps 12 Bit 16 Bit GBW Z τ t AQ t AQ (MHz) (MHz) (ns) (ns) (ns) INA155 Medium Speed, Precision INA ,157 5,672 8,881 INA128 High Precision, 120dB CMRR ,400 3,757 INA331 High Bandwidth, Single Supply OPA340 CMOS, % THD+N OPA V, High CMRR, SHDN OPA2613 Dual VFB, Low Noise OPA627 Ultra-Low THD+N, Wide BW OPA381 Precision High-Speed Amp OPA727 CMOS, e-trim, Low Noise OPA228 Precision, Low Noise, G OPA350 Precision ADC Driver OPAy365 High-Speed, Zero-Crossover OPA2889 Dual, Low Power, VFB OPA211 36V, Bipolar Precision THS4281 Very Low Power RRIO OPA358 CMOS, 3V Operation, SC

20 Not Good Design Guideline or G C ZX ZX 0 db Stability Problem

21 Ater selecting ADC and OpAmp Determine C F 20 C 60 SH C F C SH Calculate R F R F 1 = 2π C F ZX Veriy value R F R F R O 9 Calculate requency o added pole PX = 2π ( R F 1 + R O ) C F Keep added pole and zero less then decade a part 1 10 PX ZX

22 Design by Example For ADS8326 we have t AQ =750ns, C SH =48pF and N=16. 1 k = ( N+ 1) ln(2) = (16 + 1) ln(2) = t AQ 750ns τ = = ns k = = = 2. ZX 2π τ 2π 63.65ns MHz 2 GBW 4 ZX = MHz = 10MHz 3 20 C SH C 960pF C F F 60 C SH 2.9 nf C 20 F = pf C nf F 60 48pF 4 R F = 1 1 = = 2π C 2π 1.2 nf 2.5 MHz 53 F ZX Ω

23 ADC and DAC Functions VIN CODE ADC : CODE = V IN VREF CODE VOUT DAC : V OUT = CODE VREF V 2 N REF V 2 REF N

24 Noise and ENOB o ADC Signal-to-Noise Ratio and Distortion SNR SINAD ( db) = 20log 10 + THD 10 Eective Number o Bits ENOB = SINAD dB ENOB= ( SNR, THD )

25 Noise Sources in SAR ADCs Wideband ADC internal circuits noise Noise due to aperture jitter Quantization noise Transition or DNL noise Analog input buer circuit noise Reerence input voltage noise

26 V IN 0V or V IN FSR Measuring Reerence Input Noise REF5040 REFIN - V OUT CS + ADS8326 CLK SDO

27 Noise Contribution ADC + REF Noise REF Noise ADC Internal Noise Input Voltage [V] 0 Noise [uvrms]

28 Quantization o Reerence Noise Low noise analog input o 0.09V Source o noise is ADC s internal noise. Measured noise is 27µV RMS or 179µV PP Low noise analog input o 4.02V Source o noise is ADC s internal noise and reerence input noise. Measured noise is 43µV RMS or 287µV PP

29 Sources o the Noise in REF50xx 1.2V V OUT Noise Source

30 Low Pass Filter Shapes the Output Noise Spectrum RMS 1/ Region Broadband Region Low pass ilter Source: Art Kay; OpAmp Noise 2006

31 +5V C IN 10µF REF50xx Noise Test Circuit Variable NC 1 8 NC V IN TEMP GND REF NC V OUT TRIM V C OUT 1µF - 50µF

32 Capacitor Equivalent Circuit ESL ESR IR C C Capacitance ESR Equivalent Series Resistance ESL Equivalent Series Inductance IR Insulation Resistance

33 Capacitive Load with ESR V CC P = 2π ( R O 1 + ESR) C R O ESR C L Z 1 = 2π ESR C L L

34 Measured Noise or dierent BW and LP Filters Measurement Bandwith Noise 22kHz 30kHz 80kHz >500kHz Units LP-5P LP-3P LP-3P GND µv RMS 1µF ,017 µv RMS 2.2µF (cer) µv RMS 10µF µv RMS 10µF (cer) µv RMS 20µF (cer) µv RMS 47µF µv RMS The capacitor on the output o REF50xx together with internal components will create Low Pass ilters.

35 Filtering Internal Bandgap Reerence 1.2V 10k V OUT TRIM 1k

36 Measured Noise with Added Bandgap Filter Measurement Bandwith Noise 22kHz 30kHz 80kHz >500kHz Units LP-5P LP-3P LP-3P GND µv RMS 2.2µF (cer) µv RMS 2.2µF+1µF µv RMS 10µF µv RMS 10µF+1µF µv RMS 20µF (cer) µv RMS 20µF+1µF µv RMS Adding 1µF capacitor on the TRIM pin will reduce noise ~2.5x

37 REF5040 Output with 10µF and <10mΩ ESR Capacitor BW=80kHz noise=16.5µv RMS BW=65kHz noise=138µv PP

38 Added RC ilter on the Output 5V - 10k 1.2V + + ESR 10uF REF uF Adding RC ilter reduce noise rom xx to xx

39 REF5040 Output with added RC Filter BW=80kHz noise=2.2µv RMS BW=65kHz noise=15µv PP

40 VIN+ VREF SAR ADC Capacitive Conversion Network - Comparator ADS83xx + C Capacitive Conversion Network C C/2 1 C/2 2 C/2 3 C/2 N C/2 N S0 S1 S2 S3 SN Scaling

41 REF Input With Proper Buer Start Conversion End Conversion

42 REF Input With Wrong Buer Start Conversion End Conversion

43 Voltage-reerence circuit with added buer and output ilter 5V OPA V k ESR 10uF - + 5V ESR REF uF 10uF BW=80kHz noise=4.5µv RMS BW=65kHz noise=42µv PP

44 Design by Example 1. Use REF5040 and 10µF with 0.5Ω<ESR<1.5Ω (V n =39µV RMS /261µV PP ) 2. Add 1µF on the TRIM pin (V n =16µV RMS /138µV PP ) 3. Use additional RC Filter (10kΩ/10µF) (V n =2.2µV RMS /15µV PP ) 4. Buer output with OPA350 and 10µF with 0.2Ω<ESR (V n =4.5µV RMS /42µV PP )

45 Reerences 1) Green, Tim, Operational Ampliier Stability, Part 6 o 15: Capacitance-Load Stability: RISO, High Gain & CF, Noise Gain, Analog Zone, ) Miro Oljaca, and Baker Bonnie, Start with the right op amp when driving SAR ADCs, EDN, October 16, 2008, 3) Downs, Rick, and Miro Oljaca, Designing SAR ADC Drive Circuitry, Part I: A Detailed Look at SAR ADC Operation, Analog Zone, ) Downs, Rick, and Miro Oljaca, Designing SAR ADC Drive Circuitry, Part II: Input Behavior o SAR ADCs, Analog Zone, ) Downs, Rick, and Miro Oljaca, Designing SAR ADC Drive Circuitry, Part III: Designing The Optimal Input Drive Circuit For SAR ADCs, Analog Zone, ) Baker, Bonnie, and Miro Oljaca, External components improve SAR-ADC accuracy, EDN, June 7, 2007, 7) Miroslav Oljaca, Understand the Limits o Your ADC Input Circuit Beore Starting Conversions, Analog Zone, 2004.

46 Reerences Cont. 8) Art Kay, Analysis and Measurement o Intrinsic Noise in Op Amp Circuits Part 1 to 8, Analog Zone / En-Genius, ) Oljaca, M., Klein, W., Converter voltage reerence perormance improvement secrets, Instrumentation & Measurement Magazine, IEEE, Volume: 12 Issue: 5 October 2009, Page(s): 21-27, 10) Bonnie Baker, and Miro Oljaca, "How the voltage reerence aects ADC perormance, Part 3 o 3", Analog Applications Journal, Texas Instruments, Q4Y09, ) Miro Oljaca, and Bonnie Baker, "How the Voltage Reerence Aects your Perormance: Part 2 o 3", Analog Applications Journal, Texas Instruments, Q3Y09, July ) Bonnie Baker, and Miro Oljaca, How the Voltage-reerence aects Your Perormance: Part 1 o 3,, Analog Applications Journal, Texas Instruments, Q2Y09, ) Miro Oljaca, Converter Voltage Reerence Perormance Improvement Secrets Embedded Systems Conerence, Silicon Valley, 2008

47 Questions? Thanks or Your Interest in From Analog to Digital: Design In a Few Simple Steps Miro Oljaca Senior Applications Engineer Texas Instruments Inc Tucson, Arizona USA moljaca@ti.com

48 Part No. Package Type Product Description

SAR (successive-approximation-register) ADCs

SAR (successive-approximation-register) ADCs By Miro Oljaca and Bonnie C Baker Texas Instruments Start with the right op amp when driving SAR ADCs Using the right operational amplifier in front of your data converter will give you good performance.