Analog-to-Digital i Converters

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1 CSE 577 Spring 2011 Analog-to-Digital i Converters Jaehyun Lim, Kyusun Choi Department t of Computer Science and Engineering i The Pennsylvania State University

2 ADC Glossary DNL (differential nonlinearity) - measure of the maximum deviation from the ideal step size of 1 LSB

3 ADC Glossary INL (integral nonlinearity) - deviation of the entire transfer function from the ideal function

4 ADC Glossary Offset Error - difference between the ideal LSB transition to the actual transition point

5 ADC Glossary Gain Error - how well the slope of the actual transfer function matches the slope of the ideal transfer function

6 ADC Glossary Resolution - number of discrete values it can produce Monotonic - digital output code always increases as the ADC analog input increases Full scale - voltage range ADC can accept Aliasing - due to unwanted signals beyond the Nyquist limit - to prevent, all undesired signals must be filtered

7 ADC Glossary SINAD (signal-to-noise and distortion) - RMS value of the output t signal to the RMS value of all of the other spectral components below half the clock frequency ENOB (effective number of bits) - dynamic performance of an ADC at a specific input frequency and sampling rate ENOB = SINAD

8 High Speed ADC Architecture Flash ADC - highest speed - large # of comparators - large size - large power consumption - 8-bit maximum resolution

9 High Speed ADC Architecture Two-Step Flash ADC - SHA - D/A converter - subtractor - coarse flash ADC (MSB) - find flash ADC (LSB) - reduce # of comparators 2 N -1 2(2 N/2-1)

10 High Speed ADC Architecture Pipelined ADC - multi-stage conversion - high speed - acceptable power - each stage has SHA, ADC, DAC, subtractor, Amp - different conversion step concurrently

11 High Speed ADC Architecture Folding ADC - no SHA (flash) - reduce # of comparators (two step flash) - small area, high speed - rounding problem

12 High Speed ADC Architecture Time-Interleaved ADC - multiple ADCs in parallel high speed - offset/gain mismatch - phase skew

13 And More ADC Architectures Algorithmic ADC - low power, small size, slow Integrating-Type ADC - high accuracy, simple architecture, very slow Successive Approximation ADC R&C / C&R Type ADC Interpolating ADC

14 Design Consideration Flash ADC Large Input Capacitance parallel structure of 2 N -1 comparators limits speed performance large size buffer Bubble / Sparkle no SHA, comparator mismatch error in thermometer code solution : 3-input NAND

15 Design Consideration Flash ADC Metastability input to ADC comparator reference indeterminate output error solution : latch pipelining (extra gain) gray encoding (no signal split)

16 Design Consideration Flash ADC Clock Distribution and Timing clock travels long distance on a large ADC chip different delay, different loading Kickback Noise disturbs reference

17 Design Consideration Two-Step Flash ADC Subtractor Gain without gain stage output of subtractor = 1-LSB of coarse ADC difficult comparator design (offset < 1-LSB of fine ADC) with gain stage delay mismatch between subtractor output and fine ADC input full scale missing code / nonmonotonicity

18 Design Consideration Two-Step Flash ADC Nonlinearity residue SHA analog input ΔV V in t 1 t 2 residue including errors - gain mismatch - DNL, INL -offset -... t level sensed by subtractor V in level digitized by coarse ADC

19 Design Consideration Pipelined Flash ADC MDAC (Multiplying D/A Converter) - performs subtractor, gain amplifier, S/H, and DAC

20 Design Consideration Pipelined Flash ADC MDAC Operation removes offset V x Q i = (2 N -1) C V in + C V in = 2 N C V in

21 Design Consideration Pipelined Flash ADC MDAC Operation Q = N C DVref f 2 + C V o from Q in =Q f, V o = 2N(V in -DV ref )

22 Design Consideration Folding ADC Rounding Problem - only linear at zero-crossings limits resolution to ~10 bits

23 Design Consideration Folding ADC Multiple Folds

24 Two-Step Flash ADC Implementation SHA 4-bit Coarse ADC 3-bit Fine ADC Resistor-String DAC Voltage Subtractor Amplifier Registers

25 Two-Step Flash ADC Implementation Coarse ADC Bubble Correction Fat-Tree Encoder

26 Two-Step Flash ADC Implementation Coarse ADC

27 Two-Step Flash ADC Implementation Resistor-String DAC voltage scaling DAC simple fast small (under 8-bit) resistor mismatching

28 Two-Step Flash ADC Implementation Resistor-String DAC

29 SHA Two-Step Flash ADC Implementation input output

30 Two-Step Flash ADC Implementation Voltage Subtractor V2 V1 8 x (V1-V2)

31 Two-Step Flash ADC Implementation Things To Be Done voltage subtractor and gain amplifier - input voltage range for the subtractor - output offset - proper gain setting (input range of fine ADC) 3-bit fine ADC - identical to the 4-bit coarse ADC