EE 435. Lecture 41. ADC Design

Save this PDF as:
 WORD  PNG  TXT  JPG

Size: px
Start display at page:

Download "EE 435. Lecture 41. ADC Design"

Transcription

1 EE 435 Lecture 4 ADC Design

2 Nyqyist ate Usage Structures. eview from last lecture. 0 esolution 6 SA Pipeline 8 4 Flash K 0K 00K M 0M 00M G 0G Speed

3 . eview from last lecture. SA ADC C LK IN EF DAC n DAC Controller DAC Controller may be simply U/D counter Binary search controlled by Finite State Machine is faster SA ADC will have no missing codes if DAC is monotone Not very fast but can be small

4 . eview from last lecture. Flash ADC EF IN X OUT d k n : n Encoder n CL

5 . eview from last lecture. Flash ADC Summary Flash ADC ery fast Simple structure Usually Clocked Bubble emoval Important Seldom over 6 or 7 bits of resolution Flash ADC has some really desirable properties (simple and fast) Wouldn t it be nice if we could derive most of the benefits of the FLASH ADC without the major limitations To be practical at higher resolution, must address the major limitation of the FLASH ADC Major Limitation of FLASH ADC at higher resolutions? Number of comparators increases geometrically --- n

6 ADC Types Nyquist ate Flash Pipeline Two-Step Flash Multi-Step Flash Cyclic (algorithmic) Successive Approximation Folded Dual Slope Over-Sampled Single-bit Multi-bit First-order Higher-order Continuous-time All have comparable conversion rates Basic approach in all is very similar

7 Two-Step Flash ADC X IN Flash S/H ADC DAC + Flash ADC n n C LK C LK C LK MSB Digital Assembler LSB n X OUT Can operate asynchronously (either after first S/H or even w/o S/H)

8 Two-Step Flash ADC with Interstage Gain X IN Flash S/H ADC DAC + A Flash ADC n n C LK C LK C LK MSB Digital Assembler LSB n X OUT

9 Three-Step Flash ADC with Interstage Gain and S/H X IN Flash S/H 0 ADC DAC + + A Flash S/H DAC ADC A S/H Flash ADC 3 n n n 3 C LK C LK3 C C LK0 MSB C LK5 LK C LK4 Digital Assembler n X OUT

10 Three-Step Flash ADC with Interstage Gain X IN Flash S/H 0 ADC DAC + + A Flash S/H DAC ADC A S/H Flash ADC 3 n n n 3 C LK C LK3 C C LK0 MSB C LK5 LK C LK4 Digital Assembler n X OUT X INk Flash ADC k DAC k + A k S/H k X OUTk C LK n k C LK Digital Assembler

11 Pipelined ADC X IN S/H Stage r Stage r Stage k r k Stage m r m n n n k n m <b > <b > <b k > <b m > X OUT =<n :n : :n m >

12 Pipelined ADC C LK X IN S/H Stage r r Stage r Z - Z - Stage k Z - k Stage m Z - r m n n n k n m <b m > Shift egister <b k > n X OUT <b > <b >

13 Pipelined ADC Stage k Pipeline Stage X INk + A k S/H k X OUTk ADCk DACk n k d k EF C LK

14 Pipelined ADC Stage k Pipeline Stage X INk + A k S/H k X OUTk ADCk DACk n k d k EF C LK Usually ealized as Single SC Block

15 Pipelined ADC Stage k Pipeline Stage X INk + A k S/H k X OUTk ADCk DACk n k d k EF C LK Usually ealized as Flash ADC (often simple comparator if n k =)

16 Pipelined ADC Stage k Pipeline Stage for bit/stage X INk + S/H k X OUTk ADCk DACk d k EF C LK O EF IN IN 0 EF IN IN 0

17 Transfer Characteristics for bit/stage O EF IN IN 0 EF IN IN 0 OUT DD IN SS DD SS

18 Consider the following circuit Φ C IN C OUT X Φ + Φ T

19 Consider the following circuit Φ C IN C OUT X Φ + C During IN C OUT + Φ

20 Consider the following circuit C During IN C OUT + Φ Q Q C C IN IN

21 Consider the following circuit Φ C IN C OUT X Φ + During Φ C X C + OUT

22 Consider the following circuit During Φ Q Q C C IN IN C X C + OUT Define Q T to be the charge transferred from C during phase Φ Q T C C C IN X IN X Define Q F to be the total charge on C during phase Φ Q F Q Q T C IN CIN X C C IN C CX

23 Consider the following circuit During Φ C X C + OUT F IN X Q C C C C CF Q C F C C IN C C X OUTF CF C C IN C C X

24 Consider the following circuit Φ C IN EF Φ d k C OUT EF Φ d k C C OUTF IN X C C If C =C =C and = - X EF OUTF IN EF

25 Consider the following circuit Φ C IN EF Φ d k C OUT Likewise EF Φ d k C C OUTF IN X C C If C =C =C and OUTF = X IN EF EF

26 Observe Φ C IN EF Φ d k C OUT EF Φ d k O EF IN IN 0 EF IN IN 0

27 -bit/stage Pipeline Implementation C Φ INk + S/H k OUTk IN EF Φ d k C OUT DACk EF Φ d k EF d k C LK O EF IN IN 0 EF IN IN 0

28 -bit/stage Pipeline Implementation INk EF INk ADCk d k d k

29 IN EF EF / C LK Interpolating ADC Amplifiers are finite-gain saturating Shown for 4-bit Clocked comparators usually regenerative educes Offset equirements for Comparators k+ k3 Thermometer to Binary Converter EF OUT k k k n X OUT EF / k k+ k k k3 IN

30 Cyclic (Algorithmic) ADC X IN C LK S/H h MUX h Gain/Shift Stage n r <b > Shift egister n X OUT e-use Pipelined Stage Small amount of hardware Effective thru-put decreases

31 End of Lecture 4