An 8-Bit 150-MHz CMOS A/D Converter

Transcription

1 UNIVERSITY OF CALIFORNIA Los Angeles An 8-Bit 150-MHz CMOS A/D Converter A dissertation submitted in partial satisfaction of the requirements for the degree Doctor of Philosophy in Electrical Engineering by Yun-Ti Wang 1999

2 Dedication To my parents and Jing for their love and support. iii

3 Table of Contents Chapter 1 Introduction Motivation Thesis Organization... 3 Chapter 2 ADC Applications and Architectures Applications Digital Oscilloscopes Gigabit Ethernet RGB-to-LCD Display Conversion Architecture Review Flash Architecture Two-Step Architecture Pipelined Architecture Interleaved Architecture Interpolating Architecture Chapter 3 Proposed ADC Architecture Sliding Interpolation Embedded Pipelining Addition of Interleaving iv

4 3.4 Clock Edge Reassignment Reinterpolation Effect of Nonlinearity in Sliding Interpolation Chapter 4 Circuit Design and Layout Considerations Introduction Front-End Sample-and-Hold Circuit Differential Amplifiers Comparator Clock Edge Reassignment Control and Decode Circuit ROM and Output Stage Clock Generator One Slice of First-Stage Signal Path Floor Plan And Layout Considerations Chapter 5 Experimental Results Introduction Design of Chip-on-Board Assembly Test Setup Experimental Results v

5 Chapter 6 Conclusion and Future Work Bibliography vi

6 List of Figures Figure 2.1 Digital oscilloscope Figure 2.2 ADC application in Gigabit Ethernet Figure 2.3 ADC application in RGB-to-LCD display conversion Figure 2.4 Block diagram of an N-bit flash ADC Figure 2.5 Transfer curves of an N-bit flash ADC Figure 2.6 Mapping scheme of a 4-bit two-step ADC Figure 2.7 Block diagram of an N-bit, two-step ADC Figure 2.8 Block diagram of a pipelined ADC Figure 2.9 Block diagram of an interleaved ADC Figure 2.10 A 2x active interpolating ADC Figure 3.1 Traditional active 2x interpolation architecture Figure 3.2 Sliding interpolation architecture Figure 3.3 Flow diagram of multi-stage sliding interpolation Figure 3.4 Sliding interpolation architecture Figure 3.5 Block diagram of multi-stage sliding interpolation Figure 3.6 Detailed block diagram of multi-stage sliding interpolation Figure 3.7 Sliding mechanism Figure 3.8 Pipelined sliding interpolation ADC architecture Figure 3.9 Addition of interleaving scheme Figure 3.10 Complete ADC architecure with replica SHA vii

7 Figure 3.11 (a) Timing mismatch in interleaved architecture, (b) generation of CK 1 and CK 2 by a frequency divider Figure 3.12 Basic concept of the clock edge reassignment Figure 3.13 Detailed operation of clock edge reassignment Figure 3.14 Reinterpolation (a) implementation, (b) error plot Figure 3.15 INL reduction by reinterpolation observed in Monte Carlo simulations Figure 3.16 Nonlinearity-induced error in 2x interpolation Figure 4.1 Dual-channel interleaved SHA Figure 4.2 Timing diagram for SHA Figure 4.3 A triple-channel interleaved SHA with a replica Figure 4.4 Preamplifier Figure 4.5 Reinterpolating and interpolating amplifiers Figure 4.6 Comparator used in the first stage (CMP_A) Figure 4.7 Comparator used in stages 2 to 5 (CMP_B) Figure 4.8 Clock edge reassignment circuit for a dual-channel system Figure 4.9 Operational diagram of a dual-channel CERA system Figure 4.10 Block diagram of NAND_FF with comparator Figure 4.11 Details of NAND_FF Figure 4.12 ROM and output stage Figure 4.13 Clock generator viii

8 Figure 4.14 High-speed differential D latch Figure 4.15 Realization of a slice of the signal path in the first stage Figure 4.16 Simulated output of the 8-bit ADC Figure 4.17 Layout floor plan Figure 4.18 Detailed circuit arrangement in the first stage Figure 4.19 Sliding/multiplexing mechanism of the lower bank Figure 4.20 Sliding/multiplexing mechanism of the upper bank Figure 4.21 Die photo Figure 5.1 Chip-on-board assembly Figure 5.2 Zoom-in of the central cavity area Figure 5.3 Actual size of chip-on-board assembly Figure 5.4 Mother board and daughter board Figure 5.5 A combination of different kinds of boards Figure 5.6 Test setup Figure 5.7 DNL and INL at f in = 1.8 MHz and f sample = 150 MHz Figure 5.8 FFT at f in = 1.76 MHz Figure 5.9 SNDR and SFDR at f sample = 150 MHz ix

9 List of Tables Table 1: Measurement Summary x

10 ACKNOWLEDGMENTS First, I would like to express my sincere thankfulness to Professor Behzad Razavi for his guidance and support throughout my Ph.D study. He is my role model. I am also grateful to Professors William J. Kaiser, Frank M. Chang, and James S. Gibson for serving on my Ph.D. committee. Next, I would like to thank Jafar Savoj and Tai-Cheng Lee for the helpful technical discussions with them and also Alireza Razzaghi for his proofreading of my dissertation. I am very grateful and feel very lucky that my wonderful parents are openminded, patient, and very supportive throughout this long graduate study process. I am also thankful for the support from other members in our family. Last but not the least, I would like to express my deepest gratitude to Guo Jing, my dear better half, who has generously and consistently provided me the crucial emotional support and love that I needed the most to complete this challenging process. With the mutual understanding, caring, encouragement, and support between us, I believe we can make more contributions to this world in the future. xi

11 ABSTRACT OF THE DISSERTATION An 8-Bit 150-MHz CMOS A/D Converter by Yun-Ti Wang Doctor of Philosophy in Electrical Engineering University of California, Los Angeles, 1999 Professor Behzad Razavi, Chair High-speed analog-to-digital converters (ADCs) with resolutions of 8 bits find wide application in instrumentation and communication systems. For example, portable digital oscilloscopes use 8-bit ADCs with sampling rates above one hundred megahertz. Also, the Gigabit Ethernet standard with CAT-5 copper cable requires four 125-MHz ADCs having a resolution of 7 to 8 bits to perform the frontend analog-to-digital data conversion. This dissertation presents an 8-bit, 5-stage interleaved and pipelined ADC that performs analog processing only by means of open-loop circuits such as differential pairs and source followers, thereby achieving a high conversion rate. The concept of sliding interpolation is proposed to obviate the need for a large number of comparators or interstage digital-to-analog converters and residue xiv

12 amplifiers. The pipelining incorporates distributed sampling between the stages so as to relax the linearity-speed trade-offs in the sample-and-hold functions. This work also introduces a clock edge reassignment technique that suppresses timing mismatch issues in interleaved systems. Moreover, in order to reduce the integral nonlinearity error (INL) with negligible speed or power penalty, a reinterpolation method is proposed. Fabricated in a 0.6-µm CMOS technology, the ADC achieves a DNL of 0.62 LSB, INL of 1.24 LSB, SFDR of 50 db, and SNDR of 43.7 db at 150 MHz sampling rate with low input frequencies. When input frequency is at 70 MHz, SNDR of 40 db is attained. The converter draws 395 mw from a 3.3-V supply and occupies an area of 1.2 x 1.5 mm 2. xv

13 Chapter 1 Introduction 1.1 Motivation Analog-to-digital (A/D) conversion and digital-to-analog (D/A) conversion are critical interfaces in mixed-signal processing systems. With the continuous advance of semiconductor technology and scaling of devices, digital circuits have achieved both high speed and low power dissipation. This trend has several impacts on mixed-signal integrated circuits (ICs). First, increasingly more operations are performed by digital circuits rather than by their analog counterparts. Second, the speed of the A/D and D/A interfaces must scale with the speed of the digital circuits in order to fully utilize the advantages of advanced technologies. Third, cost and performance make it desirable to achieve the high levels of integration on a single chip for mixed-signal processing systems. 1

14 The above observations lead to several important design implications for analog circuits. First, front-end analog signal processing and data conversion (including antialiasing filters) still remain as important niches where analog solutions provide advantages over digital approaches. A/D converters (ADCs) and D/A converters (DACs) will continue to play an indispensable and significant role in mixed-signal processing systems. Second, in video and communications applications, the transfer rate of the data between the analog and digital domains continues to increase, creating new challenges in the design of data converters. Third, when a data converter is implemented on a chip along with a great deal of digital circuitry, it experiences a substantial substrate and supply noise. Thus, the noise immunity of data converters becomes an extremely important issue in mixed-signal processing systems. Fourth, the power consumption of data converters is a critical parameter in many of today s applications, impacting the cost of packaging as well as the battery lifetime in portable products. In general, A/D conversion requires higher power consumption and circuit complexity than D/A conversion to achieve a given resolution and speed. Therefore, ADCs often appear as the bottleneck in high-performance mixed-signal systems. This observation underscores the importance of research and development to improve A/D conversion algorithms and circuits for future applications [8]-[37]. The goal of this research is to develop new A/D conversion architectures and circuit techniques that lead to high speed and moderate power consumption in CMOS 2

15 technology, with the objective of achieving a conversion rate well above 100 MHz at a resolution of 8 bits. Such A/D converters find wide application in digital sampling oscilloscopes, Gigabit Ethernet over CAT-5 twisted pair cables, RGB-to-LCD data conversion, and imaging systems with a large number of pixels. The concepts introduced in this research have been realized in the design of an 8-bit, 150-MHz A/D converter fabricated in a 0.6-µm CMOS technology. The prototype achieved a signal-to-(noise+distortion) ratio (SNDR) of 43 db at full sampling rate while consuming 395 mw from a 3.3-V supply. 1.2 Thesis Organization This dissertation presents both a theoretical study and experimental verification of the novel architecture and circuit techniques developed during the course of this research. Chapter 2 reviews applications of ADCs and conventional ADC architectures. Chapter 3 introduces the ADC architecture, presenting techniques such as sliding interpolation, embedded pipelining and interleaving, clock edge reassignment, and reinterpolation. Chapter 4 describes the design of each building block and various trade-offs at the circuit level and the architecture level. Some critical layout issues are also addressed. Chapter 5 presents the test procedure and the experimental results obtained for the prototype and Chapter 6 provides a summary and recommendations for future work. 3

16 Chapter 2 ADC Applications and Architectures In this Chapter, we first describe general potential applications of A/D converters with sampling rates above 100 MHz and resolutions of about 8 bits. These include digital oscilloscopes, Gigabit Ethernet receivers, and LCD displays. Next, we review a number of ADC architectures suited to high-speed operation and study their speed-resolution-power trade-offs [9]-[21]. Of interest to us are flash, two-step, pipelined, interleaved, interpolating architectures. 2.1 Applications Digital Oscilloscopes Digital oscilloscopes employ high speed ADCs to quantize the probed analog 4

17 signal. For portable digital oscilloscopes, low power consumption and cost are critical. As shown in Fig. 2.1, an 8-bit A/D converter digitizes input signal, a core DSP processes the result, and an 8-bit DAC converts the signal back to an analog waveform, which is then applied to the display. Display 8-bit ADC DSP 8-bit DAC Figure 2.1 Digital oscilloscope Gigabit Ethernet Gigabit Ethernet over CAT-5 twisted-pair wires requires four 8-bit, 125-MHz ADCs at the receiver end. The principal challenge in the design of these converters is power consumption. Shown in Fig. 2.2, the ADCs must provide sufficient dynamic range so as to accommodate a large echo and signal level variation due to the attenuation through the cable. 5

18 125 MHz CAT-5 8-bit ADC Echo Canceller Equalizer Demodulator Figure 2.2 ADC application in Gigabit Ethernet RGB-to-LCD Display Conversion Computer CRT displays typically incorporate three 8-bit RAMDACs to display the analog RGB images on a CRT monitor. With the advent of flat-panel LCD displays, it is necessary to convert the analog RGB signals to the form required for LCD displays. This is accomplished as shown in Fig High-end LCD displays require an ADC conversion rate of 150 MHz. The power dissipation is also critical because three such ADCs are integrated on one chip. 6

19 RGB Display 150 MHz DSP 8-bit DAC 8-bit ADC DSP LCD Display 8-bit 8-bit DAC ADC 8-bit 8-bit DAC ADC Figure 2.3 ADC application in RGB-to-LCD display conversion. 2.2 Architecture Review Flash Architecture Figure 2.4 shows the block diagram of an N-bit flash ADC. The analog input signal is simultaneously compared with threshold voltages of the ADC by an array of 2 N 1 comparators, thereby producing a thermometer code. The result is subsequently converted to a binary output by an encoder. The threshold levels are usually generated by a ladder consisting of a string of matched resistors. 7

20 V ref V in V MAX = V R [2 N 1] V R [2 N 2] N 1 2 N 2 0 Thermometer + 1 Encoder Output 2 N 1 --> N N V R [2] V MIN = V R [1] Comparators Figure 2.4 Block diagram of an N-bit flash ADC. The operation of a flash ADC can be viewed from another perspective that leads to techniques such as interpolation. Illustrated in Fig. 2.5 are the differential outputs of each preamplifier in the ADC as the analog input varies from V MIN to V MAX. We note that each output crosses zero when the input of the preamplifier crosses its respective reference voltage. Hence, the ADC operation can be viewed as a collection of these zero crossings. 8

21 V R [2 N 2] V = V R [2 N MAX 1] V MIN 0 V in V MAX V MIN = V R [1] V R [2] 2 N 1 Zero-crossings Figure 2.5 Transfer curves of an N-bit flash ADC. The principal advantage of the flash architecture is its high throughput rate. The conversion of each sample takes only one single clock period. However, many issues limit the utility of this approach for resolutions above 6 bits. The exponential growth of the input capacitance, power dissipation, and area are critical drawbacks. Furthermore, the offset of the comparators, the feedthrough of the analog input to the resistor ladder [2], the slew-dependent comparator delay [4][7], and the problem of bubbles in the thermometer code [2][4] degrade the static and dynamic performance substantially. 9

22 2.2.2 Two-Step Architecture In order to avoid the exponential growth encountered in flash ADCs, the quantization of the signal can be performed in two or more steps. The basic principle of the two-step architecture can be illustrated by the mapping scheme of a 4-bit ADC as shown in Fig In the two-step topology, the input range is first divided into four equal segments, and a coarse quantizer is used to determine in which segment the analog input lies, thus producing the most significant bits (MSBs). Next, each segment is subdivided into four segments, and a fine quantizer detects the least significant bits (LSBs). MSB overflow 11 LSB overflow Coarse Quantizer Fine Quantizer Figure 2.6 Mapping scheme of a 4-bit two-step ADC. A more detailed description of the operation is depicted in Fig. 2.7, where the block diagram of an N-bit, two-step ADC and the conversion flow are illustrated. The circuit consists of a sample-and-hold amplifier (SHA), two flash quantizers, D/A 10

23 converter, and a subtractor. Analog Input V in S/H Residue V res Coarse ADC N 1 -bit DAC N 1 -bit Fine ADC N 2 -bit N 1 MSBs N 2 LSBs N-bit Digital Output Buffer (a) D out N-bit Digital Output Analog input V in MSB 11 Residue 10 V res LSB Digital Output D out 1011 V Coarse Subtractor Fine Quantizer Quantizer (b) Figure 2.7 Block diagram of an N-bit, two-step ADC. 11

24 The conversion proceeds as follows: an analog input signal with magnitude of V in is sampled by the SHA and subsequently mapped onto the level V 1 by the coarse quantizer, resulting in the two MSBs, e.g., 10 in this case. Next, an analog residue, V res, is produced by the subtractor and digitized by the fine quantizer, thereby generating the two LSBs. The primary advantage of the two-step topology is that it requires less hardware and power than a flash architecture. However, this savings is obtained at the cost of longer processing time, leading to a substantial reduction of the throughput rate Pipelined Architecture From the above discussion, it is clear that the use of multiple stages can alleviate the exponential growth present in flash topologies. The two-step architecture exemplifies this benefit to a certain degree, but the low throughput rate limits the use of this approach. Pipelining enables potentially faster conversion while avoiding the exponential growth of power and hardware. Figure 2.8 illustrates the block diagram of a pipelined ADC. The analog input is applied to the first stage in the chain, and N 1 bits are detected. The analog residue is also generated and applied to the next stage. The same procedure repeats up to the end of the chain. This concept is similar to the idea of an assembly line because the interstage sampling allows all of the stages to operate concurrently. A common approach to pipelining is based on a precision multiply-by-two stage 12

25 [7] that merges most of the interstage operations into a compact circuit. Usually used with 0.5 bits of overlap, this technique provides a modular implementation. Analog Input Stage 1 Stage j Stage m N 1 bits N j bits N m bits S/H 2 N j ADC N j -bit DAC N j -bit N j bits Figure 2.8 Block diagram of a pipelined ADC. The pipelined architecture offers a number of advantages. First, the throughput rate is determined by the speed of only one stage in the pipeline. Second, interstage residue amplification relaxes the precision required of subsequent stages. Third, the power and hardware of pipelined converters grow almost linearly with the number of bits. Also, overlap and digital correction [2] can be used to allow large offsets in the comparators. The primary drawback of the conventional pipelined topology is the need for high 13

26 precision in the interstage SHAs, DACs, and subtractors, especially at the front end. The precision typically mandates the use of op amps, imposing severe trade-offs among speed, voltage swing, gain, and power dissipation. As device dimensions, supply voltages, and the intrinsic gain (g m r o ) of MOSFETs continue to scale down, the design of op amps becomes increasingly more difficult Interleaved Architecture In the pipelined topology, the conversion rate is still limited by the settling time and accuracy requirements of the interstage operations. Interleaving can be used to further improve the throughput rate. The basic principle behind interleaving is illustrated in Fig The architecture employs M identical sub-adcs, each incorporating a SHA that tracks for T 1 seconds and holds for (M 1)T 1 seconds. Thus, each sub-adc is allotted (M 1)T 1 seconds for one conversion. The use of multiple parallel channels, however, introduces serious difficulties due to mismatches [14]. Tones at f ck /M and fixed-pattern noise are generally caused by offset mismatches and sideband modulation around f ck /M is introduced due to gain mismatches. The dynamic performance is severely affected by the timing mismatch among the channels [5][6]. 14

27 CK 1 SHA 1 Sub-ADC 1 N bits CK 2 V in SHA 2 Sub-ADC 2 N bits Digital M x f ck CK M SHA M Sub-ADC M N bits CK 1 T 1 (M 1)T 1 CK 2 CK M t Figure 2.9 Block diagram of an interleaved ADC. 15

28 2.2.5 Interpolating Architecture As mentioned in Section 2.2.1, one of the critical disadvantages of the flash topology is the large input capacitance. This problem can be alleviated by applying interpolation as shown in Fig The idea is that if V in crosses (V R2 + V R1 )/2, then V o2 crosses zero, increasing the resolution by a factor of two. In essence, interpolation adds zero crossings to the set of input/output characteristics of a flash stage. V in Preamplifiers Interpolating Amplifiers V R2 V o3 V o2 V R1 V o N + 1 Figure 2.10 A 2x active interpolating ADC. Interpolation lends itself to implementation submicron technologies because the amplifiers used in Fig need not have an accurate gain, high linearity, or large output swings. Also, it can reduce the differential nonlinearity (DNL) resulting from the offset of the preamplifiers [30]. However, the simple scheme shown in Fig still requires 16

29 high power and substantial hardware because of the 2x growth in each interpolation step. Furthermore, the offset voltages of the amplifiers lead to uncorrected integral nonlinearity (INL). 17

30 Chapter 3 Proposed ADC Architecture In this Chapter, we describe the architecture of the proposed A/D converter. We introduce the concept of sliding interpolation as a means of avoiding the exponential growth of power and area, extending the idea to multiple stages. Next, we incorporate a distributed sampling scheme between the stages so as to realize pipelining without op amps. To further improve the conversion rate, dual-channel interleaving is employed in all of the interpolative stages, while triple-channel interleaving is used in the front-end sample-and-hold circuit. In order to minimize dynamic performance degradation due to the timing mismatch among the channels in an interleaving system, a new technique, namely clock edge reassignment is proposed. The concept of reinterpolation is also introduced to reduce the INL by roughly 30%. Finally, the effects of the gain and offset mismatches among different channels are studied in a generic interleaved architecture 18

31 with interpolation. 3.1 Sliding Interpolation Interpolation can generally be viewed as analog-to-digital conversion in terms of zero-crossing points rather than direct amplitude quantization. The basic operation can be described as follows. A group of preamplifiers first generate the difference between the analog input signal and each tap voltage of a reference ladder. According to their polarities, the outputs of these preamplifiers can be divided into two groups: positive and negative, with a distinctive boundary between them. This phenomenon is similar to what happens inside a thermometer and can be used later to recover the actual amplitude information of the original analog input signal. These preamplifier outputs can then be fed into the next-level bank of interpolating amplifiers, whose outputs retain the thermometer code property. With the aid of these interpolating amplifiers, this code contains more divisions and hence a higher resolution. As long as the zero-crossing boundary is unique and the code exhibits sufficient linearity, the original analog signal can be recovered. Before introducing the concept of sliding interpolation, let us first briefly review the traditional active interpolation. As an example, a simple active 2x interpolation circuit is shown in Fig While this scheme reduces the number of the input preamplifiers and hence the input capacitance, it still requires a large number of differential pairs and comparators. However, we recognize that for a given input level, the outputs of only a few preamplifiers in the first stage are of interest. Thus, the 19

32 subsequent stages need not interpolate the outputs of all of the preamplifiers. We then surmise that a compact interpolating stage can slide up and down if the analog input value is roughly known. Shown in Fig. 3.2, the idea is to use a sub-adc to determine which preamplifier outputs must be interpolated and route these outputs to the interpolating differential pairs through a differential multiplexer (MUX). The rest of the preamplifier outputs are discarded. V in Preamplifiers Interpolating Amplifiers V R2 V o3 V o2 V R1 V o N + 1 Figure 3.1 Traditional active 2x interpolation architecture. While, in principle, multiplexing and interpolating between only two outputs is sufficient, in this design we process four preamplifier outputs to allow margin for offsets of the comparators in the sub-adc. When this concept is repeatedly applied to the following stages, a multi-stage sliding interpolation system can be formed. 20

33 V in MUX V o3 V R2 V o2 V R1 V o1 Sub-ADC Figure 3.2 Sliding interpolation architecture. Through the sliding interpolation, the power and hardware grow only linearly, rather than exponentially. These features make sliding interpolation a promising architecture for high-speed ADCs. The principle of multi-stage sliding interpolation is illustrated in Fig The first stage has 16 preamplifiers to generate 16 zero crossings. If the analog input lies between V R,j and V R,j+1, then a 4-bit coarse ADC and a 16-to-4 MUX route the outputs of the preamplifiers sensing V R,j 1,..., V R,j+2 to the next interpolating stage. 21

34 Stage 1 Stage 2 Stage 3 Stage 4 V max V R,j+2 V in V R,j 1 V min MUX (16 --> 4) MUX (7 --> 4) MUX (7 --> 4) Figure 3.3 Flow diagram of multi-stage sliding interpolation. Since only 2x-interpolation is used, each stage, excluding the first one, generates a total of seven outputs. Also a sub-adc is used to detect two more bits in each stage. The overall resolution is increased by one bit because the second bit is used for subsequent digital error correction. Detection of zero crossings can be implemented by a simple differential amplifier. Therefore, all of the decision levels in Fig. 3.3 can be replaced by amplifiers as shown in Fig

35 Stage 1 Stage 2 Stage 3 Stage 4 V max V in V min MUX (16 --> 4) MUX (7 --> 4) MUX (7 --> 4) Figure 3.4 Sliding interpolation architecture. If the gain of every amplifier in each stage is about two, the input dynamic range of the sub-adcs remains nearly the same through the chain. All of the sub-adcs can therefore be realized in the same form, allowing a modular design. 23

36 V max V in V min (a) V in Stage 1 Stage 2 Stage 3 Stage 4 SHA Pre- AMP MUX Interpolative AMP MUX Interpolative AMP MUX Interpolative AMP Sub- ADC Sub- ADC Sub- ADC Sub- ADC (b) Figure 3.5 Block diagram of multi-stage sliding interpolation. The implementation of the sliding interpolation is shown in Fig The frontend SHA samples and holds the analog input signal. In stage 1, the preamplifiers generate 16 zero crossings, while the sub-adc determines the four MSBs. In the second and the following stages, each MUX is commanded by the sub-adc in the previous stage to select and route four amplified outputs to the interpolative amplifiers. Stages 2 through 5 are identical, simplifying the design and layout. 24

37 Further details of the sliding interpolation are shown in Fig The first stage incorporates 16 preamplifiers while each of the following interpolative stages requires seven amplifiers. By virtue of this technique, the total number of differential pairs reduces from roughly 500 to 50. The five sub-adcs require a total of 28 comparators. Stage 1 Stage 2 Stage 3 Stage 4 V in 16 Preamps MUX (16 --> 4) 2x- Interpolation 2x- Interpolation MUX MUX (7 --> 4) (7 --> 4) 2x- Interpolation SHA Sub- ADC Sub- ADC Sub- ADC Sub- ADC 4 bits 2 bits 2 bits 2 bits Figure 3.6 Detailed block diagram of multi-stage sliding interpolation. 25

38 Output (V) A: Stage 1 Sliding Interpolation (5 Stages) Input (V) B: Stage C: Stage D: Stage Output (V) E: Stage Input (V) Figure 3.7 Sliding mechanism 26

39 Figure 3.7 plots the amplifier outputs in each stage as sliding interpolation is activated. The outputs of the first stage exhibit zero-crossing points that are separated by 50 mv. After sliding interpolation with redundancy, zero crossings with 25-mV spacing are generated, etc. Sliding interpolation provides a number of benefits. First, as described before it lends itself well to the multi-stage pipelining with no D/A converters or subtractors. Second, it requires no precision gain in any of the building blocks, allowing the use of simple differential pairs in the entire signal path. Third, it can include reinterpolation to improve the precision. Although, the hardware size and the associated power consumption in the sliding interpolation structure are substantially less than those in the traditional interpolation method, the throughput rate is severely limited by the multi-stage operation. For each held analog input sample, the overall A/D conversion is not complete unless the digital data is generated by all of the sub-adcs, an operation that can easily take several tens of nanoseconds. For a higher conversion rate, a pipelining scheme is needed. 3.2 Embedded Pipelining As mentioned before, pipelining can improve the throughput rate. The question is where and how it should be applied. As shown in Fig. 3.6, each interpolative stage contains only two analog blocks, a MUX and an amplifier bank. Thus, pipelining can be applied at only one of two points: at the input or output of the MUX. 27

40 Stage 1 Stage 2 V in 16 Preamps 16 MUX (16 --> 4) 4 Distributed Sampling & 2x- Interpolation To stages 3 to 5 SHA Sub- ADC Sub- ADC 4-bit 2-bit Digital Error Correction Figure 3.8 Pipelined sliding interpolation ADC architecture. As shown in Fig. 3.8, the interface between the multiplexer and the amplifier bank is the best choice. This is so for two reasons. First, the multiplex switches can also function as the sample-and-hold switches, significantly reducing the delay between the two stages because only one switch appears in the signal path between two consecutive stages. Second, the interconnection wires between the multiplexers and the interpolative amplifiers exhibit a significant amount of parasitic capacitance, which can 28

41 now be utilized as the sample-and-hold capacitors. This type of distributed sample-andhold system is similar to that reported in [19]. Partitioning the conversion into several equal-length time slots, the pipelining significantly improves the throughput rate. Note that each stage in the pipeline operates in the sample mode for half of the clock period and in the hold mode for the other half. On the other hand, the sub_adc in each stage operates only during the hold mode, raising the possibility of adding interleaving to further increase the throughput rate. 3.3 Addition of Interleaving Besides the reasons mentioned in the previous section, the addition of interleaving is also desirable because, even though the maximum path length between consecutive samplers in the pipeline corresponds to roughly two differential pairs, the settling requirements still limit the conversion speed. As shown in Fig. 3.9, the converter employs two identical interleaved channels to increase the speed. The multiplexers (MUXs), distributed sample-and-holds, and 2x-interpolation amplifiers are duplicated for the even and the odd channels whereas the front-end buffer, the preamplifiers, and all of the sub-adcs are shared between the two channels. The timing is such that when one stage in the odd channel is in the sampling mode, the corresponding stage in the even channel is in the hold/amplification mode and vice versa. 29

42 Stage 1 Stage 2 Stage 3 Preamps OFF (odd) ON (odd) SHA (odd) M U X Distributed S/H & 2x Interpolation M U X Distributed S/H & 2x Interpolation V in Buffer Sub- ADC Sub- ADC (even) (even) SHA (even) M U X Distributed S/H & 2x Interpolation M U X Distributed S/H & 2x Interpolation ON OFF Digital Output Figure 3.9 Addition of interleaving scheme. When the SHA in the odd channel is sampling the analog input, the SHA in the even channel is holding and passing the previous analog sample to the preamplifiers through the buffer. The sub-adc in stage 1 then generates the four-bit digital code and commands the MUX in the even channel of stage 2 to redirect the selected preamplifier outputs to the interpolation amplifiers. Even though the addition of interleaving increases the speed by almost a factor of two, the first sub-adc still creates three difficulties. First, due to the finite impedance seen at the preamplifier outputs, the kickback noise generated by the sub- 30

43 ADC considerably disturbs the analog signals at the inputs of the MUX thereby requiring a long settling time after the sub-adc is strobed. Second, the sub-adc cannot begin its conversion until the front-end SHA, the buffer, and the preamplifier outpus are settled. Since the buffer drives a relatively large capacitance, the settling in this path is quite slow. Third, since the sub-adc appears in the critical path, that is, the preamplifier outputs must remain idle until the sub-adc makes a decision, the throughput rate is severely limited. Stage 1 Stage 2 Stage 3 SHA (odd) Preamps OFF M U X (odd) Distributed S/H & 2x Interpolation ON M U X (odd) Distributed S/H & 2x Interpolation V in Buffer Sub- ADC (even) (even) SHA (even) M U X Distributed S/H & 2x Interpolation M U X Distributed S/H & 2x Interpolation Replica ON OFF SHA (odd) Buffer Sub- ADC Digital Error Correction SHA (even) Digital Output Figure 3.10 Complete ADC architecure with replica SHA. 31

44 Figure 3.10 illustrates a modification that alleviates all of the above issues. A replica front-end SHA is added and its output directly drives the first sub-adc. Scaled down in device sizes and current levels by a factor of two with respect to the main SHA, the replica prohibits the large kickback noise of the sub-adc from corrupting the output of the preamplifiers. Also, the replica signal experiences a shorter delay than that in the main path because of the much smaller load capacitance seen by the replica buffer. Thus, the sub-adc can be strobed much earlier than before. The use of interleaving raises concern with respect to mismatches between the offsets, gains, and timings of the two channels. The first two issues will be discussed in Section 3.6. The problem of the timing mismatch and the proposed solution are described in the next section. 3.4 Clock Edge Reassignment Before proposing a solution for the timing mismatch problem in interleaved systems, we revisit the problem itself to understand its nature. As shown in Fig. 3.11(a), two interleaved channels, SHA 1 and SHA 2, require two corresponding clocks, CK 1 and CK 2, which are generated by two different clock generators. In the ideal case, the sampling edge of CK 1 is placed precisely midway between the sampling edges of CK 2 such that SHA 1 and SHA 2 sample the analog signal at evenly-spaced points in time. 32

45 CK 1a Clock Generator 1 CK 1 SHA 1 CK 2a Clock Generator 2 CK 2 SHA 2 T a T b CK 1 CK 2 (a) 2T = T a + T b CK CK 1 in 2 CK 2 (b) Figure 3.11 (a) Timing mismatch in interleaved architecture, (b) generation of CK 1 and CK 2 by a frequency divider. This is usually accomplished by a frequency divider [Fig. 3.11(b)], producing CK 1 and CK 2 with a nominal duty cycle of 50% even if the duty cycle of CK in deviates from 50%. In reality, however, the devices in the clock generators of Fig. 3.11(a) or the frequency divider of Fig. 3.11(b) suffer from substantial mismatches, especially at high 33

46 speeds, introducing large timing errors between CK 1 and CK 2. Since an 8-bit ADC sampling a 75-MHz signal cannot tolerate timing mismatches greater than roughly 12 ps, frequency division does not provide the accuracy required in this design. The problem of timing mismatch can be considerably relaxed if a single clock drives both SHAs. Since the duty cycle of the clock may deviate from 50%, only one of the edges must be used for the sampling command in both circuits. Figure 3.12 illustrates how this is accomplished by clock edge reassignment. Two switches, S 1 and S 2, and two predictive control signals, V odd and V even, are added to the system. A master clock, CK master, with a frequency twice the sampling rate, is provided to the two channels through the two switches. The predictive signals V odd and V even enable one of the switches S 1 or S 2, thus routing the falling edge of CK master to either of the SHAs. The timing mismatch is now equal to the propagation delay mismatch between S 1 and S 2, and the two switches inside SHA 1 and SHA 2, a value that can be maintained well below 10 picoseconds even with 20% mismatch between the sizes of the switches. The timing of V odd and V even is quite relaxed so long as they contain the falling edge of CK master with enough margin. Thus, they can be produced by a simple nonoverlapping clock generator. In reality, each SHA requires both a rising edge and a falling edge to perform the sample and hold operations. As shown in Fig. 3.13, the falling edges of CK 1x and the rising edges of CK 2x are alternately applied to the SHAs, while the rising edges of 34

47 CK 1x and the falling edges of CK 2x are discarded. V odd V in CK master S 1 V even SHA 1 S 2 SHA 2 To SHA 1 To SHA 2 CK master V odd V even Figure 3.12 Basic concept of the clock edge reassignment. The actual sequence of operation is as follows: during phase 1, the falling edge of CK 1x is routed to SHA 1 and the rising edge of CK 2x to SHA 2. During phase 2, the states of CK 1 and CK 2 are stored, and during phase 3, the falling edge of CK 1x is rerouted to SHA 2 and the rising edge of CK 2x to SHA 1. This concept can be easily extended from two channels to three, or more channels. As discussed in Section 6.2, the front-end sample-and-hold circuit used in this work incorporates three channels. 35

48 A1 CK 1x CK 1 SHA 1 CK 1x CK 1 SHA 1 CK 1x CK 1 SHA 1 CK 2x CK 2 SHA 2 A2 1 CK 2x 2 CK 2 SHA 2 CK 2x 3 CK 2 SHA Odd Odd Odd Even Even Even CK 1x (from A 1 ) CK 2x (from A 2 ) CK 1 CK 2 T T T T Figure 3.13 Detailed operation of clock edge reassignment. 3.5 Reinterpolation As mentioned in Chapter 3, an important benefit of interpolation is the reduction of the differential nonlinearity resulting from the offset of the preamplifiers [2,3]. However, integral nonlinearity still remains uncorrected, demanding large input devices. To alleviate the problem, a reinterpolation method is introduced here. As depicted in Fig. 3.14(a), the original outputs (V A s) from the preamplifiers are fed into another bank of interpolation amplifiers to generate a second set of interpolated outputs (V B s) which, though different from V A s, contain sufficient information to represent the original analog input signal. If the offset components of the adjacent V A s are 36

49 uncorrelated, the standard deviation of the offsets of the corresponding V B s is reduced by a factor of the square root of 2. As shown in Fig. 3.14(b), INL A or INL B is defined as the maximum offset error of the zero crossings of V A s or V B s respectively. If only the interpolated zero crossings, V B s, are sensed by the following stages and the original zero crossings, V A s, are discarded, then, the overall INL is reduced by approximately 30%. Figure 3.15 plots the maximum INL with and without reinterpolation as predicted by Monte Carlo simulations, confirming the theoretical result. The reduction of the INL translates into a higher tolerance of offsets in the preamplifiers, allowing smaller input devices and a two-fold reduction in the capacitance seen by the buffer driving the first stage. The redundancy associated with reinterpolation is necessary only in the first stage of the pipeline, where the cumulative gain is still low; in stages 2 through 5 all zero crossings are utilized. Thus, reinterpolation is obtained at the cost of a few additional differential pairs. 37

50 Preamplifiers Reinterpolation Amplifiers Interpolation Amplifiers V A3 V B2 V A2 V B1 V A1 V A1, V A2, V A3 discarded (a) INL A 1 0 V in INL A INLB B 1 A 2 A s: Original Offsets B s: Interpolated Offsets : Original Zero Crossings : Interpolated Zero Crossings B 1 = A 1 + A 2 2 σ B1 = σ 2 A1 + σ 2 A2 2 (b) = σ original 2 Figure 3.14 Reinterpolation (a) implementation, (b) error plot. 38

51 Wave D0:A0:v(va1) D0:A0:v(va2) D0:A0:v(va3) D0:A0:v(va4) D0:A0:v(va5) D0:A0:v(va6) D0:A0:v(va7) D0:A0:v(va8) D0:A0:v(va9) D0:A0:v(va10) D0:A0:v(va11) D0:A0:v(va12) D0:A0:v(va13) D0:A0:v(va14) D0:A0:v(va15) D0:A0:v(va16) Symbol Voltages (lin) 20m 15m 10m 5m 0-5m -10m * offset averaging mechanism through interpolation by 2-15m -20m m 0 500m Voltage X (lin) (VOLTS) Panel 2 1 Wave D0:A0:v(vb1) D0:A0:v(vb2x) D0:A0:v(vb3x) D0:A0:v(vb4x) D0:A0:v(vb5x) D0:A0:v(vb6x) D0:A0:v(vb7x) D0:A0:v(vb8x) D0:A0:v(vb9x) D0:A0:v(vb10x) D0:A0:v(vb11x) D0:A0:v(vb12x) D0:A0:v(vb13x) D0:A0:v(vb14x) D0:A0:v(vb15x) D0:A0:v(vb16x) Symbol Voltages (lin) 10m 8m 6m 4m 2m 0-2m -4m -6m -8m -10m -12m m 0 500m Voltage X (lin) (VOLTS) 1 Figure 3.15 INL reduction by reinterpolation observed in Monte Carlo simulations. 39

52 3.6 Effect of Nonlinearity in Sliding Interpolation While the first stage of interpolation by a factor of two is quite insensitive to the nonlinearity of differential pairs [2], the subsequent reinterpolation and interpolation are susceptible to nonlinearity in each differential pair. Figure 3.16 illustrates the effect. Curves A and B are the original characteristics with the zero-crossing points at V 0 and V 2. After first 2x interpolation, curve C is generated with a zero crossing at V 1 and a slope of one half of the original one. If one more 2x interpolation is applied between curves B and C as shown in the circled area in Fig. 3.16, the resulting zero-crossing point should ideally fall midway between V 1 and V 2, i.e., at V id. In practice, however, the actual zero-crossing point, V act, deviates from V id because B and C exhibit different slopes. The difference between V act and V id is denoted by δ. In the worst case, curve A is flat for V in > V 1 and the slope of curve C is equal to one half of that of B. Through a simple derivation, it can be shown δ = (V 2 - V 1 )/6 and hence curve D suffers from a DNL of 1/3 LSB. In order to further increase the resolution through active 2x interpolation, the linear portion of curves A or B must be extended accordingly. 40

53 V 1 A C B V in V 0 V 2 Ideal Position V id δ C B V 1 V in D V 2 V act Actual Position Figure 3.16 Nonlinearity-induced error in 2x interpolation. 41

54 Chapter 4 Circuit Design and Layout Considerations 4.1 Introduction In this chapter, the design of the ADC s building blocks as well as various layout considerations are discussed. All of the analog signal paths are implemented in differential form to achieve a wide dynamic range and high immunity to common-mode noise. For the sake of simplicity, some of the circuits are drawn in single-ended form. 4.2 Front-End Sample-and-Hold Circuit The front-end SHA plays a critical role in the dynamic behavior of the converter. In order to achieve fast settling, this circuit uses a simple top-plate sampling method and a PMOS source follower as shown in Fig

55 V DD CK 1a CK 1b X V in M S 1 1 S 2 V out C 1 CK 1b CK 1a S 3 S 4 C 2 Figure 4.1 Dual-channel interleaved SHA. The interleaving is realized in the sampling network by alternately connecting C 1 and C 2 to V in whereas the source follower is shared between the two channels. Thus, gain and offset mismatches arise primarily from the charge injection mismatches of S 1 - S 4. The n-well of the source follower is tied to its source to suppress nonlinearity and gain error due to body effect. Simulations indicate that two such followers operating differentially achieve a linearity of about 10 bits. The input-dependent charge injection from S 1 and S 3 does introduce nonlinearity but it is partially cancelled by the charge absorbed by S 2 and S 4. Also, differential operation as well as large sampling capacitors (1 pf) improve the overall linearity to about 9 bits. 43

56 The finite input capacitance of the source follower results in an equivalent resistor connected between the outputs of the two channels, yielding a gain roll-off at high frequencies. From another perspective, the capacitance seen at node X and switches S 2 and S 4 form a switched-capacitor low-pass filter. With proper design, this roll-off is limited to 1 db at an input frequency of 75 MHz. CK Sample Quantize/MUX (a) Sample Quantize MUX t (b) CK a CK b CK c (c) Figure 4.2 Timing diagram for SHA. In the actual design, the front-end SHA is realized with triple-channel interleaving. This is because the sampling phase is quite faster than the hold/ quantization/multiplexing phase, thereby requiring a clock duty cycle of about 30% [Fig. 4.2(a)]. Since the duty cycle deviates substantially from 50%, it is difficult to employ dual-channel interleaving without any dead time. To resolve this issue, the clock period is divided into three equal time slots: one for front-end sampling, one for 44

57 sub-adc (coarse quantization), and one for multiplexing [Fig. 4.2(b)]. The timing diagram of Fig. 4.2(c) is then used to interleave three sampling capacitors. To generate the time slots with reasonable accuracy, the 150-MHz clock is divided by 3 on the chip. V DD V DD (To Preamps) (To sub-adc 1 ) V out, m V out, r CK 1c CK 1a CK 1a CK 1b M 1m S 2m S 1m S 1r S 2r M 1r C 1m V in C 1r CK 1a CK 1b CK 1b CK 1c S 4m S 3m S 3r S 4r C 2m C 2r CK 1b CK 1c CK 1c CK 1a S 6m S 5m S 5r S 6r C 3m C 3r Main SHA Replica SHA Figure 4.3 A triple-channel interleaved SHA with a replica. The actual triple-channel interleaved SHA circuit is shown in Fig As mentioned before, the replica is scaled down by a factor of two with respect to the main 45

58 SHA. The switches connected between V in and the sampling capacitors use the same timing sequence in both of the main and the replica SHAs. However, the switches connected between the sampling capacitors and the PMOS source followers have a different timing sequence in the two SHAs. For each channel in the main SHA, the operation sequence is: (1) sampling, (2) holding, (3) holding and connecting the held sample to the PMOS source follower. On the other hand, the replica operates in a slightly different sequence: (1) sampling, (2) holding and connecting the held sample to the PMOS source follower (whose output is then sensed by the first sub-adc ). (3) holding. 4.3 Differential Amplifiers The A/D converter incorporates differential difference amplifiers in the first stage and simple differential pair in the subsequent stages. The resistors used in the prototype are realized by non-silicided polysilicon. As shown in Fig. 4.4, the preamplifier consists of two NMOS differential pairs with source degeneration. In order to properly transform amplitude quantization into zero crossings, the design of the preamplifiers requires special attention to several issues. First, the input-referred offset of the circuit must be less than 1/4 LSB so that it does not degrade the overall DNL and INL significantly. The offset arises from three sources: mismatch between the input transistors, mismatch between the load resistors, and mismatch between the tail current sources. The mismatch of the differential pair 46

59 typically dominates the overall offset. V DD R 1a R 2a V out + V in + M 1a M 2a V in M 3a M 4a V out V ir + V ir R c1a R c2a I 1a I 2a I 3a I 4a R 1a, R2a : 4x200 Ω M 1a -- M 4a : R c1a, R c2a : I 1a -- I 4a : 8x12/ Ω 0.4 ma (4x12/1.5) Figure 4.4 Preamplifier. By virtue of reinterpolation the tolerable offset is 30% higher and, with the aid of the data in [39], the dimensions of M 1a - M 4a are chosen as W/L = 100 µm/0.6µm. This results in a total gate area of 60 µm 2, about one half of that reported in [19]. The matching requirement of the output resistors is alleviated by the gain of the preamplifier and with proper layout. The mismatch of the tail current sources is reduced significantly by using a channel length of 1.5 µm and a channel width of 48 µm. The second issue relates to the gain of the preamplifier. The gain is chosen to be around two as a trade-off between gain, linearity, and speed. Finally, although the 47

60 output of preamplifiers has a small swing, about 200 mv single-ended, the preamplifiers do require a wide input common-mode range, approximately 800 mv. This common-mode constraint limits the overdrive voltage of the input devices and the tail current source. The current densities must therefore be low enough to consume a reasonable headroom. This is possible for the current source but not for the input transistors as their linearity determines the DNL and INL in subsequent interpolation stages. The reinterpolating and interpolating amplifiers have the same topology but different device dimensions and bias currents. Figure 4.5 shows the details. V DD R 1b R 2b V out + V in + M 1b M 2b V out V in R c1b Reinterpolating Amp I 1b I 2b Interpolating Amp M 1b, M 2b : R 1b, R 2b : R c1b : I 1b, I 2b : 12x8/0.6 4x125 Ω 2x200 Ω 0.8 ma M 1b, M 2b : R 1b, R 2b : R c1b : I 1b, I 2b : 12x4/0.6 2x500 Ω 2x200 Ω 0.4 ma Figure 4.5 Reinterpolating and interpolating amplifiers. 48

61 4.4 Comparator The design of the comparators used in the sub-adcs directly impacts the speed and power dissipation of the overall converter. Shown in Fig. 4.6 is the high-speed comparator utilized in the first stage sub-adc. When CK is low, S b1 and S b2 are off. All the p-switches (S 1 - S 4 ) are on and the four internal nodes (P, Q, X, and Y) are pulled up to V DD with the aid of two equalization switches (S eq and S eqx ), placing the comparator in the reset mode. When CK goes high, S b1 and S b2 turn on and M 1 - M 4 compare the positive input voltage, V in +, with the positive reference voltage, V r +, and the negative input voltage, V in, with the negative reference voltage, V + r. When all of the reset and equalization PMOS switches are off, the cross-coupled inverters (M 5 - M 8 ) regeneratively amplify the difference between the inputs to rail-to-rail levels. The digital outputs are buffered by inverters and then fed to the control circuit. This comparator offers three important advantages over other topologies. First, the static power dissipation is zero. When CK is low, no static current flows through the circuit. When CK is high, M 7 and M 8 ensure that the current is zero. Second, the comparator requires only a single-phase clock, greatly simplifying the routing of the clock across the chip. 49

62 S eq CK CK S 1 S 3 S 2 M 5 CK M 6 CK P Q M 7 CK M 8 S 4 CK Inv 1 Inv 2 V out V out + S eqx X Y C f + C f V r + M 1 M 2 V in + Vin M 3 M 4 V r CK S b1 CK S b2 S 1, 2 : 1.8/0.6 S 3, 4 : 3.0/0.6 S eq : 2.4/0.6 S eqx : 3.0/0.6 S b1, b2 : 6.0/0.6 M 1, -- M 4 : 10.8/0.6 C + f, f : 8 ff M 5, -- M 8 : 2.4/0.6 Inv 1,2 : p-- 4.8/0.6, n-- 1.2/0.6 Figure 4.6 Comparator used in the first stage (CMP_A). The third property of the comparator is that the effect of the offsets due to the cross-coupled transistors is reduced by the dynamic gain of the input stage. This effect can be described in two phases. This is because when CK goes high, nodes X, Y, P, and Q are precharged to V DD and M 5 - M 8 are off. The input difference is therefore amplified by M 1 - M 4 and the parasitic capacitances at nodes X and Y until V x and V y drop below V DD by V THN.At 50

63 this point, M 7 and M 8 turn on but M 5 and M 6 are still off. The amplification then continues while M 5 and M 6 contribute a small regenerative gain until M 5 and M 6 turn on, and initiate the final regeneration. Using SPICE, it is possible to calculate the contribution of M 5 - M 6 and M 7 - M 8 to the input-referred offset. With the device dimensions chosen in this design, simulations suggest that the offset voltages of M 5 and M 6 is divided by a factor of 20 and that of M 7 and M 8 by a factor of 2. Since the channel area of M 7 and M 8 is about one fourth of that of the input devices, they contribute roughly equal amounts of inputreferred offset. The overall offset of the comparator is about 10 mv. Another important phenomenon in the comparator is the large kickback noise produced at the beginning of reset and regeneration modes. This effect is particularly critical in the first stage and can introduce significant dynamic offsets, saturating the second stage and creating nonlinearity. Adding a pair of cross-coupled capacitors with proper value (around 8 ff) at the input reduces the kickback noise to an acceptable level. As shown in Fig. 4.7, the comparators in stages 2 to 5 are basically the same as that in the first stage, except for the input network. The multiplexers consisting of S i1 - S i4 select the even- or odd-channel signals in a dual-channel interleaving mode. Due to the accumulative gain after stage 1, larger comparator offsets can be tolerated in stages 2 to 5. Therefore, the input differential pair uses W/L = 5.4 µm/0.6 µm. 51

64 CK S 1 M 5 CK M 6 S 2 CK Inv 1 V out + V out - CK S 3 M 3 M 4 S 4 CK Inv 2 V ie + CK _2ec S i1 CK M 1 M 2 S i3 CK _2ec V ie V io + S i2 S i4 V io CK _2oc CK S b CK _2oc S 1, 2 : 1.8/0.6 S eq : 2.4/0.6 S b : 6.0/0.6 S 3, 4 : 3.0/0.6 S eqx : 3.0/0.6 S i1-i4 : 4.8/0.6 M 1 -- M 2 : 5.4/0.6 M 3 -- M 6 : 2.4/0.6 Inv 1,2 : p-- 4.8/0.6, n-- 1.2/0.6 Figure 4.7 Comparator used in stages 2 to 5 (CMP_B). Unlike the first stage, the comparators in stages 2 to 5 do not share the same input line because they are driven by the interpolation amplifier outputs. Thus, the kickback noise is less important here. 52

65 4.5 Clock Edge Reassignment The clock edge reassignment (CERA) circuit for a dual-channel system is shown in Fig With proper control signals, S pe and S po pass the rising edges and S no and S ne pass the falling edges of the master clock to SHA 1 and SHA 2, respectively. When V odd is high, S no and S po are on, allowing SHA 1 to receive a falling edge from A 2 and SHA 2 a rising edge from A 1. When V even is high, the reverse occurs. The falling edge of A 1 and the rising edge of A 2 are discarded. CK A 1 CK 1x S pe S po SHA 1 CK 1 CK 2 SHA 2 A 2 S no Sne CK 2x V odd V even Figure 4.8 Clock edge reassignment circuit for a dual-channel system. The operation of the CERA circuit is further illustrated in Fig The circuit operates in two pass modes and one block mode. During the block mode, the clock signals inside SHA 1 or SHA 2 are stored on the parasitic capacitance at each node. The clock edge reassignment concept can be easily extended to a multi-channel system as well. 53

66 V odd = High & V even = Low V odd = Low & V even = High CK A 1 CK 1x CK A 1 S po S pe SHA 1 CK 1 SHA 2 CK 2 SHA 1 SHA 2 A 2 CK 2x S no A 2 S ne V odd & V even = Low Holding SHA 1 SHA V odd Odd V even Even CK 1x (from A 1 ) CK 2x (from A 2 ) CK 1 CK 2 T T Figure 4.9 Operational diagram of a dual-channel CERA system. 54

67 4.6 Control and Decode Circuit As shown in Fig. 4.10, the control circuit (NAND_FF) senses the outputs of two adjacent comparators to generate three control signals, two applied to the MUX, and one to the ROM. The two-input NAND gate performs 1-of-n encoding and its output drives a D-type flip-flop, which produces the digital output at the falling edge of CK. With the assertion of either CK ey or CK oy, the control signal is routed to either the evenchannel MUX or the odd-channel MUX, performing interleaving operation in stages 2 to 5. O a2 + O a2 - CMP O + dax2 O - dax2 O dax1 + D 1 D 2 D Q NAND_FF O e2- O o2- O d2 To MUX To ROM CK CK ey CKoy Figure 4.10 Block diagram of NAND_FF with comparator. The detailed circuit of NAND_FF is shown in Fig The core is based on a TSPC flip-flop structure [38]. The dual-input NAND is merged into the input stage of the D-FF, while the two interleave-control NANDs are combined with the D-FF output stage. INV3 and INV4 are scaled to drive the heavy capacitive load inside MUXs with reasonable delay. 55

68 M 1 M 2 M 6 M 9 Inv 1 Inv 3 D 1 Oe- D 2 M 3 M 7 M 10 M 4 M 13 ND M 5 M 8 Od CK CK _2ey M 11 Inv 2 Inv 4 Oo- CK _2oy M 12 M 1 - M 3 : 1.8/0.6 M 4 - M 5 : 3.0/0.6 M 6 - M 7 : 2.4/0.6 M 8 : 1.2/0.6 M 9 - M 12 : 1.8/0.6 M 13 - M 14 : 3.6/0.6 M 14 Inv 1,2 : p- 4.8/0.6; n- 2.4/0.6 Inv 3,4 : p- 19.2/0.6; n- 9.6/0.6 ND : p- 4.8/0.6; n- 2.4/0.6 Figure 4.11 Details of NAND_FF 56

69 4.7 ROM and Output Stage The ROM consists of a dynamic digital circuit with a precharging PMOS as shown in Fig ROM R o M p D x D out PAD D in M x D Q D Q M o M n CK c M p : 9.0/0.6 M x : 2.4/0.6 M n : 14.4/0.6 M o : 18/0.6 R o : 100 Ω Figure 4.12 ROM and output stage. When CK c is low, M p precharges the output node D x and M x is controlled by D in. When CK c goes high, M p turns off and M n turns on. The output D x is then evaluated and fed to the following pipelined register array and eventually the output driver. The registers consist of dynamic TSPC D flip-flops. The output driver is an open-drain NMOS device producing a current of about 6 ma. The current is drawn from an off-chip termination resistor of 100 Ω, generating 57

70 a voltage swing of 600 mv, a value sufficient for driving off-chip ECL buffers. The small voltage swings allow sharp edges in the output data waveforms even with the large capacitance due to the traces on the printed-circuit (PC) board. One dedicated ground pad is used for all of the output drivers to ensure that the large ground bounce does not disturb the sensitive analog sections. 4.8 Clock Generator In a high-speed ADC system, the clock generator requires special attention. As shown in Fig. 4.13, the clock generator contains four building blocks: two divide-bytwo circuits (DIV 2a and DIV 2b ), one divide-by-three circuit (DIV 3 ), and an output buffer section (BUF). The 300-MHz differential master clock signals, CK in and CK in, drive DIV 2a and the output flip-flop of DIV 2b. DIV 2a produces 150-MHz outputs that are applied to DIV 2b and DIV 3. DIV 2b generates 75-MHz clocks required for interleaving the interpolative stages and DIV 3 produces 50-MHz clocks used in the triple-channel frontend SHA. The BUF section generates CK a1, CK a2, CK _3a, CK _3b, CK _3c for the front-end SHAs, CK _2ec, CK _2oc, CK _2ey, CK _2oy for the dual-channel interleaving interpolative stages, and CK and CK c for the comparators and the pipelining registers. The BUF section is actually laid out in different parts of the chip, in proximity to the related sections. 58

71 DIV 2b DIV 2a o_2f ick+ CK in D Q D Q D Q o_2f CK in D Q 1 o_2b D Q 2 + D Q ick D D Q Q Q D Q D o_2b DIV 3 o_2c 2 + o_2b 2 o_4c+ o_4c D Q D Q D Q o_2c 1 unity INV = BUF Local BUFs x16 4x16 4x4 4x4 4x16 4x16 CK a1 CK a2 CK_ 3a CK_ 3b CK_ 3c CK c CK CK _2ec CK _2oc CK _2ey CK _2oy Figure 4.13 Clock generator. 59

72 Figure 4.14 shows the high-speed differential D-type latch used in the two divide-by-two circuits. With the device dimensions shown here, the latch operates at clock frequencies as high as 400 MHz. M 5 M 3 M 6 M 4 Q Q D M 1 M 2 D CK c M n M 1 - M 6 : 3.0/0.6 M n : 12/0.6 Figure 4.14 High-speed differential D latch. 4.9 One Slice of First-Stage Signal Path Figure 4.15 shows the realization of a slice of the signal path in the first stage. While interpolation by a factor of 2 tolerates large nonlinearity in differential pairs, the reinterpolation scheme does require tighter linearity. Hence, the differential amplifiers in the signal path employ resistive degeneration. The actual design is fully differential. It is also important to note that the converter requires no floating capacitors and can therefore utilize native metal-sandwich structures in digital CMOS technologies. 60

73 Even Channel V DD V in Slide Command Control Logic Interleave Command Odd Channel Figure 4.15 Realization of a slice of the signal path in the first stage. The entire ADC is simulated at the transistor level by StarSim (previously called ADM), a SPICE-like simulator. The result for typical process parameters and at room temperature is shown in Fig

74 db f samp = MHz SNDR = db HD3 = db f in = MHz ( 31/128 * f samp ) Frequency (MHz) (a) Volt Sample (Time) (b) Figure 4.16 Simulated output of the 8-bit ADC. 62

75 4.10 Floor Plan And Layout Considerations The floor plan and layout of the ADC must deal with issues such as: routing of critical paths, power and ground isolation, noise coupling from the digital sections to the analog sections, etc. Due to the nature of sliding interpolation, the high-speed digital control signals must travel through the analog sections. Also, the sub_adcs in stages 2 to 5 must be embedded with the interpolating stages. These issues underscore the importance of careful layout to suppress various noise coupling effects. Figure 4.17 shows the floor plan of the ADC. In order to reduce the wiring capacitance in the critical path, the front-end building blocks in the first stage (CMP_A, reference ladder, preamplifiers, MUX, and the distributed sample-and-hold) are folded into a U shape. The front-end SHA output and the reference ladder are routed between the comparator bank (CMP_A) and the preamplifier bank. The reference ladder is made of silicide poly-resistor with a length of two squares (about 8 Ω) between consecutive taps. Each preamplifier provides an empty stripe so that the digital control signals from CMP_A to MUX can run through it without interfering with the analog signal path. The digital signals have also been shielded on both sides with analog ground along the entire path. The ROM generates the four corresponding digital bits in the first stage. 63

76 ROM CMP_A SHA Reference Ladder Preamp Clock Generator 18 even/odd -1 e/o 17 e/o 0 e/o 16 e/o 1 e/o 15 e/o 2 e/o 14 e/o 3 e/o 13 e/o 4 e/o 12 e/o 5 e/o 11 e/o 6 e/o 10 e/o 7 e/o 9 e/o 8 e/o MUX & Distributed Sampling Interpolation Amp Amp2 5 (e) 5 (o) 4 (e) 4 (o) 3 (e) 3 (o) 2 (e) 2 (o) 1 (e) 1 (o) 7 (e) 7 (o) 6 (e) 6 (o) 5 (e) 5 (o) 4 (e) 4 (o) 3 (e) 3 (o) 2 (e) 2 (o) 1 (e) 1 (o) Stage 2 CMP_B MUX & Distributed Sampling ROM 7 (e) 7 (o) 6 (e) 6 (o) 5 (e) 5 (o) 4 (e) 4 (o) 3 (e) 3 (o) 2 (e) 2 (o) 1 (e) 1 (o) Figure 4.17 Layout floor plan. The MUX outputs are connected to metal-3 lines running vertically. Each differential analog output pair is shielded by analog V DD lines on both sides, providing isolation and forming the sampling capacitor as well. The even and the odd channels are uniformly distributed within this building block. Amp2 performs reinterpolation and contains 5 dual-channel sets which sense the outputs of the MUX and subsequently reinterpolate the new outputs to drive the next stage. 64

77 A more detailed diagram of the first stage is shown in Fig Note that the positioning of preamplifiers 1, 2, 3 and 13, 14, 15 creates a U-shaped layout. This strategy is chosen because preamplifiers 1 and 15 share the same reference voltages, etc. The actual sliding/multiplexing mechanism is depicted in more detail for the lower and upper banks in Fig and Fig. 4.20, respectively. The sliding/interleaving command reaches a unit cell (in the middle column) in each slice from the left and then connects to the cells in the adjacent two slices above and below. Stage 2 consists of reinterpolation and interpolation amplifiers, and another MUX and distributed sampling circuit. All of these circuits are in differential and dualchannel form. Only three comparators are required in CMP_B to decide which sections are needed to provide the zero-crossing information to the following stage. The ROM creates the two bits based on the results of the comparators. Stages 3 to 5 are identical to stage 2. Since all of the switches in the MUX are PMOS devices, a large n-well is used to accommodate them. With properly-spaced substrate contacts, the n-well isolates the switches from the noisy common p-substrate. 65

78 V in V ref V ref + V in + (even) V o1 (odd) (even) V o2 (odd) (even) V o3 (odd) Cntl even unit cell 1 Cntl odd 15 Cntl even 2 Cntl odd 14 Cntl even 3 Cntl odd 13 Cntl even CMP_A Preamps MUX NAND_FF Figure 4.18 Detailed circuit arrangement in the first stage. 66

79 (even) V o2 (odd) (even) V o3 (odd) (even) V o4 (odd) Figure 4.19 Sliding/multiplexing mechanism of the lower bank. 67

80 (even) V o2 (odd) (even) V o3 (odd) (even) V o4 (odd) Figure 4.20 Sliding/multiplexing mechanism of the upper bank. 68

81 SHA Clock Generator Interpolation Amp ADC2 CK in + CK in Ref Ladder V in + V in ADC1 Preamp MUX Reinterpolation Amp Stage 3 Stage 5 Stage 4 Figure 4.21 Die photo. Fig shows the die photo. The chip size is 1.5 mm x 1.2 mm with the active area about 1.2 mm 2. The analog differential input signals, V + in and V in, enter from the left side of the chip and are shielded with a common V DD in metal 2. Digital outputs leave the chip from the lower and the right sides of the chip. Three different power lines 69