Flash ADC (Part-I) Architecture & Challenges

Transcription

1 project synopsis In The Name of Almighty Lec. 4: Flash ADC (PartI) Architecture & Challenges Lecturer: Samaneh Babayan Integrated Circuit Lab. Department of Computer Science & Engineering ImamReza University of Mashhad Sep. 015.

2 In The Name of Almighty Lec. 4: Flash ADC (PartI) Architecture & Challenges Lecturer: Hooman Farkhani Department of Electrical Engineering Islamic Azad University of Najafabad Feb

3 Analog to Digital Converters NyquistRate ADCs Flash ADCs SubRanging ADCs Folding/ Interpolating ADCs Pipelined ADCs Successive Approximation ADCs (SAADCs) Integrating (serial) ADCs Oversampling ADCs DeltaSigma based ADCs 3

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5 Conversion Principles Principle Resolution Speed Cost Serial Conversion High >1 Bit Low <1kHz Low Successive Approximation Medium 814 Bit Medium <100MHz Medium Parallel Conversion Low 610 Bit High >100MHz High Delta Sigma High >1 Bit LowMedium <1MHz Low (analog only) 5

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7 ADC Architectures Flash ADCs: High speed, but large area and high power dissipation. Suitable for lowmedium resolution (610 bit). SubRanging ADCs: Require exponentially fewer comparators than Flash ADCs. Hence, they consume less silicon area and less power. Pipelined ADCs: Mediumhigh resolution with good speed. The tradeoffs are latency and power. Successive Approximation ADCs: Moderate speed with mediumhigh resolution (814 bit). Compact implementation. Integrating ADCs or Ramp ADCs: Low speed but high resolution. Simple circuitry. DeltaSigma based ADCs: Moderate bandwidth due to oversampling, but very high resolution thanks to oversampling and noise shaping. 7

8 ADC Architectures 8

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10 Flash ADC i 1 0 FS 7Δ 6Δ 5Δ Δ Δ D o 0 FS i Strobe f s N 1 comparators Encoder D out Advantrages 1. Conceptually most straightfor ward One clock cycle / conversion highest possible speed. resolution: 3 ~ 8 bits 3. clock rates 0 MHz ~ tens of G Hz Disadvantages: 1. ( N 1) comparators required Hardware complexity grows exponentially with resolution. Comparator offset limit the resolution 3. Large Power Consumption 4. Complex Layout Issues 10

11 Flash ADC Thermometer Code FS i Strobe Thermometer code b b 1 b 0 f s N 1 comparators 1ofn code ROM encoder

12 Flash ADC Challenges High Complexity ( N 1 Comparators): consumes large area high input capacitor Large power consumption Large comparators needed for removing offset. Limited to the resolution of 48 Bits. Speed limited by single comparator plus encoding logic. 1 1m σ DD = bit FS = 1 DNL < 0.5 LSB 0.5 m = 35 σ 103 comparators 1 LSB = 1 m s < 0.5 LSB σ = m 1 1

13 Flash ADC Challenges 18 os, max [m] 3 8 FS = 1 FS = DNL < 0.5 LSB Large FS relaxes offset tolerance Small FS benefits conversion speed (settling, linearity of building blocks) N [bits] 13 13

14 A Typical CMOS Comparator DD s derives from: M 3 M 4 M 5 M 6 Preamp input pair i s M 1 M Φ M 9 mismatch ( th,w,l) PMOS loads and current mirror Latch mismatch M 7 M 8 CI / CF imbalance of M 9 Preamp SS Latch Clock routing Parasitics 14

15 Latch Regeneration DD M 5 M 6 Φ PA tracking Latch reseting Latch regenrating C L Φ M 9 C L DD M 7 M 8 SS SS Exponential regeneration due to positive feedback of M 7 and M

16 Regeneration Speed Linear Model C L M 7 M 8 C L C L g m 1 o o g o m o /sc L 1 1 g m 1 /sc L o o 0 Δ s g m /sc L 1 0 s p g m /C L, singlerhppole t 0 t 0exp t g o o m/cl 16 16

17 Reg. Speed Linear Model C L M 7 M 8 C L (t=0) t = 1 (t=0) t/(c L /g m ) 1 100m m m 6.9 t C g L m t o ln o t μ

18 Reg. Speed Linear Model M 3 M 4 m M 5 M 6 m g m5 m g m5 m i m M 1 M m x M 7 Φ=1 M 9 M 8 R 9 R 9 X 1 1 g m7 g m7 A 1 g g m1 m3 A gm5r9 g R m7 9, R 9 1 g m7 to beamplifier. o 0 i 0 A i 0 A1A t 0 A A exp t g o i 1 m/cl 18 18

19 Comparator Metastability Φ T/ t 0 A A exp t g o i 1 m/cl Curve A 1 A i (t=0) m 10 1 m μ μ Comparator fails to produce valid logic outputs within T/ when input falls into a r egion that is sufficiently close to the comparator threshold 19 19

20 Comparator Metastability Δ D o j1 Assuming that the input is uniformly di stributed over FS, then i BER Δ 1LSB j t 0 A A exp t g o i 1 m/cl s Cascade preamp stages (typical flash comparator has 3 PA stages) Use pipelined multistage latches; PA can be pipelined too Avoid branching off comparator logic outputs 0 0

21 Comparator Metastability i x Logic levels can be misinterpreted by digital gates (branching off, diff. outputs) even a wrong decision is better than no decision! 1 1

22 CI and CF in Latch M 5 M 6 Φ Φ C L C gs M 9 C gd C L CM jump M 7 M 8 Charge injection and clock feedthrough introduce CM jump in and Dynamic latches are more susceptible to CI and CF errors

23 Dynamic Offset of Latch Φ Dynamic offset derives from: Imbalanced CI and CF Imbalanced load capacitance Mismatch b/t M 7 and M 8 Mismatch b/t M 5 and M 6 Clock routing 0.5 CMjump 10%imbalance 50mffset Dynamic offset is usually the dominant offset error in latches 3 3

24 Typical CMOS Comparator DD Inputreferred latch M 3 M 4 M 5 M 6 offset gets divided by s Φ the gain of PA Preamp introduces i M 1 M M 9 its own offset (mostly static due to th, W, M 7 M 8 and L mismatches) PA also reduces SS kickback noise Preamp Latch Kickback noise disturbs reference voltages, must settle before next sample 4 4

25 Comparator Offset DD M 3 M 4 M 5 M 6 Differential pair mismatch: i s M 1 M Φ M 9 os Δ th 1 4 ov ΔW W ΔL L SS M 7 M 8 A 1 g g m1 m3 A gm5r9 g R m7 9 Preamp Latch Total inputreferred comparator offset: os os,1 os,34 A os,56 1 A os,78 1 A A os,dyn 1 A 5 5

26 Matching Properties Suppose parameter P of two rectangular devices has a mismatch error of ΔP. The variance of parameter ΔP b/t the two devices is σ A WL P ΔP S D, P 1 st term dominates for small devices where, W and L are the effective width and length, D is the distance A Threshold: σ = S D WL σ β A Current factor : β WL th th th β Sβ D Ref: M. J. M. Pelgrom, et al., Matching properties of MOS transistors, IEEE Journal o f SolidState Circuits, vol. 4, pp , issue 5,

27 Why Large Devices Match Better? W R 1 R X X X X X X X X L 10 identical resistors L R R with std σ W 1 S R1 L R RS 10 10R 1 with std σ R, W 10 R R j R1 R R1 j1 σ σ 10σ σ 10σ σ R 10σR1 1 σr1 σr 1 1 R 10R1 10 R1 R A WL Spatial averaging 7 7

28 ADC Input Capacitance A σ C 10 ff / WL th th g μm N = 6 bits FS = 1 σ = LSB/4 A T0 = 10 m μm 63 comparators 1 LSB = 16 m σ = 4 m L = 0.4 μm, W = 6 μm N (bits) # of comp. C in (pf) ??! Small s leads to large device sizes, hence large area and power Large comparator leads to large input capacitance, difficult to drive and difficult to m aintain tracking bandwidth 8 8

29 Refernces Professor Boris Murmann Course slides 01, Stanford University EE315B course Dr. Reza Lotfi, ADC course slides