Administrative. No office hour on Thurs. this week Instead, office hour 3 to 4pm on Wed.

Size: px
Start display at page:

Download "Administrative. No office hour on Thurs. this week Instead, office hour 3 to 4pm on Wed."

Transcription

1 Administrative No office hour on Thurs. this week Instead, office hour 3 to 4pm on Wed. EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page EE247 Lecture 2 ADC Converters Sampling (continued) Effect of clock jitter on sampling ADC architectures and design Serial- slope type Successive approximation Flash Flash ADC sources of error Sparkle code Meta-stability Comparator design EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 2

2 Summary Last Lecture ADC Converters Sampling (continued) Sampling switch charge injection & clock feedthrough Complementary switch Use of dummy device Bottom-plate switching Track & hold Flip-around T/H circuit T/H combined with summing/difference function T/H circuit incorporating gain & offset cancellation T/H aperture uncertainty EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 3 Effect of Clock Jitter So far assumption was that the clock signal controlling the sampling instants has no variability and have their edges spaced exactly equal to T s /2 In practice the clock edges are not prefectly spaced and have some level of jitter Variability in T s causes errors in data converter performance "Aperture Uncertainty" or "Aperture Jitter Question: for a given application how much clock jitter can be tolerated? EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 4

3 Clock Jitter Sampling jitter adds an error voltage proportional to the product of (t J -t ) and the derivative of the input signal at the sampling instant x(t) x (t ) actual sampling time t J Jitter doesn t matter when sampling dc signals (x (t )=) nominal (ideal) sampling time t EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 5 Clock Jitter The error voltage is e = x (t )(t J t ) x(t) x (t ) error actual sampling time t J nominal sampling time t EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 6

4 Jitter Example Sinusoidal input: Amplitude: A Frequency: Jitter: f x dt max ( π ) x( t ) = A s i n 2 f t x x x max x ( π ) x'(t ) = 2π f Acos 2 f t x'(t ) 2π f A Thus: e( t ) x' ( t ) d t e( t ) 2π f A d t x Worst case error: A= AFS f fs x = 2 2 Δ AFS e( t ) << B+ 2 2 dt << B 2 π f # of Bits 6 2 s f s MHz MHz MHz dt <<.5 ps.8 ps.3 ps EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 7 Law of Jitter The worst case looks pretty stringent what about the average? Let s calculate the mean squared jitter error (variance) If we re sampling a sinusoidal signal x(t) = Asin(2πf x t), then x (t) = 2πf x Acos(2πf x t) E{[x (t)] 2 } = 2π 2 f x2 A 2 Assume the jitter has variance E{(t J -t ) 2 } = τ 2 EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 8

5 Law of Jitter If x (t) and the jitter are independent E{[x (t)(t J -t )] 2 }= E{[x (t)] 2 } E{(t J -t ) 2 } Hence, the jitter error power is E{e 2 } = 2π 2 f x2 A 2 τ 2 If the jitter is uncorrelated from sample to sample, this jitter noise is white EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 9 Law of Jitter DR jitter 2 A / 2 = π f A τ x = π f τ x = 2log ( 2πf τ ) x Example: ENOB=2bit f in =35MHz τ<ps rms! EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page

6 Clock Jitter Conclusion The first requirement is to have a good enough clock generator Clock signal should be handled carefully on-chip to prevent additional excessive jitter Usually, clock jitter in the single-digit pico-second range can be prevented by appropriate design techniques: Separate supplies Separate analog and digital clocks Short inverter chains between clock source and destination Few, if any, other analog-to-digital conversion non-idealities have the same symptoms as sampling jitter: RMS noise proportional to input frequency RMS noise proportional to input amplitude In cases where clock jitter limits the dynamic range, it s easy to tell, but may be difficult to fix... EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page ADC Architecture & Design EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 2

7 ADC Architectures Slope type converters Successive approximation Flash Time-interleaved / parallel converter Folding Residue type ADCs Two-step Pipeline Oversampled ADCs EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 3 Various ADC Architectures Resolution/Conversion Rate Resolution Oversampled & Serial Algorithmic e.g. Succ. Approx. Subranging e.g. Pipelined Folding & Interpolative Parallel & Time Interleaved Conversion Rate EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 4

8 Serial ADC Single Slope V Ramp Ramp Generator V Ramp V IN "" stop start B..B N.. Counter Clock Time Counter starts V Ramp = Counter stops counting for V IN =V Ramp Counter output proportional to V IN EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 5 Single Slope ADC Advantages: Low complexity & simple INL depends on ramp linearity & not component matching Inherently monotonic Disadvantages: Slow (2 N clock pulses for N-bit conversion) (e.g. N=6 f clock =MHz needs 65xμs=65ms/conversion) Hard to generate precise ramp required for high resolution ADCs Need to calibrate ramp slope versus V IN Better: Dual Slope, Multi-Slope EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 6

9 Serial ADC Dual Slope V IN V "" Integrator o -V REF Flip Flop Clock B..B N.. Counter & Timing First: V IN is integrated for a fixed time (2 N xt CLK ) V o = 2 N xt CLK V IN /τ intg Next: V o is de-integrated with V REF until V o = Counter output = 2 N V IN /V REF EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 7 Dual Slope ADC Slope α V IN Slope = Const. Integrate V in for fixed time (T INT ), de-integrate with V REF applied T De-Int ~ 2 Nx T CLK xv in /V REF Most laboratory DVMs use this type of ADC EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 8

10 Dual Slope ADC Advantage: Accuracy to st order independent of integrator time-constant and clock period Comparator offset referred to input is attenuated by integrator high DC gain Insensitive to most linear error sources DNL is a function of clock jitter Power line (6Hz) xtalk effect on reading can be canceled by: choosing conversion time multiple of /6Hz High accuracy achievable (6+bit) Disadvantage: Slow (maximum 2x2 N xt clk per conversion) Integrator opamp offset results in ADC offset (can cancel) Finite opamp gain gives rise to INL EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 9 Successive Approximation ADC SAR Algorithmic type ADC Based on binary search over DAC output Reset DAC Set DAC[MSB]= V IN T/H MSB Y V IN >V DAC? N MSB V REF DAC Set DAC[MSB-]= Control Logic Clock [MSB-] [LSB] Y Y V IN >V DAC?. V IN >V DAC? N [MSB-] N [LSB] DAC[Input]= ADC[Output] EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 2

11 Successive Approximation ADC Example: 6-bit ADC & V IN =5/8V REF V IN T/H V REF Control Logic Clock DAC + - 3/4 5/8 /2 V DAC /V REF /2 3/4 5/8 /6 2/32 4/64 Test MSB V IN DAC Output Test MSB- ADC Time / Clock Ticks High accuracy achievable (6+ Bits) Required N clock cycles for N-bit conversion (much faster than slope type) Moderate speed proportional to N (typically MHz range) EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 2 Example: SAR ADC Charge Redistribution Type S top Comparator 32C 6C 8C 4C 2C C C - Out b 4 (MSB) b 3 b 3 b 2 b b V in Control To Logic switches V REF V in Built with binary weighted capacitors, switches, comparator & control logic T/H inherent in DAC EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 22

12 Charge Redistribution Type SAR DAC Operation: MSB 32C 32C 32C -V in +V REF /2 32C - Comparator Out b 4 (MSB) V in Phase b 3 -b V REF b 4 (MSB) b 3 -b Phase 2 To switches Control Logic Operation starts by connecting all top plate to gnd and all bottom plates to V in To test the MSB all top plate are opened bottom plate of 32C connected to V REF & rest of bottom plates connected to ground input to comparator= -V in +V REF /2 Comparator is strobed to determine the polarity of input signal: If negative MSB=, else MSB= The process continues until all bits are determined EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 23 Example: SAR ADC Charge Redistribution Type reset C P -Comparator 32C 6C 8C 4C 2C C C Out b 4 (msb) b 3 b 3 b 2 b b V in Control Logic To switches V REF V in To st order parasitic (C p ) insensitive since top plate driven from initial to final by the global negative feedback Linearity is a function of accuracy of C ratios Possible to add a C ratio calibration cycle (see Ref.) Ref: H. Lee, D. A. Hodges, and P. R. Gray, "A self-calibrating 5 bit CMOS A/D converter," IEEE Journal of Solid-State Circuits, vol. 9, pp , December 984. EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 24

13 B-bit flash ADC: DAC generates all possible 2 B - levels 2 B - comparators compare V IN to DAC outputs Comparator output: If V DAC < V IN If V DAC > V IN Comparator outputs form thermometer code Encoder converts thermometer to binary code Flash ADC V REF V IN f s D A C B - B Encoder Digital Output EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 25 Flash ADC Converter Example: 3-bit Conversion V IN V IN V REF V REF f s Thermometer code Encoder Binary B-bits T s Time EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 26

14 Flash Converter Characteristics Very fast: only clock cycle per conversion ½ clock cycle V IN & V DAC comparison ½ clock cycle 2 B - to B encoding High complexity: 2 B - comparators V IN V REF f s Encoder Input capacitance of 2 B - comparators connected to the input node: High input node Thermometer code B-bits EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 27 Flash Converter Sources of Error V REF V IN f s R/2 R R R R R/2. Encoder Digital Output Comparator input: Offset Nonlinear input capacitance Kickback noise (disturbs reference) Signal dependent sampling time Comparator output: Sparkle codes ( ) Metastability EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 28

15 Flash Converter Example: 8-bit ADC 8-bit 255 comparators R/2 V REF V IN f s V REF =V LSB=4mV R DNL</2LSB Comparator input referred offset < 2mV R R. Encoder Digital Output Assuming close to % yield, 2mV =6σ offset σ offset <.33mV R R/2 EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 29 Flash ADC Converter Example: 8-bits ADC (continued) σ Offset <.33mV Let us assume in the technology used: Voffset-per-unit-sqrt(WxL)=3 mvx μ 3mV 2 V ffset = =.33mV W L = 83μ W L 2 2 Assuming: Cox = 9 ff/ μ CGS = CoxW L= 496 ff 3 Total input capacitance: = 26.5 pf! Issues: Si area quite large Large input capacitance Since depending on input voltage different number of comparator input transistors would be on/off- total input capacitance varies as input varies Nonlinear input capacitance could give rise to signal distortion Ref: M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, "Matching properties of MOS transistors," IEEE Journal of Solid-State Circuits, vol. 24, pp , October 989. EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 3

16 Flash ADC Converter Example (continued) Trade-offs: Allowing larger DNL e.g. LSB instead of.5lsb: Increases the maximum allowable input-referred offset voltage by a factor of 2 Decreases the required device WxL by a factor of 4 Reduces the input device area by a factor of 4 Reduces the input capacitance by a factor of 4! Reducing the ADC resolution by -bit Increases the maximum allowable input-referred offset voltage by a factor of 2 Decreases the required device WxL by a factor of 4 Reduces the input device area by a factor of 4 Reduce the input capacitance by a factor of 4 EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 3 Flash Converter Comparator Tolerable Maximum Offset versus ADC Resolution Assumption: DNL=.5LSB Note: Graph shows max. tolerable offset, note that depending on min acceptable yield, the derived offset numbers are associated with 2σ to 6σ offset voltage Maximum Comparator V offset [mv] 2 - V REF =2V V REF =V ADC Resolution EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 32

17 Typical Flash Output Encoder V DD Thermometer code -of-n code b3 b2 b b Binary B-bits Thermometer to Binary encoder ROM Thermometer code -of-n decoding Final encoding NOR ROM Ideally, for each code, only one ROM row is on b3 b2 b b Output EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 33 Sparkle Codes V DD Erroneous (comparator offset?) b3 b2 b b Correct Output: Problem: Two rows are on Erroneous Output: Up to ~ ½ FS error!! EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 34

18 Sparkle Tolerant Encoder Protects against a single sparkle. Ref: C. Mangelsdorf et al, A 4-MHz Flash Converter with Error Correction, JSSC February 99, pp EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 35 Meta-Stability Different gates interpret metastable output X differently X Correct output: Erroneous output: Solutions: Latches (high power) Gray encoding Ref: C. Portmann and T. Meng, Power-Efficient Metastability Error Reduction in CMOS Flash A/D Converters, JSSC August 996, pp EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 36

19 Gray Encoding Example: 3bit ADC Thermometer Code Gray Binary T T 2 T 3 T 4 T 5 T 6 T 7 G 3 G 2 G B 3 B 2 B G G G 2 3 = T T + T T = T T = T Each T i affects only one G i Avoids disagreement of interpretation by multiple gates Protects also against sparkles Follow Gray encoder by (latch and) binary encoder EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 37 Voltage Comparators V DD V i+ V i V out (Digital Output) Play an important role in majority of ADCs Function: Compare the instantaneous value of two analog signals & generate a digital output voltage based on the sign of the difference: If V i+ -V i- > V out = If V i+ -V i- < V out = EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 38

20 Voltage Comparator Architectures Comparator architectures High gain amplifier with differential analog input & single-ended large swing output Output swing compatible with driving digital logic circuits Open-loop amplification no frequency compensation required Precise gain not required Latched comparators; in response to a strobe, input stage disabled & digital output stored in a latch till next strobe Two options for implementation : Latch-only comparator Low-gain amplifier + high-sensitivity latch Sample-data comparators T/H input Offset cancellation EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 39 Comparators w/ High-Gain Amplification Amplify V in (min) to V DD V in (min) determined by ADC resolution Example: 2-bit ADC with: -V FS =.5V LSB=.36mV -V DD =.8V For.8V output &.5LSB precision: Min.8V Av =,.8mV EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 4

21 f u u Comparators -Single-Stage Amplification = unity-gain frequency, f =-3dB frequency fu f= o AV Example: f =GHz & A =, GHz fo = khz, τsettling = =.6μsec 2π fo Allowa few τ for output to settle Max. fclock 26kHz 5τ settling V o Gain f u =.-GHz f f u frequency Too slow for majority of applications! Try cascade of lower gain stages to broaden frequency of operation A v Assumption: Single pole amplifier EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 4 Comparators 2- Cascade of Open Loop Amplifiers The stages identical small-signal model for the cascades: One stage: EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 42

22 Open Loop Cascade of Amplifiers EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 43 Open Loop Cascade of Amplifiers For A T (DC) =, Example: N=3, f =GHz & A () = u GHz /3 fon = MHz /3 (,) τ settling = = 7nsec 2π f Max. Clock o A llowa few τ for output to settle f 29MHz 5τ settling T f max improved from 26kHz to 29MHz X236 EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 44

23 Open Loop Cascade of Amplifiers Offset Voltage From offset point of view high gain/stage is preferred Choice of # of stage bandwidth vs offset tradeoff Input-referred offset EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 45 Open Loop Cascade of Amplifiers Step Response Assuming linear behavior t EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 46

24 Open Loop Cascade of Amplifiers Step Response Assuming linear behavior EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 47 Open Loop Cascade of Amplifiers Delay/(C/g m ) Minimum total delay broad function of N Relationship between # of stages resulting in minimize delay (N op ) and gain (V out /V in ) approximately: Delay/(C/g m ) N opt + log 2 A T for A< N opt.2lna T for A Ref: J.T. Wu, et al., A -MHz pipelined CMOS comparator IEEE Journal of Solid-State Circuits, vol. 23, pp , December 988. EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 48

25 Offset Cancellation In sampled-data cascade of amplifiers Vos can be cancelled Store on ac-coupling caps in series with amp stages Offset associated with a specific amp can be cancelled by storing it in series with either the input or the output of that stage Offset can be cancelled by adding a pair of auxiliary inputs to the amplifier and storing the offset on capacitors connected to the aux. inputs during offset cancellation phase Ref: J.T. Wu, et al., A -MHz pipelined CMOS comparator IEEE Journal of Solid-State Circuits, vol. 23, pp , December 988. EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 49 Offset Cancellation Output Series Cancellation Amp modeled as ideal + V os (input referred) Store offset: S, S4 open S2, S3 closed V C =AxV OS Ref: J.T. Wu, et al., A -MHz pipelined CMOS comparator IEEE Journal of Solid-State Circuits, vol. 23, pp , December 988. EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 5

26 Offset Cancellation Output Series Cancellation Amplify: S, S4 closed S2, S3 open V C =AxV OS Circuit requirements: Amp not saturate during offset storage High-impedance (C) load C c not discharged C c >> C L to avoid attenuation C c >> C switch offset due to charge injection EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 5 Offset Cancellation Cascaded Output Series Cancellation EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 52

27 Offset Cancellation Cascaded Output Series Cancellation - S open, S2,3,4,5 closed V C =A xv os V C2 =A 2 xv os2 V C3 =A xv os3 EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 53 Offset Cancellation Cascaded Output Series Cancellation 2- S3 open Feedthrough from S3 offset on X Switch offset, ε 2 induced on node X Since S4 remains closed, offset associated with ε 2 stored on C2 V X = ε 2 V C =A xv os - ε 2 V C2 =A 2 x(v os2 + ε 2 ) EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 54

28 Offset Cancellation Cascaded Output Series Cancellation 3- S4 open Feedthrough from S4 offset on Y Switch offset, ε 3 induces error on node Y Since S5 remains closed, offset associated with ε 3 stored on C3 V Y = ε 3 V C2 =A 2 x(v os2 + ε 2 ) - ε 3 V C3 =A 3 x(v os3 + ε 3 ) EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 55 Offset Cancellation Cascaded Output Series Cancellation 4- S2 open, S closed, S5 open S closed & S2 open since input connected to low impedance source charge injection not of major concern Switch offset, ε 4 introduced due to S5 opening EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 56

29 Offset Cancellation Cascaded Output Series Cancellation EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 57 Offset Cancellation Cascaded Output Series Cancellation Example: 3-stage open-loop differential amplifier with offset cancellation + output amplifier (see Ref.) A Total (DC) = 2x 6 = 2dB Input-referred offset < 5μV Ref: :R. Poujois and J. Borel, "A low drift fully integrated MOSFET operational amplifier," IEEE Journal of Solid- State Circuits, vol. 3, pp , August 978. EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 58

30 Offset Cancellation Output Series Cancellation Advantages: Almost compete cancellation Closed-loop stability not required Disadvantages: Gain per stage must be small Offset storage C in the signal path- could slow down overall performance EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 59 Offset Cancellation Input Series Cancellation Ref: :R. Poujois and J. Borel, "A low drift fully integrated MOSFET operational amplifier," IEEE Journal of Solid-State Circuits, vol. 3, pp , August 978. EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 6

31 Offset Cancellation Input Series Cancellation Store offset Note: Mandates closed-loop stability Ref: :R. Poujois and J. Borel, "A low drift fully integrated MOSFET operational amplifier," IEEE Journal of Solid-State Circuits, vol. 3, pp , August 978. EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 6 Amplify S2, S3 open S closed Offset Cancellation Input Series Cancellation Example: A=4 Input-referred offset =V os /5 EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 62

32 Offset Cancellation Cascaded Input Series Cancellation ε 2 charge injection associated with opening of S4 EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 63 Offset Cancellation Input Series Cancellation Advantages: In applications such as C-array successive approximation ADCs can use C-array to store offset Disadvantages: Cancellation not complete Requires closed loop stability Offset storage C in the signal path- could slow down overall performance EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 64

33 CMOS Comparators Cascade of Gain Stages Fully differential gain stages st order cancellation of switch feedthrough offset - Output series offset cancellation 2- Input series offset cancellation EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 65 CMOS Comparators Cascade of Gain Stages 3-Combined input & output series offset cancellation EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 66

34 Offset Cancellation Cancel offset by additional pair of inputs (Lecture 9 slide 35-37) EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 67

Summary of Last Lecture

Summary of Last Lecture EE247 Lecture 2 ADC Converters (continued) Successive approximation ADCs (continued) Flash ADC Flash ADC sources of error Sparkle code Meta-stability Comparator design EECS 247 Lecture 2: Data Converters

More information

EECS 247 Lecture 18: Data Converters- Track & Hold- ADC Design 2009 Page 1. EE247 Lecture 18

EECS 247 Lecture 18: Data Converters- Track & Hold- ADC Design 2009 Page 1. EE247 Lecture 18 EE247 Lecture 8 ADC Converters Sampling (continued) Bottom-plate switching Track & hold T/H circuits T/H combined with summing/difference function T/H circuit incorporating gain & offset cancellation T/H

More information

EE247 Lecture 20. Comparator architecture examples Flash ADC sources of error Sparkle code Meta-stability

EE247 Lecture 20. Comparator architecture examples Flash ADC sources of error Sparkle code Meta-stability EE247 Lecture 2 ADC Converters ADC architectures (continued) Comparator architectures Latched comparators Latched comparators incorporating preamplifier Sample-data comparators Offset cancellation Comparator

More information

EE247 Lecture 16. EECS 247 Lecture 16: Data Converters- DAC Design & Intro. to ADCs 2009 Page 1

EE247 Lecture 16. EECS 247 Lecture 16: Data Converters- DAC Design & Intro. to ADCs 2009 Page 1 EE47 Lecture 6 D/A Converters (continued) Self calibration techniques Current copiers (last lecture) Dynamic element matching DAC reconstruction filter ADC Converters Sampling Sampling switch considerations

More information

Tuesday, March 1st, 9:15 11:00. Snorre Aunet Nanoelectronics group Department of Informatics University of Oslo.

Tuesday, March 1st, 9:15 11:00. Snorre Aunet Nanoelectronics group Department of Informatics University of Oslo. Nyquist Analog to Digital it Converters Tuesday, March 1st, 9:15 11:00 Snorre Aunet (sa@ifi.uio.no) Nanoelectronics group Department of Informatics University of Oslo 3.1 Introduction 3.1.1 DAC applications

More information

Flash ADC (Part-I) Architecture & Challenges

Flash ADC (Part-I) Architecture & Challenges project synopsis In The Name of Almighty Lec. 4: Flash ADC (PartI) Architecture & Challenges Lecturer: Samaneh Babayan Integrated Circuit Lab. Department of Computer Science & Engineering ImamReza University

More information

High-Speed Analog to Digital Converters. ELCT 1003:High Speed ADCs

High-Speed Analog to Digital Converters. ELCT 1003:High Speed ADCs High-Speed Analog to Digital Converters Ann Kotkat Barbara Georgy Mahmoud Tantawi Ayman Sakr Heidi El-Feky Nourane Gamal 1 Outline Introduction. Process of ADC. ADC Specifications. Flash ADC. Pipelined

More information

Summary of Last Lecture

Summary of Last Lecture EE47 Lecture 7 DAC Converters (continued) Dynamic element matching DAC reconstruction filter ADC Converters Sampling Sampling switch considerations Thermal noise due to switch resistance Sampling switch

More information

CHAPTER 6 PHASE LOCKED LOOP ARCHITECTURE FOR ADC

CHAPTER 6 PHASE LOCKED LOOP ARCHITECTURE FOR ADC 138 CHAPTER 6 PHASE LOCKED LOOP ARCHITECTURE FOR ADC 6.1 INTRODUCTION The Clock generator is a circuit that produces the timing or the clock signal for the operation in sequential circuits. The circuit

More information

CMOS ADC & DAC Principles

CMOS ADC & DAC Principles CMOS ADC & DAC Principles Willy Sansen KULeuven, ESAT-MICAS Leuven, Belgium willy.sansen@esat.kuleuven.be Willy Sansen 10-05 201 Table of contents Definitions Digital-to-analog converters Resistive Capacitive

More information

Analog-to-Digital i Converters

Analog-to-Digital i Converters CSE 577 Spring 2011 Analog-to-Digital i Converters Jaehyun Lim, Kyusun Choi Department t of Computer Science and Engineering i The Pennsylvania State University ADC Glossary DNL (differential nonlinearity)

More information

Analogue to Digital Conversion

Analogue to Digital Conversion Analogue to Digital Conversion Turns electrical input (voltage/current) into numeric value Parameters and requirements Resolution the granularity of the digital values Integral NonLinearity proportionality

More information

Lecture 3 Switched-Capacitor Circuits Trevor Caldwell

Lecture 3 Switched-Capacitor Circuits Trevor Caldwell Advanced Analog Circuits Lecture 3 Switched-Capacitor Circuits Trevor Caldwell trevor.caldwell@analog.com Lecture Plan Date Lecture (Wednesday 2-4pm) Reference Homework 2017-01-11 1 MOD1 & MOD2 ST 2, 3,

More information

Summary Last Lecture

Summary Last Lecture Interleaved ADCs EE47 Lecture 4 Oversampled ADCs Why oversampling? Pulse-count modulation Sigma-delta modulation 1-Bit quantization Quantization error (noise) spectrum SQNR analysis Limit cycle oscillations

More information

EE247 Lecture 15. EE247 Lecture 15

EE247 Lecture 15. EE247 Lecture 15 EE47 Lecture 5 Administrative issues Midterm exam postponed to Tues. Oct. 8th o You can only bring one 8x paper with your own written notes (please do not photocopy) o No books, class or any other kind

More information

Lecture #6: Analog-to-Digital Converter

Lecture #6: Analog-to-Digital Converter Lecture #6: Analog-to-Digital Converter All electrical signals in the real world are analog, and their waveforms are continuous in time. Since most signal processing is done digitally in discrete time,

More information

Chapter 13: Introduction to Switched- Capacitor Circuits

Chapter 13: Introduction to Switched- Capacitor Circuits Chapter 13: Introduction to Switched- Capacitor Circuits 13.1 General Considerations 13.2 Sampling Switches 13.3 Switched-Capacitor Amplifiers 13.4 Switched-Capacitor Integrator 13.5 Switched-Capacitor

More information

EE247 Lecture 26. This lecture is taped on Wed. Nov. 28 th due to conflict of regular class hours with a meeting

EE247 Lecture 26. This lecture is taped on Wed. Nov. 28 th due to conflict of regular class hours with a meeting EE47 Lecture 6 This lecture is taped on Wed. Nov. 8 th due to conflict of regular class hours with a meeting Any questions regarding this lecture could be discussed during regular office hours or in class

More information

A 4 GSample/s 8-bit ADC in. Ken Poulton, Robert Neff, Art Muto, Wei Liu, Andrew Burstein*, Mehrdad Heshami* Agilent Laboratories Palo Alto, California

A 4 GSample/s 8-bit ADC in. Ken Poulton, Robert Neff, Art Muto, Wei Liu, Andrew Burstein*, Mehrdad Heshami* Agilent Laboratories Palo Alto, California A 4 GSample/s 8-bit ADC in 0.35 µm CMOS Ken Poulton, Robert Neff, Art Muto, Wei Liu, Andrew Burstein*, Mehrdad Heshami* Agilent Laboratories Palo Alto, California 1 Outline Background Chip Architecture

More information

Assoc. Prof. Dr. Burak Kelleci

Assoc. Prof. Dr. Burak Kelleci DEPARTMENT OF ELECTRICAL &ELECTRONICS ENGINEERING ANALOG-TO-DIGITAL AND DIGITAL- TO-ANALOG CONVERTERS Assoc. Prof. Dr. Burak Kelleci Fall 2018 OUTLINE Nyquist-Rate DAC Thermometer-Code Converter Hybrid

More information

Analog to Digital Conversion

Analog to Digital Conversion Analog to Digital Conversion Florian Erdinger Lehrstuhl für Schaltungstechnik und Simulation Technische Informatik der Uni Heidelberg VLSI Design - Mixed Mode Simulation F. Erdinger, ZITI, Uni Heidelberg

More information

Summary Last Lecture

Summary Last Lecture EE247 Lecture 23 Converters Techniques to reduce flash complexity Interpolating (continued) Folding Multi-Step s Two-Step flash Pipelined s EECS 247 Lecture 23: Data Converters 26 H.K. Page 1 Summary Last

More information

EE247 Lecture 17. EECS 247 Lecture 17: Data Converters 2006 H.K. Page 1. Summary of Last Lecture

EE247 Lecture 17. EECS 247 Lecture 17: Data Converters 2006 H.K. Page 1. Summary of Last Lecture EE47 Lecture 7 DAC Converters (continued) DAC dynamic non-idealities DAC design considerations Self calibration techniques Current copiers Dynamic element matching DAC reconstruction filter ADC Converters

More information

Analogue to Digital Conversion

Analogue to Digital Conversion Analogue to Digital Conversion Turns electrical input (voltage/current) into numeric value Parameters and requirements Resolution the granularity of the digital values Integral NonLinearity proportionality

More information

Summary Last Lecture

Summary Last Lecture EE247 Lecture 23 Converters Techniques to reduce flash complexity Interpolating (continued) Folding Multi-Step s Two-Step flash Pipelined s EECS 247 Lecture 23: Data Converters 26 H.K. Page Summary Last

More information

Fundamentals of Data Converters. DAVID KRESS Director of Technical Marketing

Fundamentals of Data Converters. DAVID KRESS Director of Technical Marketing Fundamentals of Data Converters DAVID KRESS Director of Technical Marketing 9/14/2016 Analog to Electronic Signal Processing Sensor (INPUT) Amp Converter Digital Processor Actuator (OUTPUT) Amp Converter

More information

Chapter 2 Signal Conditioning, Propagation, and Conversion

Chapter 2 Signal Conditioning, Propagation, and Conversion 09/0 PHY 4330 Instrumentation I Chapter Signal Conditioning, Propagation, and Conversion. Amplification (Review of Op-amps) Reference: D. A. Bell, Operational Amplifiers Applications, Troubleshooting,

More information

EE247 Lecture 14. To avoid having EE247 & EE 142 or EE290C midterms on the same day, EE247 midterm moved from Oct. 20 th to Thurs. Oct.

EE247 Lecture 14. To avoid having EE247 & EE 142 or EE290C midterms on the same day, EE247 midterm moved from Oct. 20 th to Thurs. Oct. Administrative issues EE247 Lecture 14 To avoid having EE247 & EE 142 or EE29C midterms on the same day, EE247 midterm moved from Oct. 2 th to Thurs. Oct. 27 th Homework # 4 due on Thurs. Oct. 2 th H.K.

More information

UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences

UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Final Exam EECS 247 H. Khorramabadi Tues., Dec. 14, 2010 FALL 2010 Name: SID: Total number of

More information

Analog to Digital Converters (ADC) Rferences. Types of AD converters Direct (voltage comparison)

Analog to Digital Converters (ADC) Rferences. Types of AD converters Direct (voltage comparison) Analog to Digital Converters (ADC) Lecture 7 Rferences U. Tietze, Ch.Schenk, Electronics Circuits Handbook for Design and Applications, Springer,2010 Advertisement materials and Application notes of: Linear

More information

A 12-bit Interpolated Pipeline ADC using Body Voltage Controlled Amplifier

A 12-bit Interpolated Pipeline ADC using Body Voltage Controlled Amplifier A 12-bit Interpolated Pipeline ADC using Body Voltage Controlled Amplifier Hyunui Lee, Masaya Miyahara, and Akira Matsuzawa Tokyo Institute of Technology, Japan Outline Background Body voltage controlled

More information

Quad 12-Bit Digital-to-Analog Converter (Serial Interface)

Quad 12-Bit Digital-to-Analog Converter (Serial Interface) Quad 1-Bit Digital-to-Analog Converter (Serial Interface) FEATURES COMPLETE QUAD DAC INCLUDES INTERNAL REFERENCES AND OUTPUT AMPLIFIERS GUARANTEED SPECIFICATIONS OVER TEMPERATURE GUARANTEED MONOTONIC OVER

More information

EE247 Lecture 26. EE247 Lecture 26

EE247 Lecture 26. EE247 Lecture 26 EE247 Lecture 26 Administrative EE247 Final exam: Date: Mon. Dec. 18 th Time: 12:30pm-3:30pm Location: 241 Cory Hall Extra office hours: Thurs. Dec. 14 th, 10:30am-12pm Closed book/course notes No calculators/cell

More information

EE247 Lecture 24. EE247 Lecture 24

EE247 Lecture 24. EE247 Lecture 24 EE247 Lecture 24 Administrative EE247 Final exam: Date: Wed. Dec. 15 th Time: -12:30pm-3:30pm- Location: 289 Cory Closed book/course notes No calculators/cell phones/pdas/computers Bring one 8x11 paper

More information

INF4420 Switched capacitor circuits Outline

INF4420 Switched capacitor circuits Outline INF4420 Switched capacitor circuits Spring 2012 1 / 54 Outline Switched capacitor introduction MOSFET as an analog switch z-transform Switched capacitor integrators 2 / 54 Introduction Discrete time analog

More information

Low-Power Pipelined ADC Design for Wireless LANs

Low-Power Pipelined ADC Design for Wireless LANs Low-Power Pipelined ADC Design for Wireless LANs J. Arias, D. Bisbal, J. San Pablo, L. Quintanilla, L. Enriquez, J. Vicente, J. Barbolla Dept. de Electricidad y Electrónica, E.T.S.I. de Telecomunicación,

More information

A Successive Approximation ADC based on a new Segmented DAC

A Successive Approximation ADC based on a new Segmented DAC A Successive Approximation ADC based on a new Segmented DAC segmented current-mode DAC successive approximation ADC bi-direction segmented current-mode DAC DAC INL 0.47 LSB DNL 0.154 LSB DAC 3V 8 2MS/s

More information

Outline. Analog/Digital Conversion

Outline. Analog/Digital Conversion Analog/Digital Conversion The real world is analog. Interfacing a microprocessor-based system to real-world devices often requires conversion between the microprocessor s digital representation of values

More information

The need for Data Converters

The need for Data Converters The need for Data Converters ANALOG SIGNAL (Speech, Images, Sensors, Radar, etc.) PRE-PROCESSING (Filtering and analog to digital conversion) DIGITAL PROCESSOR (Microprocessor) POST-PROCESSING (Digital

More information

Analog-to-Digital Converter Survey & Analysis. Bob Walden. (310) Update: July 16,1999

Analog-to-Digital Converter Survey & Analysis. Bob Walden. (310) Update: July 16,1999 Analog-to-Digital Converter Survey & Analysis Update: July 16,1999 References: 1. R.H. Walden, Analog-to-digital converter survey and analysis, IEEE Journal on Selected Areas in Communications, vol. 17,

More information

INF4420. Switched capacitor circuits. Spring Jørgen Andreas Michaelsen

INF4420. Switched capacitor circuits. Spring Jørgen Andreas Michaelsen INF4420 Switched capacitor circuits Spring 2012 Jørgen Andreas Michaelsen (jorgenam@ifi.uio.no) Outline Switched capacitor introduction MOSFET as an analog switch z-transform Switched capacitor integrators

More information

Mixed-Signal-Electronics

Mixed-Signal-Electronics 1 Mixed-Signal-Electronics PD Dr.-Ing. Stephan Henzler 2 Chapter 6 Nyquist Rate Analog-to-Digital Converters 3 Pipelined ADC 2 4 High-Speed ADC: Pipeline Processing Stephan Henzler Advanced Integrated

More information

2. ADC Architectures and CMOS Circuits

2. ADC Architectures and CMOS Circuits /58 2. Architectures and CMOS Circuits Francesc Serra Graells francesc.serra.graells@uab.cat Departament de Microelectrònica i Sistemes Electrònics Universitat Autònoma de Barcelona paco.serra@imb-cnm.csic.es

More information

INTEGRATED CIRCUITS. AN109 Microprocessor-compatible DACs Dec

INTEGRATED CIRCUITS. AN109 Microprocessor-compatible DACs Dec INTEGRATED CIRCUITS 1988 Dec DAC products are designed to convert a digital code to an analog signal. Since a common source of digital signals is the data bus of a microprocessor, DAC circuits that are

More information

Design of Pipeline Analog to Digital Converter

Design of Pipeline Analog to Digital Converter Design of Pipeline Analog to Digital Converter Vivek Tripathi, Chandrajit Debnath, Rakesh Malik STMicroelectronics The pipeline analog-to-digital converter (ADC) architecture is the most popular topology

More information

Working with ADCs, OAs and the MSP430

Working with ADCs, OAs and the MSP430 Working with ADCs, OAs and the MSP430 Bonnie Baker HPA Senior Applications Engineer Texas Instruments 2006 Texas Instruments Inc, Slide 1 Agenda An Overview of the MSP430 Data Acquisition System SAR Converters

More information

Advantages of Analog Representation. Varies continuously, like the property being measured. Represents continuous values. See Figure 12.

Advantages of Analog Representation. Varies continuously, like the property being measured. Represents continuous values. See Figure 12. Analog Signals Signals that vary continuously throughout a defined range. Representative of many physical quantities, such as temperature and velocity. Usually a voltage or current level. Digital Signals

More information

SPT Bit, 250 MSPS A/D Converter with Demuxed Outputs

SPT Bit, 250 MSPS A/D Converter with Demuxed Outputs 8-Bit, 250 MSPS A/D Converter with Demuxed Outputs Features TTL/CMOS/PECL input logic compatible High conversion rate: 250 MSPS Single +5V power supply Very low power dissipation: 425mW 350 MHz full power

More information

EE 435. Lecture 32. DAC Design. Parasitic Capacitances. The String DAC

EE 435. Lecture 32. DAC Design. Parasitic Capacitances. The String DAC EE 435 Lecture 32 DAC Design The String DAC Parasitic Capacitances . eview from last lecture. DFT Simulation from Matlab . eview from last lecture. Summary of time and amplitude quantization assessment

More information

10. Chapter: A/D and D/A converter principles

10. Chapter: A/D and D/A converter principles Punčochář, Mohylová: TELO, Chapter 10: A/D and D/A converter principles 1 10. Chapter: A/D and D/A converter principles Time of study: 6 hours Goals: the student should be able to define basic principles

More information

CMOS High Speed A/D Converter Architectures

CMOS High Speed A/D Converter Architectures CHAPTER 3 CMOS High Speed A/D Converter Architectures 3.1 Introduction In the previous chapter, basic key functions are examined with special emphasis on the power dissipation associated with its implementation.

More information

SWITCHED CAPACITOR CIRCUITS

SWITCHED CAPACITOR CIRCUITS EE37 Advanced Analog ircuits Lecture 7 SWITHED APAITOR IRUITS Richard Schreier richard.schreier@analog.com Trevor aldwell trevor.caldwell@utoronto.ca ourse Goals Deepen Understanding of MOS analog circuit

More information

Summary Last Lecture

Summary Last Lecture EE47 Lecture 5 Pipelined ADCs (continued) How many bits per stage? Algorithmic ADCs utilizing pipeline structure Advanced background calibration techniques Oversampled ADCs Why oversampling? Pulse-count

More information

Fig. 2. Schematic of the THA. M1 M2 M3 M4 Vbias Vdd. Fig. 1. Simple 3-Bit Flash ADC. Table1. THA Design Values ( with 0.

Fig. 2. Schematic of the THA. M1 M2 M3 M4 Vbias Vdd. Fig. 1. Simple 3-Bit Flash ADC. Table1. THA Design Values ( with 0. A 2-GSPS 4-Bit Flash A/D Converter Using Multiple Track/Hold Amplifiers By Dr. Mahmoud Fawzy Wagdy, Professor And Chun-Shou (Charlie) Huang, MSEE Department of Electrical Engineering, California State

More information

System on a Chip. Prof. Dr. Michael Kraft

System on a Chip. Prof. Dr. Michael Kraft System on a Chip Prof. Dr. Michael Kraft Lecture 5: Data Conversion ADC Background/Theory Examples Background Physical systems are typically analogue To apply digital signal processing, the analogue signal

More information

ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2012

ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2012 ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2012 Lecture 5: Termination, TX Driver, & Multiplexer Circuits Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements

More information

A 35 fj 10b 160 MS/s Pipelined- SAR ADC with Decoupled Flip- Around MDAC and Self- Embedded Offset Cancellation

A 35 fj 10b 160 MS/s Pipelined- SAR ADC with Decoupled Flip- Around MDAC and Self- Embedded Offset Cancellation Y. Zu, C.- H. Chan, S.- W. Sin, S.- P. U, R.P. Martins, F. Maloberti: "A 35 fj 10b 160 MS/s Pipelined-SAR ADC with Decoupled Flip-Around MDAC and Self- Embedded Offset Cancellation"; IEEE Asian Solid-

More information

Deep-Submicron CMOS Design Methodology for High-Performance Low- Power Analog-to-Digital Converters

Deep-Submicron CMOS Design Methodology for High-Performance Low- Power Analog-to-Digital Converters Deep-Submicron CMOS Design Methodology for High-Performance Low- Power Analog-to-Digital Converters Abstract In this paper, we present a complete design methodology for high-performance low-power Analog-to-Digital

More information

CMOS Operational-Amplifier

CMOS Operational-Amplifier CMOS Operational-Amplifier 1 What will we learn in this course How to design a good OP Amp. Basic building blocks Biasing and Loading Swings and Bandwidth CH2(8) Operational Amplifier as A Black Box Copyright

More information

Digital to Analog Conversion. Data Acquisition

Digital to Analog Conversion. Data Acquisition Digital to Analog Conversion (DAC) Digital to Analog Conversion Data Acquisition DACs or D/A converters are used to convert digital signals representing binary numbers into proportional analog voltages.

More information

Design of an Assembly Line Structure ADC

Design of an Assembly Line Structure ADC Design of an Assembly Line Structure ADC Chen Hu 1, Feng Xie 1,Ming Yin 1 1 Department of Electronic Engineering, Naval University of Engineering, Wuhan, China Abstract This paper presents a circuit design

More information

A Unity Gain Fully-Differential 10bit and 40MSps Sample-And-Hold Amplifier in 0.18μm CMOS

A Unity Gain Fully-Differential 10bit and 40MSps Sample-And-Hold Amplifier in 0.18μm CMOS A Unity Gain Fully-Differential 0bit and 40MSps Sample-And-Hold Amplifier in 0.8μm CMOS Sanaz Haddadian, and Rahele Hedayati Abstract A 0bit, 40 MSps, sample and hold, implemented in 0.8-μm CMOS technology

More information

EE247 Lecture 23. Advanced calibration techniques. Compensating inter-stage amplifier non-linearity Calibration via parallel & slow ADC

EE247 Lecture 23. Advanced calibration techniques. Compensating inter-stage amplifier non-linearity Calibration via parallel & slow ADC EE247 Lecture 23 Pipelined ADCs Combining the bits Stage implementation Circuits Noise budgeting Advanced calibration techniques Compensating inter-stage amplifier non-linearity Calibration via parallel

More information

IN the design of the fine comparator for a CMOS two-step flash A/D converter, the main design issues are offset cancelation

IN the design of the fine comparator for a CMOS two-step flash A/D converter, the main design issues are offset cancelation JOURNAL OF STELLAR EE315 CIRCUITS 1 A 60-MHz 150-µV Fully-Differential Comparator Erik P. Anderson and Jonathan S. Daniels (Invited Paper) Abstract The overall performance of two-step flash A/D converters

More information

The Case for Oversampling

The Case for Oversampling EE47 Lecture 4 Oversampled ADCs Why oversampling? Pulse-count modulation Sigma-delta modulation 1-Bit quantization Quantization error (noise) spectrum SQNR analysis Limit cycle oscillations nd order ΣΔ

More information

EE247 Lecture 22. Figures of merit (FOM) and trends for ADCs How to use/not use FOM. EECS 247 Lecture 22: Data Converters 2004 H. K.

EE247 Lecture 22. Figures of merit (FOM) and trends for ADCs How to use/not use FOM. EECS 247 Lecture 22: Data Converters 2004 H. K. EE247 Lecture 22 Pipelined ADCs Combining the bits Stage implementation Circuits Noise budgeting Figures of merit (FOM) and trends for ADCs How to use/not use FOM Oversampled ADCs EECS 247 Lecture 22:

More information

Asynchronous SAR ADC: Past, Present and Beyond. Mike Shuo-Wei Chen University of Southern California MWSCAS 2014

Asynchronous SAR ADC: Past, Present and Beyond. Mike Shuo-Wei Chen University of Southern California MWSCAS 2014 Asynchronous SAR ADC: Past, Present and Beyond Mike Shuo-Wei Chen University of Southern California MWSCAS 2014 1 Roles of ADCs Responsibility of ADC is increasing more BW, more dynamic range Potentially

More information

Electronics A/D and D/A converters

Electronics A/D and D/A converters Electronics A/D and D/A converters Prof. Márta Rencz, Gábor Takács, Dr. György Bognár, Dr. Péter G. Szabó BME DED December 1, 2014 1 / 26 Introduction The world is analog, signal processing nowadays is

More information

Mixed-Signal-Electronics

Mixed-Signal-Electronics 1 Mixed-Signal-Electronics PD Dr.-Ing. Stephan Henzler 2 Chapter 6 Nyquist Rate Analog-to-Digital Converters 3 Analog-to-Digital Converter Families Architecture Variant Speed Precision Counting Operation

More information

Another way to implement a folding ADC

Another way to implement a folding ADC Another way to implement a folding ADC J. Van Valburg and R. van de Plassche, An 8-b 650 MHz Folding ADC, IEEE JSSC, vol 27, #12, pp. 1662-6, Dec 1992 Coupled Differential Pair J. Van Valburg and R. van

More information

16.2 DIGITAL-TO-ANALOG CONVERSION

16.2 DIGITAL-TO-ANALOG CONVERSION 240 16. DC MEASUREMENTS In the context of contemporary instrumentation systems, a digital meter measures a voltage or current by performing an analog-to-digital (A/D) conversion. A/D converters produce

More information

Eliminate Pipeline Headaches with New 12-Bit 3Msps SAR ADC by Dave Thomas and William C. Rempfer

Eliminate Pipeline Headaches with New 12-Bit 3Msps SAR ADC by Dave Thomas and William C. Rempfer A new 12-bit 3Msps ADC brings new levels of performance and ease of use to high speed ADC applications. By raising the speed of the successive approximation (SAR) method to 3Msps, it eliminates the many

More information

781/ /

781/ / 781/329-47 781/461-3113 SPECIFICATIONS DC SPECIFICATIONS J Parameter Min Typ Max Units SAMPLING CHARACTERISTICS Acquisition Time 5 V Step to.1% 25 375 ns 5 V Step to.1% 2 35 ns Small Signal Bandwidth 15

More information

9-Bit, 30 MSPS ADC AD9049 REV. 0. Figure 1. Typical Connections FUNCTIONAL BLOCK DIAGRAM

9-Bit, 30 MSPS ADC AD9049 REV. 0. Figure 1. Typical Connections FUNCTIONAL BLOCK DIAGRAM a FEATURES Low Power: 00 mw On-Chip T/H, Reference Single +5 V Power Supply Operation Selectable 5 V or V Logic I/O Wide Dynamic Performance APPLICATIONS Digital Communications Professional Video Medical

More information

CMOS 12-Bit Serial Input Multiplying DIGITAL-TO-ANALOG CONVERTER

CMOS 12-Bit Serial Input Multiplying DIGITAL-TO-ANALOG CONVERTER CMOS 12-Bit Serial Input Multiplying DIGITAL-TO-ANALOG CONVERTER FEATURES 12-BICCURACY IN 8-PIN MINI-DIP AND 8-PIN SOIC FAST 3-WIRE SERIAL INTERFACE LOW INL AND DNL: ±1/2 LSB max GAIN ACCURACY TO ±1LSB

More information

10-Bit, 40 MSPS/60 MSPS A/D Converter AD9050 REV. B. Figure 1. Typical Connections FUNCTIONAL BLOCK DIAGRAM

10-Bit, 40 MSPS/60 MSPS A/D Converter AD9050 REV. B. Figure 1. Typical Connections FUNCTIONAL BLOCK DIAGRAM a FEATURES Low Power: 1 mw @ 0 MSPS, mw @ 0 MSPS On-Chip T/H, Reference Single + V Power Supply Operation Selectable V or V Logic I/O SNR: db Minimum at MHz w/0 MSPS APPLICATIONS Medical Imaging Instrumentation

More information

The Real World is Analog ADC are necessary to convert the real world signals (analog) into the digital form for easy processing. Digital Processing

The Real World is Analog ADC are necessary to convert the real world signals (analog) into the digital form for easy processing. Digital Processing Data Converters The Real World is Analog ADC are necessary to convert the real world signals (analog) into the digital form for easy processing ADC Digital Processing (Computer, DSP...) DAC Real World:

More information

4 Bits 250MHz Sampling Rate CMOS Pipelined Analog-to-Digital Converter

4 Bits 250MHz Sampling Rate CMOS Pipelined Analog-to-Digital Converter 4 Bits 250MHz Sampling Rate CMOS Pipelined Analog-to-Digital Converter Jinrong Wang B.Sc. Ningbo University Supervisor: dr.ir. Wouter A. Serdijn Submitted to The Faculty of Electrical Engineering, Mathematics

More information

Data Converters. Springer FRANCO MALOBERTI. Pavia University, Italy

Data Converters. Springer FRANCO MALOBERTI. Pavia University, Italy Data Converters by FRANCO MALOBERTI Pavia University, Italy Springer Contents Dedicat ion Preface 1. BACKGROUND ELEMENTS 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 The Ideal Data Converter Sampling 1.2.1 Undersampling

More information

Analog I/O. ECE 153B Sensor & Peripheral Interface Design Winter 2016

Analog I/O. ECE 153B Sensor & Peripheral Interface Design Winter 2016 Analog I/O ECE 153B Sensor & Peripheral Interface Design Introduction Anytime we need to monitor or control analog signals with a digital system, we require analogto-digital (ADC) and digital-to-analog

More information

Chapter 3 Novel Digital-to-Analog Converter with Gamma Correction for On-Panel Data Driver

Chapter 3 Novel Digital-to-Analog Converter with Gamma Correction for On-Panel Data Driver Chapter 3 Novel Digital-to-Analog Converter with Gamma Correction for On-Panel Data Driver 3.1 INTRODUCTION As last chapter description, we know that there is a nonlinearity relationship between luminance

More information

Electronics II Physics 3620 / 6620

Electronics II Physics 3620 / 6620 Electronics II Physics 3620 / 6620 Feb 09, 2009 Part 1 Analog-to-Digital Converters (ADC) 2/8/2009 1 Why ADC? Digital Signal Processing is more popular Easy to implement, modify, Low cost Data from real

More information

Selecting and Using High-Precision Digital-to-Analog Converters

Selecting and Using High-Precision Digital-to-Analog Converters Selecting and Using High-Precision Digital-to-Analog Converters Chad Steward DAC Design Section Leader Linear Technology Corporation Many applications, including precision instrumentation, industrial automation,

More information

Experiment 1: Amplifier Characterization Spring 2019

Experiment 1: Amplifier Characterization Spring 2019 Experiment 1: Amplifier Characterization Spring 2019 Objective: The objective of this experiment is to develop methods for characterizing key properties of operational amplifiers Note: We will be using

More information

Proposing. An Interpolated Pipeline ADC

Proposing. An Interpolated Pipeline ADC Proposing An Interpolated Pipeline ADC Akira Matsuzawa Tokyo Institute of Technology, Japan Matsuzawa & Okada Lab. Background 38GHz long range mm-wave system Role of long range mm-wave Current Optical

More information

PHYS225 Lecture 22. Electronic Circuits

PHYS225 Lecture 22. Electronic Circuits PHYS225 Lecture 22 Electronic Circuits Last lecture Digital to Analog Conversion DAC Converts digital signal to an analog signal Computer control of everything! Various types/techniques for conversion

More information

Analog-to-Digital Converters

Analog-to-Digital Converters EE47 Lecture 3 Oversampled ADCs Why oversampling? Pulse-count modulation Sigma-delta modulation 1-Bit quantization Quantization error (noise) spectrum SQNR analysis Limit cycle oscillations nd order ΣΔ

More information

ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2012

ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2012 ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2012 Lecture 6: RX Circuits Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements Lab 4 Prelab due now Exam

More information

Design and Implementation of a Sigma Delta ADC By: Moslem Rashidi, March 2009

Design and Implementation of a Sigma Delta ADC By: Moslem Rashidi, March 2009 Design and Implementation of a Sigma Delta ADC By: Moslem Rashidi, March 2009 Introduction The first thing in design an ADC is select architecture of ADC that is depend on parameters like bandwidth, resolution,

More information

8-Bit, high-speed, µp-compatible A/D converter with track/hold function ADC0820

8-Bit, high-speed, µp-compatible A/D converter with track/hold function ADC0820 8-Bit, high-speed, µp-compatible A/D converter with DESCRIPTION By using a half-flash conversion technique, the 8-bit CMOS A/D offers a 1.5µs conversion time while dissipating a maximum 75mW of power.

More information

Design of an 8-bit Successive Approximation Pipelined Analog to Digital Converter (SAP- ADC) in 90 nm CMOS

Design of an 8-bit Successive Approximation Pipelined Analog to Digital Converter (SAP- ADC) in 90 nm CMOS Design of an 8-bit Successive Approximation Pipelined Analog to Digital Converter (SAP- ADC) in 90 nm CMOS A thesis submitted in partial fulfillment of the requirements for the degree of Master of Science

More information

EE247 Lecture 23. EECS 247 Lecture 23 Pipelined ADCs 2008 H.K. Page 1. Pipeline ADC Block Diagram DAC ADC. V res2. Stage 2 B 2.

EE247 Lecture 23. EECS 247 Lecture 23 Pipelined ADCs 2008 H.K. Page 1. Pipeline ADC Block Diagram DAC ADC. V res2. Stage 2 B 2. EE247 Lecture 23 Pipelined ADCs (continued) Effect gain stage, sub-dac non-idealities on overall ADC performance Digital calibration (continued) Correction for inter-stage gain nonlinearity Implementation

More information

DATASHEET HI5805. Features. Applications. Ordering Information. Pinout. 12-Bit, 5MSPS A/D Converter. FN3984 Rev 7.00 Page 1 of 12.

DATASHEET HI5805. Features. Applications. Ordering Information. Pinout. 12-Bit, 5MSPS A/D Converter. FN3984 Rev 7.00 Page 1 of 12. 12-Bit, 5MSPS A/D Converter NOT RECOMMENDED FOR NEW DESIGNS NO RECOMMENDED REPLACEMENT contact our Technical Support Center at 1-888-INTERSIL or www.intersil.com/tsc DATASHEET FN3984 Rev 7.00 The HI5805

More information

TUTORIAL 283 INL/DNL Measurements for High-Speed Analog-to- Digital Converters (ADCs)

TUTORIAL 283 INL/DNL Measurements for High-Speed Analog-to- Digital Converters (ADCs) Maxim > Design Support > Technical Documents > Tutorials > A/D and D/A Conversion/Sampling Circuits > APP 283 Maxim > Design Support > Technical Documents > Tutorials > High-Speed Signal Processing > APP

More information

10.1: A 4 GSample/s 8b ADC in 0.35-um CMOS

10.1: A 4 GSample/s 8b ADC in 0.35-um CMOS 10.1: A 4 GSample/s 8b ADC in 0.35-um CMOS Ken Poulton, Robert Neff, Art Muto, Wei Liu*, Andy Burstein**, Mehrdad Heshami*** Agilent Technologies, Palo Alto, CA *Agilent Technologies, Colorado Springs,

More information

Lecture 6: Digital/Analog Techniques

Lecture 6: Digital/Analog Techniques Lecture 6: Digital/Analog Techniques The electronics signals that we ve looked at so far have been analog that means the information is continuous. A voltage of 5.3V represents different information that

More information

CDK bit, 250 MSPS A/D Converter with Demuxed Outputs

CDK bit, 250 MSPS A/D Converter with Demuxed Outputs Amplify the Human Experience CDK1301 8-bit, 250 MSPS A/D Converter with Demuxed Outputs features n TTL/CMOS/PECL input logic compatible n High conversion rate: 250 MSPS n Single +5V power supply n Very

More information

12 Bit 1.5 GS/s Return to Zero DAC

12 Bit 1.5 GS/s Return to Zero DAC 12 Bit 1.5 GS/s Return to Zero DAC RDA112RZ Features 12 Bit Resolution 1.5 GS/s Sampling Rate 10 Bit Static Linearity LVDS Compliant Digital Inputs Power Supply: -5.2V, +3.3V Input Code Format: Offset

More information

A Serial Link Transceiver Based on 8 GSa/s A/D and D/A Converters

A Serial Link Transceiver Based on 8 GSa/s A/D and D/A Converters A Serial Link Transceiver Based on 8 GSa/s A/D and D/A Converters in 0.25µm m CMOS William Ellersick 1,3, Chih-Kong Ken Yang 2 Vladimir Stojanovic 1, Siamak Modjtahedi 2, Mark A. Horowitz 1 1 Stanford

More information

NPTEL. VLSI Data Conversion Circuits - Video course. Electronics & Communication Engineering.

NPTEL. VLSI Data Conversion Circuits - Video course. Electronics & Communication Engineering. NPTEL Syllabus VLSI Data Conversion Circuits - Video course COURSE OUTLINE This course covers the analysis and design of CMOS Analog-to-Digital and Digital-to-Analog Converters,with about 7 design assigments.

More information