Administrative. No office hour on Thurs. this week Instead, office hour 3 to 4pm on Wed.
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1 Administrative No office hour on Thurs. this week Instead, office hour 3 to 4pm on Wed. EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page EE247 Lecture 2 ADC Converters Sampling (continued) Effect of clock jitter on sampling ADC architectures and design Serial- slope type Successive approximation Flash Flash ADC sources of error Sparkle code Meta-stability Comparator design EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 2
2 Summary Last Lecture ADC Converters Sampling (continued) Sampling switch charge injection & clock feedthrough Complementary switch Use of dummy device Bottom-plate switching Track & hold Flip-around T/H circuit T/H combined with summing/difference function T/H circuit incorporating gain & offset cancellation T/H aperture uncertainty EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 3 Effect of Clock Jitter So far assumption was that the clock signal controlling the sampling instants has no variability and have their edges spaced exactly equal to T s /2 In practice the clock edges are not prefectly spaced and have some level of jitter Variability in T s causes errors in data converter performance "Aperture Uncertainty" or "Aperture Jitter Question: for a given application how much clock jitter can be tolerated? EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 4
3 Clock Jitter Sampling jitter adds an error voltage proportional to the product of (t J -t ) and the derivative of the input signal at the sampling instant x(t) x (t ) actual sampling time t J Jitter doesn t matter when sampling dc signals (x (t )=) nominal (ideal) sampling time t EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 5 Clock Jitter The error voltage is e = x (t )(t J t ) x(t) x (t ) error actual sampling time t J nominal sampling time t EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 6
4 Jitter Example Sinusoidal input: Amplitude: A Frequency: Jitter: f x dt max ( π ) x( t ) = A s i n 2 f t x x x max x ( π ) x'(t ) = 2π f Acos 2 f t x'(t ) 2π f A Thus: e( t ) x' ( t ) d t e( t ) 2π f A d t x Worst case error: A= AFS f fs x = 2 2 Δ AFS e( t ) << B+ 2 2 dt << B 2 π f # of Bits 6 2 s f s MHz MHz MHz dt <<.5 ps.8 ps.3 ps EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 7 Law of Jitter The worst case looks pretty stringent what about the average? Let s calculate the mean squared jitter error (variance) If we re sampling a sinusoidal signal x(t) = Asin(2πf x t), then x (t) = 2πf x Acos(2πf x t) E{[x (t)] 2 } = 2π 2 f x2 A 2 Assume the jitter has variance E{(t J -t ) 2 } = τ 2 EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 8
5 Law of Jitter If x (t) and the jitter are independent E{[x (t)(t J -t )] 2 }= E{[x (t)] 2 } E{(t J -t ) 2 } Hence, the jitter error power is E{e 2 } = 2π 2 f x2 A 2 τ 2 If the jitter is uncorrelated from sample to sample, this jitter noise is white EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 9 Law of Jitter DR jitter 2 A / 2 = π f A τ x = π f τ x = 2log ( 2πf τ ) x Example: ENOB=2bit f in =35MHz τ<ps rms! EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page
6 Clock Jitter Conclusion The first requirement is to have a good enough clock generator Clock signal should be handled carefully on-chip to prevent additional excessive jitter Usually, clock jitter in the single-digit pico-second range can be prevented by appropriate design techniques: Separate supplies Separate analog and digital clocks Short inverter chains between clock source and destination Few, if any, other analog-to-digital conversion non-idealities have the same symptoms as sampling jitter: RMS noise proportional to input frequency RMS noise proportional to input amplitude In cases where clock jitter limits the dynamic range, it s easy to tell, but may be difficult to fix... EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page ADC Architecture & Design EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 2
7 ADC Architectures Slope type converters Successive approximation Flash Time-interleaved / parallel converter Folding Residue type ADCs Two-step Pipeline Oversampled ADCs EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 3 Various ADC Architectures Resolution/Conversion Rate Resolution Oversampled & Serial Algorithmic e.g. Succ. Approx. Subranging e.g. Pipelined Folding & Interpolative Parallel & Time Interleaved Conversion Rate EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 4
8 Serial ADC Single Slope V Ramp Ramp Generator V Ramp V IN "" stop start B..B N.. Counter Clock Time Counter starts V Ramp = Counter stops counting for V IN =V Ramp Counter output proportional to V IN EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 5 Single Slope ADC Advantages: Low complexity & simple INL depends on ramp linearity & not component matching Inherently monotonic Disadvantages: Slow (2 N clock pulses for N-bit conversion) (e.g. N=6 f clock =MHz needs 65xμs=65ms/conversion) Hard to generate precise ramp required for high resolution ADCs Need to calibrate ramp slope versus V IN Better: Dual Slope, Multi-Slope EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 6
9 Serial ADC Dual Slope V IN V "" Integrator o -V REF Flip Flop Clock B..B N.. Counter & Timing First: V IN is integrated for a fixed time (2 N xt CLK ) V o = 2 N xt CLK V IN /τ intg Next: V o is de-integrated with V REF until V o = Counter output = 2 N V IN /V REF EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 7 Dual Slope ADC Slope α V IN Slope = Const. Integrate V in for fixed time (T INT ), de-integrate with V REF applied T De-Int ~ 2 Nx T CLK xv in /V REF Most laboratory DVMs use this type of ADC EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 8
10 Dual Slope ADC Advantage: Accuracy to st order independent of integrator time-constant and clock period Comparator offset referred to input is attenuated by integrator high DC gain Insensitive to most linear error sources DNL is a function of clock jitter Power line (6Hz) xtalk effect on reading can be canceled by: choosing conversion time multiple of /6Hz High accuracy achievable (6+bit) Disadvantage: Slow (maximum 2x2 N xt clk per conversion) Integrator opamp offset results in ADC offset (can cancel) Finite opamp gain gives rise to INL EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 9 Successive Approximation ADC SAR Algorithmic type ADC Based on binary search over DAC output Reset DAC Set DAC[MSB]= V IN T/H MSB Y V IN >V DAC? N MSB V REF DAC Set DAC[MSB-]= Control Logic Clock [MSB-] [LSB] Y Y V IN >V DAC?. V IN >V DAC? N [MSB-] N [LSB] DAC[Input]= ADC[Output] EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 2
11 Successive Approximation ADC Example: 6-bit ADC & V IN =5/8V REF V IN T/H V REF Control Logic Clock DAC + - 3/4 5/8 /2 V DAC /V REF /2 3/4 5/8 /6 2/32 4/64 Test MSB V IN DAC Output Test MSB- ADC Time / Clock Ticks High accuracy achievable (6+ Bits) Required N clock cycles for N-bit conversion (much faster than slope type) Moderate speed proportional to N (typically MHz range) EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 2 Example: SAR ADC Charge Redistribution Type S top Comparator 32C 6C 8C 4C 2C C C - Out b 4 (MSB) b 3 b 3 b 2 b b V in Control To Logic switches V REF V in Built with binary weighted capacitors, switches, comparator & control logic T/H inherent in DAC EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 22
12 Charge Redistribution Type SAR DAC Operation: MSB 32C 32C 32C -V in +V REF /2 32C - Comparator Out b 4 (MSB) V in Phase b 3 -b V REF b 4 (MSB) b 3 -b Phase 2 To switches Control Logic Operation starts by connecting all top plate to gnd and all bottom plates to V in To test the MSB all top plate are opened bottom plate of 32C connected to V REF & rest of bottom plates connected to ground input to comparator= -V in +V REF /2 Comparator is strobed to determine the polarity of input signal: If negative MSB=, else MSB= The process continues until all bits are determined EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 23 Example: SAR ADC Charge Redistribution Type reset C P -Comparator 32C 6C 8C 4C 2C C C Out b 4 (msb) b 3 b 3 b 2 b b V in Control Logic To switches V REF V in To st order parasitic (C p ) insensitive since top plate driven from initial to final by the global negative feedback Linearity is a function of accuracy of C ratios Possible to add a C ratio calibration cycle (see Ref.) Ref: H. Lee, D. A. Hodges, and P. R. Gray, "A self-calibrating 5 bit CMOS A/D converter," IEEE Journal of Solid-State Circuits, vol. 9, pp , December 984. EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 24
13 B-bit flash ADC: DAC generates all possible 2 B - levels 2 B - comparators compare V IN to DAC outputs Comparator output: If V DAC < V IN If V DAC > V IN Comparator outputs form thermometer code Encoder converts thermometer to binary code Flash ADC V REF V IN f s D A C B - B Encoder Digital Output EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 25 Flash ADC Converter Example: 3-bit Conversion V IN V IN V REF V REF f s Thermometer code Encoder Binary B-bits T s Time EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 26
14 Flash Converter Characteristics Very fast: only clock cycle per conversion ½ clock cycle V IN & V DAC comparison ½ clock cycle 2 B - to B encoding High complexity: 2 B - comparators V IN V REF f s Encoder Input capacitance of 2 B - comparators connected to the input node: High input node Thermometer code B-bits EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 27 Flash Converter Sources of Error V REF V IN f s R/2 R R R R R/2. Encoder Digital Output Comparator input: Offset Nonlinear input capacitance Kickback noise (disturbs reference) Signal dependent sampling time Comparator output: Sparkle codes ( ) Metastability EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 28
15 Flash Converter Example: 8-bit ADC 8-bit 255 comparators R/2 V REF V IN f s V REF =V LSB=4mV R DNL</2LSB Comparator input referred offset < 2mV R R. Encoder Digital Output Assuming close to % yield, 2mV =6σ offset σ offset <.33mV R R/2 EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 29 Flash ADC Converter Example: 8-bits ADC (continued) σ Offset <.33mV Let us assume in the technology used: Voffset-per-unit-sqrt(WxL)=3 mvx μ 3mV 2 V ffset = =.33mV W L = 83μ W L 2 2 Assuming: Cox = 9 ff/ μ CGS = CoxW L= 496 ff 3 Total input capacitance: = 26.5 pf! Issues: Si area quite large Large input capacitance Since depending on input voltage different number of comparator input transistors would be on/off- total input capacitance varies as input varies Nonlinear input capacitance could give rise to signal distortion Ref: M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, "Matching properties of MOS transistors," IEEE Journal of Solid-State Circuits, vol. 24, pp , October 989. EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 3
16 Flash ADC Converter Example (continued) Trade-offs: Allowing larger DNL e.g. LSB instead of.5lsb: Increases the maximum allowable input-referred offset voltage by a factor of 2 Decreases the required device WxL by a factor of 4 Reduces the input device area by a factor of 4 Reduces the input capacitance by a factor of 4! Reducing the ADC resolution by -bit Increases the maximum allowable input-referred offset voltage by a factor of 2 Decreases the required device WxL by a factor of 4 Reduces the input device area by a factor of 4 Reduce the input capacitance by a factor of 4 EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 3 Flash Converter Comparator Tolerable Maximum Offset versus ADC Resolution Assumption: DNL=.5LSB Note: Graph shows max. tolerable offset, note that depending on min acceptable yield, the derived offset numbers are associated with 2σ to 6σ offset voltage Maximum Comparator V offset [mv] 2 - V REF =2V V REF =V ADC Resolution EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 32
17 Typical Flash Output Encoder V DD Thermometer code -of-n code b3 b2 b b Binary B-bits Thermometer to Binary encoder ROM Thermometer code -of-n decoding Final encoding NOR ROM Ideally, for each code, only one ROM row is on b3 b2 b b Output EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 33 Sparkle Codes V DD Erroneous (comparator offset?) b3 b2 b b Correct Output: Problem: Two rows are on Erroneous Output: Up to ~ ½ FS error!! EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 34
18 Sparkle Tolerant Encoder Protects against a single sparkle. Ref: C. Mangelsdorf et al, A 4-MHz Flash Converter with Error Correction, JSSC February 99, pp EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 35 Meta-Stability Different gates interpret metastable output X differently X Correct output: Erroneous output: Solutions: Latches (high power) Gray encoding Ref: C. Portmann and T. Meng, Power-Efficient Metastability Error Reduction in CMOS Flash A/D Converters, JSSC August 996, pp EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 36
19 Gray Encoding Example: 3bit ADC Thermometer Code Gray Binary T T 2 T 3 T 4 T 5 T 6 T 7 G 3 G 2 G B 3 B 2 B G G G 2 3 = T T + T T = T T = T Each T i affects only one G i Avoids disagreement of interpretation by multiple gates Protects also against sparkles Follow Gray encoder by (latch and) binary encoder EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 37 Voltage Comparators V DD V i+ V i V out (Digital Output) Play an important role in majority of ADCs Function: Compare the instantaneous value of two analog signals & generate a digital output voltage based on the sign of the difference: If V i+ -V i- > V out = If V i+ -V i- < V out = EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 38
20 Voltage Comparator Architectures Comparator architectures High gain amplifier with differential analog input & single-ended large swing output Output swing compatible with driving digital logic circuits Open-loop amplification no frequency compensation required Precise gain not required Latched comparators; in response to a strobe, input stage disabled & digital output stored in a latch till next strobe Two options for implementation : Latch-only comparator Low-gain amplifier + high-sensitivity latch Sample-data comparators T/H input Offset cancellation EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 39 Comparators w/ High-Gain Amplification Amplify V in (min) to V DD V in (min) determined by ADC resolution Example: 2-bit ADC with: -V FS =.5V LSB=.36mV -V DD =.8V For.8V output &.5LSB precision: Min.8V Av =,.8mV EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 4
21 f u u Comparators -Single-Stage Amplification = unity-gain frequency, f =-3dB frequency fu f= o AV Example: f =GHz & A =, GHz fo = khz, τsettling = =.6μsec 2π fo Allowa few τ for output to settle Max. fclock 26kHz 5τ settling V o Gain f u =.-GHz f f u frequency Too slow for majority of applications! Try cascade of lower gain stages to broaden frequency of operation A v Assumption: Single pole amplifier EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 4 Comparators 2- Cascade of Open Loop Amplifiers The stages identical small-signal model for the cascades: One stage: EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 42
22 Open Loop Cascade of Amplifiers EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 43 Open Loop Cascade of Amplifiers For A T (DC) =, Example: N=3, f =GHz & A () = u GHz /3 fon = MHz /3 (,) τ settling = = 7nsec 2π f Max. Clock o A llowa few τ for output to settle f 29MHz 5τ settling T f max improved from 26kHz to 29MHz X236 EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 44
23 Open Loop Cascade of Amplifiers Offset Voltage From offset point of view high gain/stage is preferred Choice of # of stage bandwidth vs offset tradeoff Input-referred offset EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 45 Open Loop Cascade of Amplifiers Step Response Assuming linear behavior t EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 46
24 Open Loop Cascade of Amplifiers Step Response Assuming linear behavior EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 47 Open Loop Cascade of Amplifiers Delay/(C/g m ) Minimum total delay broad function of N Relationship between # of stages resulting in minimize delay (N op ) and gain (V out /V in ) approximately: Delay/(C/g m ) N opt + log 2 A T for A< N opt.2lna T for A Ref: J.T. Wu, et al., A -MHz pipelined CMOS comparator IEEE Journal of Solid-State Circuits, vol. 23, pp , December 988. EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 48
25 Offset Cancellation In sampled-data cascade of amplifiers Vos can be cancelled Store on ac-coupling caps in series with amp stages Offset associated with a specific amp can be cancelled by storing it in series with either the input or the output of that stage Offset can be cancelled by adding a pair of auxiliary inputs to the amplifier and storing the offset on capacitors connected to the aux. inputs during offset cancellation phase Ref: J.T. Wu, et al., A -MHz pipelined CMOS comparator IEEE Journal of Solid-State Circuits, vol. 23, pp , December 988. EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 49 Offset Cancellation Output Series Cancellation Amp modeled as ideal + V os (input referred) Store offset: S, S4 open S2, S3 closed V C =AxV OS Ref: J.T. Wu, et al., A -MHz pipelined CMOS comparator IEEE Journal of Solid-State Circuits, vol. 23, pp , December 988. EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 5
26 Offset Cancellation Output Series Cancellation Amplify: S, S4 closed S2, S3 open V C =AxV OS Circuit requirements: Amp not saturate during offset storage High-impedance (C) load C c not discharged C c >> C L to avoid attenuation C c >> C switch offset due to charge injection EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 5 Offset Cancellation Cascaded Output Series Cancellation EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 52
27 Offset Cancellation Cascaded Output Series Cancellation - S open, S2,3,4,5 closed V C =A xv os V C2 =A 2 xv os2 V C3 =A xv os3 EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 53 Offset Cancellation Cascaded Output Series Cancellation 2- S3 open Feedthrough from S3 offset on X Switch offset, ε 2 induced on node X Since S4 remains closed, offset associated with ε 2 stored on C2 V X = ε 2 V C =A xv os - ε 2 V C2 =A 2 x(v os2 + ε 2 ) EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 54
28 Offset Cancellation Cascaded Output Series Cancellation 3- S4 open Feedthrough from S4 offset on Y Switch offset, ε 3 induces error on node Y Since S5 remains closed, offset associated with ε 3 stored on C3 V Y = ε 3 V C2 =A 2 x(v os2 + ε 2 ) - ε 3 V C3 =A 3 x(v os3 + ε 3 ) EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 55 Offset Cancellation Cascaded Output Series Cancellation 4- S2 open, S closed, S5 open S closed & S2 open since input connected to low impedance source charge injection not of major concern Switch offset, ε 4 introduced due to S5 opening EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 56
29 Offset Cancellation Cascaded Output Series Cancellation EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 57 Offset Cancellation Cascaded Output Series Cancellation Example: 3-stage open-loop differential amplifier with offset cancellation + output amplifier (see Ref.) A Total (DC) = 2x 6 = 2dB Input-referred offset < 5μV Ref: :R. Poujois and J. Borel, "A low drift fully integrated MOSFET operational amplifier," IEEE Journal of Solid- State Circuits, vol. 3, pp , August 978. EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 58
30 Offset Cancellation Output Series Cancellation Advantages: Almost compete cancellation Closed-loop stability not required Disadvantages: Gain per stage must be small Offset storage C in the signal path- could slow down overall performance EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 59 Offset Cancellation Input Series Cancellation Ref: :R. Poujois and J. Borel, "A low drift fully integrated MOSFET operational amplifier," IEEE Journal of Solid-State Circuits, vol. 3, pp , August 978. EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 6
31 Offset Cancellation Input Series Cancellation Store offset Note: Mandates closed-loop stability Ref: :R. Poujois and J. Borel, "A low drift fully integrated MOSFET operational amplifier," IEEE Journal of Solid-State Circuits, vol. 3, pp , August 978. EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 6 Amplify S2, S3 open S closed Offset Cancellation Input Series Cancellation Example: A=4 Input-referred offset =V os /5 EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 62
32 Offset Cancellation Cascaded Input Series Cancellation ε 2 charge injection associated with opening of S4 EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 63 Offset Cancellation Input Series Cancellation Advantages: In applications such as C-array successive approximation ADCs can use C-array to store offset Disadvantages: Cancellation not complete Requires closed loop stability Offset storage C in the signal path- could slow down overall performance EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 64
33 CMOS Comparators Cascade of Gain Stages Fully differential gain stages st order cancellation of switch feedthrough offset - Output series offset cancellation 2- Input series offset cancellation EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 65 CMOS Comparators Cascade of Gain Stages 3-Combined input & output series offset cancellation EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 66
34 Offset Cancellation Cancel offset by additional pair of inputs (Lecture 9 slide 35-37) EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page 67
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