SWITCHED CAPACITOR CIRCUITS

Transcription

1 EE37 Advanced Analog ircuits Lecture 7 SWITHED APAITOR IRUITS Richard Schreier richard.schreier@analog.com Trevor aldwell trevor.caldwell@utoronto.ca ourse Goals Deepen Understanding of MOS analog circuit design through a top-down study of a modern analog system The lectures will focus on Delta-Sigma ADs, but you may do your project on another analog system. Develop circuit insight through brief peeks at some nifty little circuits The circuit world is filled with many little gems that every competent designer ought to recognize. EE37 7-

2 Date Lecture Ref Homework RS Introduction: MOD & MOD S&T -3, A Matlab MOD RS Example Design: Part S&T 9., J&M 0 Switch-level sim RS 3 Example Design: Part J&M 4, S&T B Q-level sim T 4 Pipeline and SAR ADs J&M,3 Pipeline DNL ISS No Lecture RS 5 Advanced ΔΣ S&T 4, 6.6, 9.4, B TMOD; Proj Reading Week No Lecture RS 6 omparator and Flash AD J&M T 7 S ircuits Raz, J&M T 8 Amplifier Design T 9 Amplifier Design T 0 Noise in S ircuits S&T Project Presentations T Matching & MM-Shaping RS Switching Regulator Project Report EE NLOTD: Schmitt Trigger Problem: Input is noisy or slowly varying V IN V OUT? t t Noisy Input lean Output How do we turn this into a clean digital output? EE37 7-4

3 Highlights (i.e. What you will learn today). Motivation for S ircuits. Basic sampling switch and charge injection errors 3. Fundamental S ircuits Sample & Hold, Gain and Integrator 4. Other ircuits Bootstrapping, S MFB EE Why Switched apacitor? Used in discrete-time or sampled-data circuits Alternative to continuous-time circuits apacitors instead of resistors apacitors won t reduce the gain of high output impedance OTAs No need for low output impedance buffer to drive resistors Accurate frequency response Filter coefficients determined by capacitor ratios (rather than R time constants) and clock frequencies apacitor matching on the order of 0.% - when the transfer characteristics are a function of only a capacitor ratio, it can be very accurate R time constants vary by up to 0% EE37 7-6

4 Opamps Basic Building Blocks Ideal usually assumed Some important non-idealities to consider include:. D Gain: sets the accuracy of the charge transfer, how grounded the virtual ground is. Unity-gain freq, Phase Margin & Slew Rate: determines maximum clock frequency 3. D Offsets: circuit techniques to combat this and /f noise orrelated Double Sampling, hopping apacitors Large absolute variation, good matching Large bottom plate capacitor adds parasitic cap EE Switches Basic Building Blocks MOSFET switches are good large off resistance (GΩ), small on resistance (00Ω -5kΩ, depending on transistor sizing) MOSFET switches have non-linear parasitic capacitors Non-Overlapping locks locks are never on at the same time Required so that charge is never lost/shared lock Generator previously discussed T EE37 7-8

5 Basic Sampling Switch MOSFET used as sample-and-hold When LK is HIGH, V OUT follows V IN through the lowpass filter created by R ON and R ON varies depending on V IN, V OUT, and V DD V IN V DD V OUT R ON When LK is LOW, V OUT holds the value on V SS V IN V OUT EE On-Resistance Variation With an NMOS sampling switch, as V IN approaches V DD -V TH, R ON increases dramatically In smaller technologies, as V DD decreases the swing on V IN is severely limited R ON = W μnox ( VDD VIN VTH) L R ON V DD -V TH Sampling switch must be sized for worst case R ON so that the bandwidth is still sufficient V IN EE37 7-0

6 On-Resistance Variation PMOS switches suffer from the same problem as V IN approaches V T omplementary switch can allow rail-to-rail input swings Ignoring variation of R ON,n R ON,p V TH with V IN, R ON,eq is R ON,n constant with V IN if R ON,p W W μnox = μpox L L V TH V DD -V TH V DD V IN EE37 7- Settling Accuracy Two situations to consider ) Discrete-time signal When analyzing a signal within the switchedcapacitor circuit (for example, at the output of the first OTA) ) ontinuous-time signal When analyzing a signal that is sampled at the input EE37 7-

7 Settling Accuracy DT Discrete-Time Signal Settling Error = e -T/4R For N-bit accuracy in T/4 seconds T RON < 4N ln This is the maximum R ON (for a given ) Example: Assume GHz to 4 GHz variation of Input sinusoidal signal at 50 MHz π RON For f S =00MHz, N= bits with discrete-time signal (typically you are limited by the OTA) EE Settling Accuracy T ontinuous-time Signal R ON acts as a low-pass filter and introduces amplitude and phase change Variations in the input signal size cause variations in R ON, causing distortion in the sampled signal Both the amplitude and phase vary which one causes distortion? EE37 7-4

8 Amplitude Error Less significant error Due to variation in magnitude of low-pass filter At 50 MHz (with same R ON variation as DT case), maximum possible error is 0.% EE Distortion in sampled T input Input ~50 MHz, sampled at 00MHz Distortion at 57dB, or ~9 bits This is larger than the maximum possible error due to amplitude variation dbfs EE Normalized Frequency

9 Phase Error More significant error Due to variation in phase of low-pass filter At 50 MHz (with same R ON variation as DT case), maximum possible error is a few percent - error is less than that EE harge Injection When a transistor turns off, the channel charge Q H goes into the circuit Doesn t exactly divide in half - depends on impedance seen at each terminal and the clock transition time Q = WL ( V V V ) H ox DD IN TH harge into V IN has no impact on output node Doesn t create error in the circuit harge into causes error ΔV in V OUT V IN Q H Q H V OUT Δ V = Q H ( ) WL V ox DD V IN V TH = EE37 7-8

10 harge Injection In previous analysis, charge injection introduces a gain and offset error This is still linear and could be tolerated or corrected VOUT = VIN ΔV WLox WLox( VDD VTH ) = VIN + But V TH is actually a function of ~ V IN Introduces non-linear term that cannot be corrected in the circuit EE harge Injection vs. Speed harge injection Proportional to transistor size (WL) Speed R ON inversely proportional to aspect ratio (W/L) Figure of Merit Product of speed (/τ) and charge injection (/ΔV) WLox ( τδ V) = ( VDD VIN VTH ) μnox( W/ L)( VDD VIN VTH) μn = L EE37 7-0

11 lock Feedthrough Overlap capacitance allows clock to couple from the gate to drain/source terminals hange in voltage ΔV independent of the input signal Error is an offset voltage which is cancelled with differential operation V LK 0 OV V IN OV V OUT Δ V = ov + ov V LK EE37 7- harge Error ancellation Differential operation ancels offset errors, depending on the matching between differential circuits Applies to signal dependent portion of charge injection error, and clock feedthrough error omplementary Switches Error cancelled for input level WL n n ox( VLK VIN VTHN ) = WL p p ox( VIN VTHP ) lock feedthrough cancelled depending on similarity of overlap capacitance for PMOS and NMOS switches EE37 7-

12 harge Error ancellation Dummy Switch Use second transistor to remove charge injection by main transistor Inverted clock operates on dummy switch harge from M: qm = WL ox( VK VIN VTH)/ harge from M: qm = WL ox( VK VIN VTH) If charge splits equally in M (not quite true), then with M half the size of M, q = q M M EE Sample and Hold Amplifier Input dependent charge from S onto When S turns off, charge q adds to V OUT is then equal to V IN +q/ where q has a non-linear dependence on V IN We can improve on this by making V OUT independent of sampling switch charge EE37 7-4

13 Two phases S/H Amplifier Phase : S and S closed, V IN sampled on Phase : S 3 closed, is tied to V OUT Phase harge on is V IN S opens, injecting signal indep. charge at node X Then S opens, injecting signal dependent charge q onto + p EE Phase S/H Amplifier Node X is a virtual ground and charge on p is zero harge on is still V IN S 3 injects charge on X that must be discharged due to virtual ground node it does not disturb charge on V OUT =V IN S / S 3 are non-overlapping, S slightly ahead of S EE37 7-6

14 Gain of the S/H Finite OTA gain reduces gain of sampler On Phase, charges to V IN On Phase, node X goes from 0 to V X = -V OUT /A harge comes from, changing q to V IN + p V X V OUT -(V IN + p V X )/ = V X V OUT VIN = p + A + p VIN + A EE Speed of the S/H In sampling mode (Phase ) At node X, R X ~ /G m, τ ~ (R on +/G m ) In amplification mode (Phase ) Replace charge on by voltage source V IN (like switching in voltage source at start of Phase ) After analysis, τ = ( L p + p + L )/G M Reduces to τ ~ L /G M if p is small R on V IN V IN R on X G M V X R O V OUT p X G M V X R O V OUT L EE37 7-8

15 Basic Amplifier Sampling phase when S and S closed Input signal sampled onto Amplifying phase when S 3 closed harge on transferred to so that the final output is VOUT = VIN EE Basic Amplifier S must open before S for the charge injection to be signal independent harge from S opening is deposited on, but is not signal dependent harge from S opening causes glitch in V OUT When S 3 closes, V OUT goes to final value, regardless of what happened between S opening and S 3 closing EE

16 Precision Gain- Sampling phase when S, S, S 3 closed Input signal sampled onto and Amplifying phase when S 4, S 5 closed harge on is transferred to, doubling the charge on Final output is V IN since = S 4 S S 3 V IN S S 5 V OUT EE Precision Gain- How is it more precise? The feedback factor in both gain circuits is + + p In the precision Gain- circuit, =, while the basic amplifier has =, resulting in a smaller feedback factor and a slower circuit The gain error is inversely proportional to the feedback factor, so the precision circuit is more accurate for a given amplifier gain A V + OUT + p VIN A EE37 7-3

17 Resistor Equivalence of S Average current through switched-capacitor φ : Q = V φ : Q = V Q Q ( V V) IAVG = = T T Equivalent current through a resistor (f IN << f S ) V V IEQ = REQ T R = = f EQ EE37 S 7-33 Switched-apacitor Integrator s s V I V O Two non-overlapping clock phases control s,s Phase : Sampling phase input is sampled onto capacitor Phase : Integrating phase additional charge is added to previous charge on EE

18 Switched-apacitor Integrator -VO[n] +VO[n] -VO[n]+VI[n] +VO[n]-VI[n] Final charge on L.S. of is +V O [n+] + V [ n+ ] = + V [ n] V[ n] O O I zvo( z ) = VO( z ) VI( z ) VO ( z) = V z EE37 I 7-35 Parasitic Sensitive Parasitic capacitances p, p3 and p4 have no impact on transfer function p in parallel with, changes transfer function V ( + p) O ( z ) = V z I EE

19 Parasitic Insensitive p3 p4 V I p p V O Transfer function is non-inverting, delaying V V O I ( z) = z EE Parasitic Insensitive Parasitics have no impact on transfer function Better linearity since non-linear capacitors are unimportant Top plate on virtual ground node Minimizes parasitics, improves amplifier speed and resolution, reduces noise coupled to node Two extra switches needed More power to drive the switches for the same onresistance EE

20 Delay-Free Integrator Same structure, still parasitic insensitive Transfer function is inverting, delay-free VO z ( z) = V z I EE Bootstrapping At low supply voltages, signal swing is limited Maximum distortion determines the tolerable variation in R ON, and this limits the signal swing Want to increase V GS on the sampling switch an do this by increasing the supply voltage for the sampling switch, but this requires slower thick oxide devices Alternatively, add a constant voltage to the input signal and use that as the gate voltage keep V GS constant, reducing the variation in R ON EE

21 Bootstrapped ircuit Basic operation φ : is charged to V DD and gate of sampling switch is discharged to V SS (turned off) φ : V IN is added to voltage across, sampling switch turns on, gate voltage of the sampling switch is V IN + V DD V SS V DD S S Ideally, there is S 3 S 4 always V GS = V DD for the sampling switch S 5 V IN V OUT V SS EE Bootstrapped ircuit must be sized so that charge sharing between gate capacitance of switch is not significant VG = VIN + VDD + Rise time controlled by size of S 4, fall time controlled by size of S 5 G Extra transistors required to limit gate-source voltages to V DD and prevent overstress See Dessouky, JSS Mar.00 EE37 7-4

22 Switched-apacitor MFB Two parts to the circuit First, sense the common mode of the output Second, compare the common mode to the expected common mode, and adjust the bias accordingly Sensing ould use resistors they are either too small and reduce the gain, or they can get prohibitively large ould use capacitors they don t reduce the gain, but the voltage across them is undefined The voltage across them can be refreshed every clock cycle EE Switched-apacitor MFB One alternative Phase : precharge capacitors to ideal value Phase : sense the difference and adjust the bias accordingly But there may be large changes in the tail current bias EE

23 Switched-apacitor MFB Solution: Part of the tail current source can be controlled by a constant bias voltage Will this work? V B V M V M V IN + V IN - V B P V B EE37 ½ size ½ size 7-45 Switched-apacitor MFB Alternatively, use capacitors so that only a fraction of the charge is shared to adjust the bias voltage Typically, is 4-0 times EE

24 NLOTD: Schmitt Trigger EE What You Learned Today. Errors introduced with simple sampling switch RON variation, charge injection. Main S ircuits S/H, Gain and Integrators Parasitic Insensitive Signal-independent charge injection 3. Bootstrapped ircuit 4. Switched apacitor MFB EE