Investigation of Comparator Topologies and their Usage in a Technology Independent Flash-ADC Testbed

Transcription

1 Investigation of Comparator Topologies and their Usage in a Technology Independent Flash-ADC Testbed Cand.-Ing. Öner B. Ergin Prof. Dr.-Ing. Klaus Solbach Department of Microwave and RF-Technology University of Duisburg-Essen Dipl.-Ing. Harald Bothe and Dipl.-Ing. Reimund Wittmann Nokia Research Center Bochum Prof. Dr.-Ing. Werner Schardein University of Applied Sciences and Arts Dortmund

2 Contents Introduction ( ADCs ) State-of-the-Art Analog-to-Digital Converters Flash ADC Comparators Comparator Selection Procedure Flash ADC Testbed Verification in 65 nm Technology Conclusion

3 Introduction: Generic Engineering Model Variety of process technologies increases Circuits have to be rebuilt for every process ( GEM ) The Generic Engineering Model Circuits are portable to all technologies Automatical symbol, schematic, layout and testbench generation During this thesis, all circuits were developed using the GEM approach

4 Introduction: Selection methodology Selection methodology on top of GEM implementation allows parameterizable layout solutions Main high level design constraints: Power Supply voltage Area Bit resolution ( rate Speed (clock Comparator topologies are investigated with respect to the above listed constraints for flash ADC implementation

5 Contents Introduction ( ADCs ) State-of-the-Art Analog-to-Digital Converters Flash ADC Comparators Comparator Selection Procedure Flash ADC Testbed Verification in 65 nm Technology Conclusion

6 State-of-the-Art ADCs ADCs are developed for high speed or high resolution High resolution and high speed leads to high die size (high costs and ( effort implementation

7 Contents Introduction ( ADCs ) State-of-the-Art Analog-to-Digital Converters Flash ADC Comparators Comparator Selection Procedure Flash ADC Testbed Verification in 65 nm Technology Conclusion

8 Flash ADC Fastest ADC structure 2 N resistors, 2 N -1 comparators, thermometer-code to binary encoder Single-ended or differential type (wider ( range intensity Drawbacks (bit wise increase): Area and power double approximately Resistor matching becomes more critical Input bandwidth limited by increasing input capacitance

9 Contents Introduction ( ADCs ) State-of-the-Art Analog-to-Digital Converters Flash ADC Comparators Comparator Specifications Latch-Type Topologies SC-Type Topologies Simulation Results in 65 nm Technology Comparator Selection Procedure Flash ADC Testbed Verification in 65 nm Technology Conclusion

10 Comparators: Specifications Widely used components, especially in ADCs Comparator as 1-bit ADC Important specifications for implementation in flash ADCs: ( ADC Bit resolution ( maximum bit resolution of flash ( range Input common mode range (ICMR) ( maximum flash ADC approximation ( ADC Speed ( maximum speed of flash Power ( minimum power dissipation of flash ADC (after division by the number of (( comparators No Sample & Hold block needed when clocked comparators are implemented e.g. Latch-type comparators SC-type comparators

11 Contents Introduction ( ADCs ) State-of-the-Art Analog-to-Digital Converters Flash ADC Comparators Comparator Specifications Latch-Type Topologies SC-Type Topologies Simulation Results in 65 nm Technology Comparator Selection Procedure Flash ADC Testbed Verification in 65 nm Technology Conclusion

12 Comparators: Latch-Type Topologies Latch-type topologies Dynamic latched 4-inputs Class AB latched 4-inputs Static latched 2-inputs 4-inputs Principle: Positive-feedback circuit Phases: regeneration (latch=0) and amplification Advantages: High and rapid amplification Low area Low power Disadvantages: Kickback noise is the main challenge (Charge transfer between the input and the positive-feedback circuit ( active when the amplification phase is Mismatch and parasitic sensitivity are additional drawbacks Output changes to opposed digital state in the regeneration phase Solution: SR-Latch at the output

13 Comparators: Latch-Type: 2-inputs Dynamic Latched Latch-type topologies Dynamic latched 4-inputs Class AB latched 4-inputs static latched 2-inputs 4-inputs + High speed + Low power + Low area High parasitic sensitivity Limited ICMR

14 Comparators: Latch-Type: 4-inputs Class AB Latched Latch-type topologies Dynamic latched 4-inputs Class AB latched 4-inputs static latched + High speed + Low power + Low area + Rail-to-rail ICMR Not equal resolution at different references

15 Contents Introduction ( ADCs ) State-of-the-Art analog-to-digital converters Flash ADC Comparators Comparator Specifications Latch-Type Topologies SC-Type Topologies Simulation Results in 65 nm Technology Comparator Selection Procedure Flash ADC Testbed Verification in 65 nm Technology Conclusion

16 Comparators: SC-Type Topologies SC-type topologies 2-inputs IOS 2-inputs OOS 4-inputs OOS Singlestage Multistage Principle: Periodically sense and store the offset on capacitors Phases: Offset cancellation, amplification and latch A PMOS-input differential amplifier is used as the preamplifier The latch part is represented by the 2-inputs dynamic latched comparator Advantages High Resolution Disadvantages High area High power

17 Comparators: SC-Type: 2-inputs IOS SC-type topologies 2-inputs IOS 2-inputs OOS 4-inputs OOS Singlestage Multistage IOS: Input offset storage + Rail-to-rail ICMR + High resolution High area High power

18 Comparators: SC-Type: 4-inputs OOS SC-type topologies 2-inputs IOS 2-inputs OOS 4-inputs OOS OOS: Output offset storage + Rail-to-rail ICMR + High resolution High area High power

19 Contents Introduction ( ADCs ) State-of-the-Art Analog-to-Digital Converters Flash ADC Comparators Comparator Specifications Latch-Type Topologies SC-Type Topologies Simulation Results in 65 nm Technology Comparator Selection Procedure Flash ADC Testbed Verification in 65 nm Technology Conclusion

20 Comparators: Results: Area and Resolution Area [µm²] Latch-type comparators Low area Parasitic sensitivity degrades maximum resolution SC-type comparators High area Less parasitic sensitivity Conclusion: Lower area leads to less area consumption Class AB latched layout 2-input dynamic latched layout Class AB latched layout 2-input dynamic latched layout IOS layout Resolution [bits] for layouted Comparators IOS layout OOS 4in layout OOS 4in layout 0,8 1 1,2

21 Comparators: Results: Speed and Power Speed [MHz] ,8 1 1, input dynamic latched layout Class AB latched Static latched 2-input dynamic latched 4-input dynamic latched Class AB latched layout IOS IOS layout Multi IOS OOS 2in OOS 4in OOS 4in layout Power [µw] at 10 MHz 70,00 60,00 50,00 40,00 30,00 20,00 0,8 1 1,2 10,00 0,00 2-input dynamic latched layout Class AB latched Static latched 2-input dynamic latched 4-input dynamic latched Class AB latched layout IOS IOS layout Multi IOS OOS 2in OOS 4in OOS 4in layout

22 Contents Introduction ( ADCs ) State-of-the-Art Analog-to-Digital Converters Flash ADC Comparators Comparator Selection Procedure Flash ADC Testbed Verification in 65 nm Technology Conclusion

23 Parameters Technology Bit resolution Speed Approximation range Supply voltage 2-inputs / 4-inputs Comparator Selection Procedure Comparator selection routine Output Relevant topologies Area consumptions Power dissipations Flash ADC testbed GEM FAT tree encoder with single bubble error correction array GEM Comparator GEM Poly resistor array GEM

24 Contents Introduction ( ADCs ) State-of-the-Art Analog-to-Digital Converters Flash ADC Comparators Comparator Selection Procedure Flash ADC Testbed Verification in 65 nm Technology Layouts DNL/INL Results Conclusion

25 Flash ADC Testbed: Layouts: 4bit-flash ADC Checked and verified for resolutions ( LVS between 4 and 10 bit (DRC & Compatible for all analyzed comparators Dimension scalability: (x-y distribution of comparators & ( adjustable resistors is 4bit Flash ADC layout; Implemented comparator: 2-inputs dynamic latched

26 Flash ADC Testbed: Layouts: Dimension Scalability with 8bit-Flash ADC Scalable X-Y distribution of resistors & comparators Left: 32 blocks with each 8 comparators & resistors Right: 16 blocks with each 16 comparators & resistors Implemented Comparator: 4-inputs Class AB latched

27 Contents Introduction ( ADCs ) State-of-the-Art Analog-to-Digital Converters Flash ADC Comparators Comparator Selection Procedure Flash ADC Testbed Verification in 65 nm Technology Layouts DNL/INL Results Conclusion

28 Flash ADC Testbed: DNL / INL Results 0,16 DNL / INL Results 4 bits, 10 MHz 0,25 DNL / INL Results 5 bits, 10 MHz 0,14 0,12 0,2 0,1 0,08 0,06 DNL INL 0,15 0,1 DNL INL 0,04 0,02 0,05 0 Class AB latched layout 2-input dynamic latched layout IOS layout OOS 4in layout 0 Class AB latched layout 2-input dynamic latched layout IOS layout OOS 4in layout

29 Contents Introduction ( ADCs ) State-of-the-Art Analog-to-Digital Converters Flash ADC Comparators Comparator Selection Procedure Flash ADC Testbed Verification in 65 nm Technology Conclusion

30 Conclusion Investigation of relevant comparator topologies: Latch-type comparators:+ high speed, + low area, + low power, - high parasitic sensitivity SC-type comparators: - low speed, - high area, - high power, + low parasitic sensitivity Investigation and implementation of comparator selection procedure for the flash ADC testbed A flash ADC GEM testbed has been developed, which is compatible to all analyzed comparators Checked and verified (DRC, LVS) for resolutions between 4 and 10 bits Integration of x-y dimension scalability Complex FAT tree encoder with single bubble error correction array implemented Functional verification (simulation of schematic and extracted layout view) has been done in 65 nm technology Selection methodology verified for all analyzed comparators Main advantage of the selection methodology: Simplification of selection and implementation of flash ADCs referring to high-level demands

31 Thank you for your attention!