EE247 Lecture 15. EE247 Lecture 15

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1 EE47 Lecture 5 Administrative issues Midterm exam postponed to Tues. Oct. 8th o You can only bring one 8x paper with your own written notes (please do not photocopy) o No books, class or any other kind of handouts/notes, calculators, computers, PDA, cell phones... o Midterm includes material covered to end of lecture 4 EECS 47- Lecture 5 Data Converters:DAC Design (continued) 8 H.K. Page EE47 Lecture 5 D/A converters Static performance of D/As (continued) Systematic & random errors Practical aspects of current-switched DACs Segmented current-switched DACs DAC dynamic non-idealities DAC design considerations Self calibration techniques Current copiers Dynamic element matching DAC reconstruction filter EECS 47- Lecture 5 Data Converters:DAC Design (continued) 8 H.K. Page

2 Summary Last Lecture D/A converter architectures: Resistor string DAC Serial charge redistribution DAC Parallel charge scaling DAC Combination of resistor string (MSB) & binary weighted charge scaling (LSB) Current source DAC Unit element Binary weighted Static performance Component matching-systematic & random errors Component random variations Gaussian pdf NL for both unit-element DAC: σ NL = σ ε x B/- DNL for unit-element: σ DNL = σ ε EECS 47- Lecture 5 Data Converters:DAC Design (continued) 8 H.K. Page 3 DAC NL σ NL /σ ε n σe = n σ ( ε B -).5 / N dσ E To find max. variance: = dn N n= N / σe = σε 4 Error is maximum at mid-scale (N/): σ NL B = σε B with N =.5 n/n NL depends on both DAC resolution & element matching σ ε While σ DNL = σ ε is to first order independent of DAC resolution and is only a function of element matching Ref: Kuboki et al, TCAS, 6/98 EECS 47- Lecture 5 Data Converters:DAC Design (continued) 8 H.K. Page 4

3 DNL [LSB] Simulation Example Bit converter DNL and NL -.4 / +.3 LSB σ ε = % B = Random # generator used in MatLab NL LSB] bin -. / +.8 LSB bin Computed NL: σ NL max =.3 LSB (midscale) Why is the results not as expected per our derivation? EECS 47- Lecture 5 Data Converters:DAC Design (continued) 8 H.K. Page 5 NL & DNL for Binary Weighted DAC NL same as for unit element DAC out DNL depends on transition Example: to σ DNL = σ (dι/ι) to σ DNL = 3σ (dι/ι) B- ref 4 ref ref ref Consider MSB transition: EECS 47- Lecture 5 Data Converters:DAC Design (continued) 8 H.K. Page 6

4 8 4 8 ref 4 ref DAC DNL Example: 4bit DAC ref out ref DNL depends on transition Example: to σ DNL = σ (dιref/ιref) to σ DNL = 3σ (dιref/ιref) Analog Output [ ref ] on 4, off, off on, on on, off on. on 8, off 4, off, off 8 off, 4 on, on, on Digital nput EECS 47- Lecture 5 Data Converters:DAC Design (continued) 8 H.K. Page 7. Binary Weighted DAC DNL σ DNL / σ ε 5 5 DNL for a 4-Bit DAC DAC Output [LSB] Worst-case transition occurs at mid-scale: ( ) ε ( ) B B DNL = + ε σ σ σ Bσ ε σdnl = B/ max σε B σnlmax σε σdnl max Example: B =, σ ε = % σ DNL =.64 LSB σ NL =.3 LSB EECS 47- Lecture 5 Data Converters:DAC Design (continued) 8 H.K. Page 8

5 MOS Current Source Variations Due to Device Matching Effects d d d = d + d = d d d d d dd d dv = + V V W L W L GS th th d d Current matching depends on: - Device W/L ratio matching Larger device area less mismatch effect - Current mismatch due to threshold voltage variations: Larger gate-overdrive less threshold voltage mismatch effect EECS 47- Lecture 5 Data Converters:DAC Design (continued) 8 H.K. Page 9 Current-Switched DACs in CMOS out ref Switch Array d W d d L dvth = + V V W d L GS th Advantages: Example: 8bit Binary Weighted Can be very fast Reasonable area for resolution < 9-bits Disadvantages: Accuracy depends on device W/L & V th matching EECS 47- Lecture 5 Data Converters:DAC Design (continued) 8 H.K. Page

6 Unit Element versus Binary Weighted DAC Unit Element DAC σ = σ DNL ε B σ σ NL ε Binary Weighted DAC B σ σ = σ DNL ε NL B σ σ NL ε Number of switched elements: S = B S = B Key point: Significant difference in performance and complexity! EECS 47- Lecture 5 Data Converters:DAC Design (continued) 8 H.K. Page Another Random Run DNL [LSB] NL [LSB] DNL and NL of Bit converter - / +. LSB, bin -.8 / +.8 LSB bin Now (by chance) worst DNL is mid-scale. Close to statistical result! EECS 47- Lecture 5 Data Converters:DAC Design (continued) 8 H.K. Page

7 Bit DAC DNL/NL Comparison Plots: Simulation Runs Overlaid Ref: C. Lin and K. Bult, "A -b, 5- MSample/s CMOS DAC in.6 mm," EEE Journal of Solid-State Circuits, vol. 33, pp , December 998. Note: σ ε =% EECS 47- Lecture 5 Data Converters:DAC Design (continued) 8 H.K. Page 3 Bit DAC DNL/NL Comparison Plots: RMS for Simulation Runs Ref: C. Lin and K. Bult, "A -b, 5- MSample/s CMOS DAC in.6 mm," EEE Journal of Solid-State Circuits, vol. 33, pp , December 998. Note: σ ε =% EECS 47- Lecture 5 Data Converters:DAC Design (continued) 8 H.K. Page 4

8 DAC NL/DNL Summary DAC choice of architecture has significant impact on DNL NL is independent of DAC architecture and requires element matching commensurate with overall DAC precision Results assume uncorrelated random element variations Systematic errors and correlations are usually also important and may affect final DAC performance Ref: Kuboki, S.; Kato, K.; Miyakawa, N.; Matsubara, K. Nonlinearity analysis of resistor string A/D converters. EEE Transactions on Circuits and Systems, vol.cas-9, (no.6), June 98. p EECS 47- Lecture 5 Data Converters:DAC Design (continued) 8 H.K. Page 5 Unit Element versus Binary Weighted DAC Example: B= Unit Element DAC σ DNL = σ ε Binary Weighted DAC σ DNL = B σ 3 ε σ ε σ σ 6σ B NL ε = ε σ NL Number of switched elements: = B σ 6 ε σ ε B S = = 4 S = B= Significant difference in performance and complexity! EECS 47- Lecture 5 Data Converters:DAC Design (continued) 8 H.K. Page 6

9 Segmented DAC Combination of Unit-Element & Binary-Weighted Objective: Compromise between unit-element and binary-weighted DAC MSB (B bits) (B bits) LSB Unit Element Binary Weighted Approach: B MSB bits unit elements B LSB bits binary weighted V Analog B Total = B +B NL: unaffected same as either architecture DNL: Worst case occurs when LSB DAC turns off and one more MSB DAC element turns on Same as binary weighted DAC with (B +) # of bits Number of switched elements: ( B -) + B EECS 47- Lecture 5 Data Converters:DAC Design (continued) 8 H.K. Page 7 Comparison Example: B =, B = 5, B = 7 B = 6, B = 6 MSB Assuming: σ ε = % DAC Architecture (B+B) Unit element (+) Segmented (6+6) Segmented (5+7) Binary weighted(+) LSB σ NL[LSB] DNL NL ( B + ) σ σ = σ σ B B σ ε ε S = + B σ DNL[LSB] NL # of switched elements =69 3+7=38 EECS 47- Lecture 5 Data Converters:DAC Design (continued) 8 H.K. Page 8

10 Practical Aspects Current-Switched DACs Unit element DACs ensure monotonicity by turning on equal-weighted current sources in succession Typically current switching performed by differential pairs For each diff pair, only one of the devices are on switch device mismatch not an issue ssue: While binary weighted DAC can use the incoming binary digital word directly, unit element requires a decoder Binary Thermometer N to ( N -) decoder EECS 47- Lecture 5 Data Converters:DAC Design (continued) 8 H.K. Page 9 4-bit MSB Unit element DAC + 4-bit binary weighted DAC Note: 4-bit MSB DAC requires extra 4-to-6 bit decoder Digital code for both DACs stored in a register Segmented Current-Switched DAC Example: 8bit 4MSB+4LSB EECS 47- Lecture 5 Data Converters:DAC Design (continued) 8 H.K. Page

11 Segmented Current-Switched DAC Cont d 4-bit MSB Unit element DAC + 4- bit binary weighted DAC Note: 4-bit MSB DAC requires extra 4-to-6 bit decoder Digital code for both DACs stored in a register EECS 47- Lecture 5 Data Converters:DAC Design (continued) 8 H.K. Page Segmented Current-Switched DAC Cont d MSB Decoder Domino logic Example: D4,5,6,7= OUT= Domino Logic Register Latched NAND gate: CTRL= OUT=NB N Register EECS 47- Lecture 5 Data Converters:DAC Design (continued) 8 H.K. Page

12 Segmented Current-Switched DAC Reference Current Considerations ref is referenced to V DD Problem: Reference current varies with supply voltage + - ref =(V DD -V ref ) / R EECS 47- Lecture 5 Data Converters:DAC Design (continued) 8 H.K. Page 3 ref is referenced to V ss GND Segmented Current-Switched DAC Reference Current Considerations + - ref =(V ref -V ss ) / R EECS 47- Lecture 5 Data Converters:DAC Design (continued) 8 H.K. Page 4

13 Segmented Current-Switched DAC Considerations Example: bit MSB Unit element DAC & 3bit binary weighted DAC To ensure monotonicity at the MSB LSB transition: First OFF MSB current source is routed to LSB current generator LSB MSB EECS 47- Lecture 5 Data Converters:DAC Design (continued) 8 H.K. Page 5 DAC Dynamic Non-dealities Finite settling time Linear settling issues: (e.g. RC time constants) Slew limited settling Spurious signal coupling Coupling of clock/control signals to the output via switches Timing error related glitches Control signal timing skew EECS 47- Lecture 5 Data Converters:DAC Design (continued) 8 H.K. Page 6

14 Dynamic DAC Error: Timing Glitch Consider binary weighted DAC transition DAC output depends on timing Plot shows situation where the control signals for LSB & MSB LSB/MSBs on time LSB early, MSB late LSB late, MSB early deal Late 5 Early 5 5 DAC Output Time EECS 47- Lecture 5 Data Converters:DAC Design (continued) 8 H.K. Page 7 Glitch Energy Glitch energy (worst case) proportional to: dt x B- dt error in timing & B- associated with half of the switches changing state LSB energy proportional to: T=/f s Need dt x B- << T or dt << -B+ T Examples: f s [MHz] B 6 dt [ps] << 488 <<.5 << Timing accuracy for data converters much more critical compared to digital circuitry EECS 47- Lecture 5 Data Converters:DAC Design (continued) 8 H.K. Page 8

15 DAC Dynamic Errors To suppress effect of non-idealities: Retiming of current source control signals Each current source has its own clocked latch incorporated in the current cell Minimization of latch clock skew by careful layout ensuring simultaneous change of bits To minimize control and clock feed through to the output via G-D & G-S of the switches Use of low-swing digital circuitry EECS 47- Lecture 5 Data Converters:DAC Design (continued) 8 H.K. Page 9 DAC mplementation Examples Untrimmed segmented T. Miki et al, An 8-MHz 8-bit CMOS D/A Converter, JSSC December 986, pp. 983 A. Van den Bosch et al, A -GSample/s Nyquist Current-Steering CMOS D/A Converter, JSSC March, pp. 35 Current copiers: D. W. J. Groeneveld et al, A Self-Calibration Technique for Monolithic High-Resolution D/A Converters, JSSC December 989, pp. 57 Dynamic element matching: R. J. van de Plassche, Dynamic Element Matching for High- Accuracy Monolithic D/A Converters, JSSC December 976, pp. 795 EECS 47- Lecture 5 Data Converters:DAC Design (continued) 8 H.K. Page 3

16 8x8 array μ tech., 5Vsupply 6+ segmented EECS 47- Lecture 5 Data Converters:DAC Design (continued) 8 H.K. Page 3 Two sources of systematic error: - Finite current source output resistance - Voltage drop due to finite ground bus resistance EECS 47- Lecture 5 Data Converters:DAC Design (continued) 8 H.K. Page 3

17 Current-Switched DACs in CMOS Assumptions: Rx small compared to transistor gate-overdrive To simplify analysis: nitially, all device currents assumed to be equal to V = V 4R GS M GS M V = V 7R GS M3 GS M out V = V 9R GS GS M4 M5 = GS GS M V = V R = k M ( VGS Vth) M V GS 4R M V th V G V DD M 5 M M M 3 M Rx4 Rx3 Rx Rx Example: 5 unit element current sources EECS 47- Lecture 5 Data Converters:DAC Design (continued) 8 H.K. Page 33 Current-Switched DACs in CMOS 4R = k( VGS V ) M th = VGS V M th g m = M VGS V M th 4Rgm M 4Rgm = ( ) 7Rgm 3 m ( ) M 7Rg = 9Rgm 4 m ( ) M 9Rg = Rgm 5 m ( ) M Rg = Desirable to have g m small M M M M out V DD M 5 M M M 3 M Rx4 Rx3 Rx Rx Example: 5 unit element current sources EECS 47- Lecture 5 Data Converters:DAC Design (continued) 8 H.K. Page 34

18 NL [LSB] Current-Switched DACs in CMOS Example: NL of 3-Bit unit element DAC nput Sequential current source switching Symmetrical current source switching Example: 7 unit element current source DAC- assume g m R=/ f switching of current sources arranged sequentially ( ) NL= +.5LSB f switching of current sources symmetrical ( ) NL = +.9, -.58LSB NL reduced by a factor of.6 EECS 47- Lecture 5 Data Converters:DAC Design (continued) 8 H.K. Page 35 Current-Switched DACs in CMOS Example: DNL of 7 unit element DAC. DNL [LSB] Sequential current source switching Symmetrical current source switching nput Example: 7 unit element current source DAC- assume g m R=/ f switching of current sources arranged sequentially ( ) DNL max = +.5LSB f switching of current sources symmetrical ( ) DNL max = +.5LSB DNL unchanged EECS 47- Lecture 5 Data Converters:DAC Design (continued) 8 H.K. Page 36

19 (5+5) More recent published DAC using symmetrical switching built in.35μ/3v analog/.9v digital, area x smaller compared to previous example EECS 47- Lecture 5 Data Converters:DAC Design (continued) 8 H.K. Page 37 Layout of Current sources -each current source made of 4 devices in parallel each located in one of the 4 quadrants Thermometer decoder used to convert incoming binary digital control for the 5 MSB bits Dummy decoder used on the LSB side to match the latency due to the MSB decoder EECS 47- Lecture 5 Data Converters:DAC Design (continued) 8 H.K. Page 38

20 Current source layout MSB current sources layout in the mid sections of the four quad LSB current sources on the periphery Two rows of dummy current sources the periphery to create identical environment for devices in the center versus the ones on the outer sections EECS 47- Lecture 5 Data Converters:DAC Design (continued) 8 H.K. Page 39 Note that each current cell has its clocked latch and clock signal laid out to be close to its switch to ensure simultaneous switching of current sources Special attention paid to the final latch to have the cross point of the complementary switch control signal such that the two switches are not both turned off during transition EECS 47- Lecture 5 Data Converters:DAC Design (continued) 8 H.K. Page 4

21 Measured DNL/NL with current associated with the current cells as variable EECS 47- Lecture 5 Data Converters:DAC Design (continued) 8 H.K. Page 4 EECS 47- Lecture 5 Data Converters:DAC Design (continued) 8 H.K. Page 4

22 6bit DAC (6+)- MSB DAC uses calibrated current sources / / Current Divider EECS 47- Lecture 5 Data Converters:DAC Design (continued) 8 H.K. Page 43 EECS 47- Lecture 5 Data Converters:DAC Design (continued) 8 H.K. Page 44

23 Current Divider Accuracy d+ d = d = d d d d d d W d d d L = dvth W + d V GS V th L / / M M deal Current Divider /+d d / M M /-d d / Real Current Divider M& M mismatched Problem: Device mismatch could severely limit DAC accuracy EECS 47- Lecture 5 Data Converters:DAC Design (continued) 8 H.K. Page 45 EECS 47- Lecture 5 Data Converters:DAC Design (continued) 8 H.K. Page 46

24 Dynamic Element Matching During Φ During Φ () = o +Δ () = o Δ ( ) ( ) () () + = ( Δ ) + ( +Δ ) o = o () = o Δ () = o +Δ ( ) ( ) f clk o / o / / error Δ o EECS 47- Lecture 5 Data Converters:DAC Design (continued) 8 H.K. Page 47 EECS 47- Lecture 5 Data Converters:DAC Design (continued) 8 H.K. Page 48

25 Dynamic Element Matching () () = o( + Δ) = o( Δ) () () = ( Δ ) = ( + Δ ) During Φ During Φ o / o /4 o /4 o o f clk 3 4 () 3 = = () 4 o ( + Δ ) ( + Δ )( + Δ ) () 3 = = () 4 o ( Δ ) ( Δ )( Δ ) / error Δ 3 () 3 + = o = 4 o = 4 () 3 ( + Δ )( + Δ ) + ( Δ )( Δ ) ( + Δ Δ ) f clk / error Δ E.g. Δ = Δ = % matching error is (%) =.% o EECS 47- Lecture 5 Data Converters:DAC Design (continued) 8 H.K. Page 49 Bipolar -bit DAC using dynamic element matching built in 976 Element matching clock frequency khz NL <.5LSB! EECS 47- Lecture 5 Data Converters:DAC Design (continued) 8 H.K. Page 5

26 Example: Stateof-the-Art current steering DAC 6bit unit-element 8bit binary EECS 47- Lecture 5 Data Converters:DAC Design (continued) 8 H.K. Page 5 EECS 47- Lecture 5 Data Converters:DAC Design (continued) 8 H.K. Page 5

27 DAC n the Big Picture Learned to build DACs Convert the incoming digital signal to analog DAC output staircase form Some applications require filtering (smoothing) of DAC output reconstruction filter Analog nput Analog Preprocessing A/D Conversion DSP D/A Conversion Analog Post processing Analog Output Anti-Aliasing Filter Sampling +Quantization... "Bits to Staircase" Reconstruction Filter EECS 47- Lecture 5 Data Converters:DAC Design (continued) 8 H.K. Page 53 DAC Reconstruction Filter Need for and requirements depend on application Tasks: Correct for sinc droop Remove aliases (stair-case approximation) DAC nput sinc DAC Output.5 B f s / x x Normalized Frequency f/f s EECS 47- Lecture 5 Data Converters:DAC Design (continued) 8 H.K. Page 54

28 Reconstruction Filter Options Reconstruction Filters Digital Filter DAC SC Filter CT Filter Digital and SC filter possible only in combination with oversampling (signal bandwidth B << f s /) Digital filter Band limits the input signal prevent aliasing Could also provide high-frequency pre-emphasis to compensate in-band sinc amplitude droop associated with the inherent DAC S/H function EECS 47- Lecture 5 Data Converters:DAC Design (continued) 8 H.K. Page 55 DAC Reconstruction Filter Example: Voice-Band CODEC Receive Path Receive Output f s = 8kHz f s = 8kHz f s = 8kHz f s = 8kHz GSR Reconstruction Filter & sinx/x Compensator Note: f max sig = 3.4kHz f DAC s = 8kHz sin(π f max sig x T s )/(π f max sig xt s ) = -.75 db droop due to DAC sinc shape f s = 8kHz Ref: D. Senderowicz et. al, A Family of Differential NMOS Analog Circuits for PCM Codec Filter Chip, EEE Journal of Solid-State Circuits, Vol.-SC-7, No. 6, pp.4-3, Dec. 98. EECS 47- Lecture 5 Data Converters:DAC Design (continued) 8 H.K. Page 56

29 Summary D/A Converter D/A architecture Unit element complexity proportional to B - excellent DNL Binary weighted- complexity proportional to B- poor DNL Segmented- unit element MSB(B )+ binary weighted LSB(B ) Complexity proportional (( B -) + B ) -DNL compromise between the two Static performance Component matching Dynamic performance Time constants, Glitches DAC improvement techniques Symmetrical switching rather than sequential switching Current source self calibration Dynamic element matching Depending on the application, reconstruction filter may be needed EECS 47- Lecture 5 Data Converters:DAC Design (continued) 8 H.K. Page 57 What Next? Analog nput ADC Converters: Need to build circuits that "sample Need to build circuits for amplitude quantization Analog Preprocessing A/D Conversion DSP D/A Conversion Analog Post processing Analog Output Anti-Aliasing Filter Sampling +Quantization... "Bits to Staircase" Reconstruction Filter EECS 47- Lecture 5 Data Converters:DAC Design (continued) 8 H.K. Page 58

30 Analog-to-Digital Converters Two categories: Nyquist rate ADCs f sig max ~.5xf sampling Maximum achievable signal bandwidth higher compared to oversampled type Resolution limited to max. -4bits Oversampled ADCs f sig max <<.5xf sampling Maximum achievable signal bandwidth significantly lower compared to nyquist Maximum achievable resolution high (8 to bits!) EECS 47- Lecture 5 Data Converters:DAC Design (continued) 8 H.K. Page 59