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1 EE247 Lecture 16 D/A onverters (continued) DA reconstruction filter AD onverters Sampling Sampling switch considerations Thermal noise due to switch resistance lock jitter related non-idealities Sampling switch bandwidth limitations Switch conductance non-linearity induced distortion Sampling switch conductance dependence on input voltage lock voltage boosters Sampling switch charge injection & clock feedthrough EES 247 Lecture 16: Data onverters- AD Design 2010 Page 1 Summary Last Lecture D/A converters Practical aspects of current-switched DAs (continued) Segmented current-switched DAs DA dynamic non-idealities DA design considerations Self calibration techniques urrent copiers Dynamic element matching EES 247 Lecture 16: Data onverters- DA Design 2010 Page 2

2 DA Output sinc DA Input Learned to build DAs onvert the incoming digital signal to analog DA output staircase form Some applications require filtering (smoothing) of DA output Reconstruction filter DA In the Big Picture Analog Input Analog Preprocessing A/D onversion DSP D/A onversion Analog Post processing Analog Output Anti-Aliasing Filter Sampling +Quantization "Bits to Staircase" Reconstruction Filter EES 247 Lecture 16: Data onverters- AD Design 2010 Page 3 DA Reconstruction Filter Need for and requirements depend on application Tasks: orrect for sinc droop Remove aliases (stair-case approximation) B f s / x x Normalized Frequency f/f s EES 247 Lecture 16: Data onverters- AD Design 2010 Page 4

3 Reconstruction Filter Options Reconstruction Filters Digital Filter DA S Filter T Filter Reconstruction filter options: ontinuous-time filter only T + S filter S filter possible only in combination with oversampling (signal bandwidth B << f s /2) Digital filter Band limits the input signal prevent aliasing ould also provide high-frequency pre-emphasis to compensate inband sinx/x amplitude droop associated with the inherent DA S/H function EES 247 Lecture 16: Data onverters- AD Design 2010 Page 5 DA Reconstruction Filter Example: Voice-Band ODE Receive Path Receive Output f s = 8kHz f s = 8kHz f s = 128kHz f s = 128kHz GSR Reconstruction Filter & sinx/x ompensator f s = 128kHz Note: f max sig = 3.4kHz f DA s = 8kHz sin(p f max sig x T s )/(p f max sig xt s ) = db droop due to DA sinx/x shape Ref: D. Senderowicz et. al, A Family of Differential NMOS Analog ircuits for PM odec Filter hip, IEEE Journal of Solid-State ircuits, Vol.-S-17, No. 6, pp , Dec EES 247 Lecture 16: Data onverters- AD Design 2010 Page 6

4 Summary D/A onverter D/A architecture Unit element complexity proportional to 2 B - excellent DNL Binary weighted- complexity proportional to B- poor DNL Segmented- unit element MSB(B 1 )+ binary weighted LSB(B 2 ) omplexity proportional ((2 B1-1) + B 2 ) -DNL compromise between the two Static performance omponent matching Dynamic performance Time constants, Glitches DA improvement techniques Symmetrical switching rather than sequential switching urrent source self calibration Dynamic element matching Depending on the application, reconstruction filter may be needed EES 247 Lecture 16: Data onverters- AD Design 2010 Page 7 What Next? Analog Input AD onverters: Need to build circuits that "sample Need to build circuits for amplitude quantization Analog Preprocessing A/D onversion DSP D/A onversion Analog Post processing Analog Output Anti-Aliasing Filter Sampling +Quantization "Bits to Staircase" Reconstruction Filter EES 247 Lecture 16: Data onverters- AD Design 2010 Page 8

5 Analog-to-Digital onverters Two categories: Nyquist rate ADs f sig max ~ 0.5xf sampling Maximum achievable signal bandwidth higher compared to oversampled type Resolution limited to <14bits Oversampled ADs f sig max << 0.5xf sampling Maximum achievable signal bandwidth significantly lower compared to nyquist Maximum achievable resolution high (18 to 20bits!) EES 247 Lecture 16: Data onverters- AD Design 2010 Page 9 MOS Sampling ircuits EES 247 Lecture 16: Data onverters- AD Design 2010 Page 10

6 Ideal Sampling In an ideal world, zero resistance sampling switches would close for the briefest instant to sample a continuous voltage v IN onto the capacitor v IN 1 S1 v OUT Output Dirac-like pulses with amplitude equal to V IN at the time of sampling 1 T=1/f S In practice not realizable! EES 247 Lecture 16: Data onverters- AD Design 2010 Page 11 Ideal Track & Hold Sampling 1 v IN S1 v OUT 1 T=1/f S V out tracks input for ½ clock cycle when switch is closed Ideally acquires exact value of V in at the instant the switch opens "Track and Hold" (T/H) (often called Sample & Hold!) EES 247 Lecture 16: Data onverters- AD Design 2010 Page 12

7 Track Hold Ideal T/H Sampling ontinuous Time time T/H signal (Sampled-Data Signal) lock Discrete-Time Signal EES 247 Lecture 15: Data onverters- DA Design & Intro. to ADs 2010 Page 13 Practical Sampling Issues 1 v IN M1 v OUT Switch induced noise due to M1 finite channel resistance lock jitter (edge variation of 1 ) Finite R sw limited bandwidth finite acquisition time R sw = f(v in ) distortion Switch charge injection & clock feedthrough EES 247 Lecture 16: Data onverters- AD Design 2010 Page 14

8 Sampling ircuit kt/ Noise 1 4kTRDf v IN M1 v OUT v IN R S1 v OUT Switch resistance & sampling capacitor form a low-pass filter Noise associated with the switch resistance results in Total noise variance= the output (see noise analysis in Lecture 1) In high resolution ADs with such sampling circuit right at the input, kt/ noise at times dominates overall minimum signal handling capability (power dissipation considerations). EES 247 Lecture 16: Data onverters- AD Design 2010 Page 15 Sampling Network kt/ Noise For ADs sampling capacitor size is usually chosen based on having thermal noise smaller or equal or at times slightly larger compared to quantization noise: Assumption: Nyquist rate AD hoose such that 2 kbt D 12 2 D 12 thermal noise level is less (or equal) than Q noise For a Nyquist rate AD :Total quantizati on noise power 2 B kBT V FS 2B 2 12kBT 2 VFS EES 247 Lecture 16: Data onverters- AD Design 2010 Page 16

9 Sampling Network kt/ Noise Required min as a Function of AD Resolution B min (V FS = 1V) min (V FS = 0.5V) B 2 12kBT V 2 FS pf 0.8 pf 13 pf 206 pf 52,800 pf pf 2.4 pf 52 pf 824 pf 211,200 pf The large area required for limit highest achievable resolution for Nyquist rate ADs Oversampling results in reduction of required value for (will be covered in oversampled converter lectures) EES 247 Lecture 16: Data onverters- AD Design 2010 Page 17 Practical Sampling Issues 1 v IN M1 v OUT Switch induced noise due to M1 finite channel resistance lock jitter (edge variation of 1 ) Finite R sw limited bandwidth finite acquisition time R sw = f(v in ) distortion Switch charge injection & clock feedthrough EES 247 Lecture 16: Data onverters- AD Design 2010 Page 18

10 lock Jitter So far : clock signal controls sampling instants which we assumed to be precisely equi-distant in time (period T) Real clock generator some level of variability Variability in T causes errors "Aperture Uncertainty" or "Aperture Jitter What is the effect of clock jitter on AD performance? EES 247 Lecture 16: Data onverters- AD Design 2010 Page 19 lock Jitter Sampling jitter adds an error voltage proportional to the product of (t J -t 0 ) and the derivative of the input signal at the sampling instant x(t) x (t 0 ) actual sampling time t J nominal (ideal) sampling time t 0 EES 247 Lecture 16: Data onverters- AD Design 2010 Page 20

11 lock Jitter The error voltage is e = x (t 0 )(t J t 0 ) x(t) x (t 0 ) actual sampling time t J error Does jitter matter when sampling dc signals (x (t 0 )=0)? nominal sampling time t 0 EES 247 Lecture 16: Data onverters- AD Design 2010 Page 21 Effect of lock Jitter on Sampling of a Sinusoidal Signal Sinusoidal input Amplitude: Frequency: Jitter: p x( t ) Asin 2 f t max x x x max x A f x dt p x'( t ) 2p f Acos 2 f t x'( t ) 2p f A Then: e( t ) x'( t ) dt e( t ) 2p f Adt x Worst case # of Bits f s dt << A A FS s 2 x 2 D A e( t ) 2 2 dt 1 B 2 p f s f FS B1 1 MHz 20 MHz 1000 MHz f 78 ps 0.24 ps 0.07 ps EES 247 Lecture 16: Data onverters- AD Design 2010 Page 22

12 Statistical Jitter Analysis The worst case looks pretty stringent what about the average? Let s calculate the mean squared jitter error (variance) If we re sampling a sinusoidal signal x(t) = Asin(2pf x t), then x (t) = 2pf x Acos(2pf x t) E{[x (t)] 2 } = 2p 2 f x2 A 2 Assume the jitter has variance E{(t J -t 0 ) 2 } = 2 EES 247 Lecture 16: Data onverters- AD Design 2010 Page 23 Statistical Jitter Analysis If x (t) and the jitter are independent E{[x (t)(t J -t 0 )] 2 }= E{[x (t)] 2 } E{(t J -t 0 ) 2 } Hence, the jitter error power is E{e 2 } = 2p 2 f x2 A 2 2 If the jitter is uncorrelated from sample to sample, this jitter noise is white EES 247 Lecture 16: Data onverters- AD Design 2010 Page 24

13 Statistical Jitter Analysis DR jitter 2 A / p f A x p f x 20log 10 2pf x EES 247 Lecture 16: Data onverters- AD Design 2010 Page 25 Example: AD Spectral Tests SFDR SDR SNR SNR loss due to clock jitter f s Ref: W. Yang et al., "A 3-V 340-mW 14-b 75-Msample/s MOS AD with 85-dB SFDR at Nyquist input," IEEE J. of Solid-State ircuits, Dec EES 247 Lecture 15: Data onverters- DA Design & Intro. to ADs 2010 Page 26

14 Summary Effect of lock Jitter on AD Performance In cases where clock signal is provided from off-chip have to choose a clock signal source with low enough jitter On-chip precautions to keep the clock jitter less than single-digit pico-second : Separate supplies as much as possible Separate analog and digital clocks Short on-chip inverter chains between clock source and destination Few, if any, other analog-to-digital conversion non-idealities have the same symptoms as sampling jitter: RMS noise proportional to input signal frequency RMS noise proportional to input signal amplitude In cases where clock jitter limits the dynamic range, it s easy to tell, but may be difficult to fix... EES 247 Lecture 16: Data onverters- AD Design 2010 Page 27 Practical Sampling Issues 1 v IN M1 v OUT Switch induced noise due to M1 finite channel resistance lock jitter (edge variation of 1 ) Finite R sw limited bandwidth finite acquisition time R sw = f(v in ) distortion Switch charge injection & clock feedthrough EES 247 Lecture 16: Data onverters- AD Design 2010 Page 28

15 Sampling Acquisition Bandwidth The resistance R of switch S1 turns the sampling network into a lowpass filter with finite time constant: = R v IN R 1 S1 v OUT Assuming V in is constant or changing slowly during the sampling period and is initially discharged v out ( t) v in 1 e t / Need to allow enough time for the output to settle to less than 1 AD LSB determines minimum duration for 1 or maximum AD operating freq. 1 v invout d v EES 247 Lecture 16: Data onverters- AD Design 2010 Page 29 Sampling: Effect of Finite Switch On-Resistance V V D since V V 1 e tx tx t / in out out in Ts T 1 2 s Vine D or 2 V ln in D Worst ase: V V in FS 1 v IN v R OUT S1 Ts Ts B 2 ln 2 1 B R B 2 f ln 2 1 B f s s 1 t x Example: B = 14, min = 13pF, f s = 100MHz T s / >> 19.4, or 10 <<T s /2 R << 40 W T=1/f S EES 247 Lecture 16: Data onverters- AD Design 2010 Page 30

16 Practical Sampling Issues 1 v IN M1 v OUT Switch induced noise due to M1 finite channel resistance lock jitter (edge variation of 1 ) Finite R sw limited bandwidth finite acquisition time R sw = f(v in ) distortion Switch charge injection & clock feedthrough EES 247 Lecture 16: Data onverters- AD Design 2010 Page 31 Non-Linear Switch On-Resistance Switch MOS operating in triode mode: W VDS 1 di ID( triode) ox VGS VTH VDS, L 2 R dv D( triode) ON DS V 0 DS R ON 1 1 W W V V V V V L L ox GS th ox DD th in Let us call V =0 R then R R ON Ro Vin 1 V V DD in o o th 1 W V V L ox DD th V GS = V DD - V in V in 1 V DD M1 EES 247 Lecture 16: Data onverters- AD Design 2010 Page 32

17 Sampling Distortion Simulated 10-Bit AD & Sampling Switch modeled: v out v in 1e T s /2 = 5 V DD V th = 2V V FS = 1V T V in 1 2 VDD V th Results in HD2=-41dBFS & HD3=-51.4dBFS EES 247 Lecture 16: Data onverters- AD Design 2010 Page 33 Doubling sampling time (or ½ time constant) Results in: HD2 improved from -41dBFS to -70dBFS ~30dB HD3 improved from dBFS to -76.3dBFS ~25dB Sampling Distortion Allowing enough time for the sampling network settling Reduces distortion due to switch R non-linear behavior to a tolerable level 10bit AD T s /2 = 10 V DD V th = 2V V FS = 1V EES 247 Lecture 16: Data onverters- AD Design 2010 Page 34

Sampling Distortion Effect of Supply Voltage 10bit AD & T s /2 = 5 V DD V th = 2V V FS = 1V 10bit AD & T s /2 = 5 V DD V th = 4V V FS = 1V Effect of higher supply voltage on sampling distortion HD3

18 Sampling Distortion Effect of Supply Voltage 10bit AD & T s /2 = 5 V DD V th = 2V V FS = 1V 10bit AD & T s /2 = 5 V DD V th = 4V V FS = 1V Effect of higher supply voltage on sampling distortion HD3 decreased by (V DD1 /V DD2 ) 2 HD2 decreased by (V DD1 /V DD2 ) EES 247 Lecture 16: Data onverters- AD Design 2010 Page 35 Sampling Distortion SFDR sensitive to sampling distortion - improve linearity by: Larger V DD /V FS Higher sampling bandwidth Solutions: Overdesign Larger switches Issue: Increased switch charge injection Increased nonlinear S &D junction cap. Maximize V DD /V FS Decreased dynamic range if V DD const. omplementary switch onstant & max. V GS f(v in ) 10bit AD T s / = 20 V DD V th = 2V V FS = 1V EES 247 Lecture 16: Data onverters- AD Design 2010 Page 36

19 kt/ noise 2 12kBT VFS 0.72 R B f s 2B Finite R sw limited bandwidth g sw = f (V in ) distortion 2 Practical Sampling Summary So Far! v IN 1 M1 v OUT Vin W gon go 1 for go ox VDD Vth VDD V th L Allowing long enough settling time reduce distortion due to sw non-linear behavior EES 247 Lecture 16: Data onverters- AD Design, Sampling 2010 Page 37 Sampling Use of omplementary Switches 1 g o g n o g o T =gon + g o p 1B g o p 1 1B omplementary n & p switch advantages: Increase in the overall conductance lower time constant Linearize the switch conductance for the range V thp < Vin < Vdd - V thn EES 247 Lecture 16: Data onverters- AD Design, Sampling 2010 Page 38

20 omplementary Switch Issues Supply Voltage Evolution Supply voltage has scaled down with technology scaling Threshold voltages do not scale accordingly Ref: A. Abo et al, A 1.5-V, 10-bit, 14.3-MS/s MOS Pipeline Analog-to-Digital onverter, JSS May 1999, pp EES 247 Lecture 16: Data onverters- AD Design, Sampling 2010 Page 39 omplementary Switch Effect of Supply Voltage Scaling g effective g o n g o T =g on + g o p 1 g o p 1B 1 1B As supply voltage scales down input voltage range for constant g o shrinks omplementary switch not effective when V DD becomes comparable to 2xV th EES 247 Lecture 16: Data onverters- AD Design, Sampling 2010 Page 40

21 Boosted & onstant V GS Sampling V GS =const. OFF ON Gate voltage V GS =low Device off Beware of signal feedthrough due to parasitic capacitors Increase gate overdrive voltage as much as possible + keep V GS constant Switch overdrive voltage independent of signal level Error due to finite R ON linear (to 1st order) Lower R on lower time constant EES 247 Lecture 16: Data onverters- AD Design, Sampling 2010 Page 41 onstant V GS Sampling (= the switch input terminal) EES 247 Lecture 16: Data onverters- AD Design, Sampling 2010 Page 42

22 P_N onstant V GS Sampling ircuit VDD=3V M1 M2 M3 M8 M6 VP1 100ns P 1 PB 2 3 M12 P M4 M5 M9 Va VS1 1.5V 1MHz Vg M11 Vb hold This Example: All device sizes:w/l=10/0.35 All capacitor size: 1pF (except for hold) Note: Each critical switch requires a separate clock booster Sampling switch & Ref: A. Abo et al, A 1.5-V, 10-bit, 14.3-MS/s MOS Pipeline Analog-to-Digital onverter, JSS May 1999, pp EES 247 Lecture 16: Data onverters- AD Design, Sampling 2010 Page 43 lock Voltage Doubler VDD=03V M1 0ff 1 PB 03V P 2 M2 Saturation mode 03V 0(3V-V th M2 ) 00 M1 Triode Acquire charge 1 2 PB 3V0 VDD=3V M2 off 3V03V (3V-V th M2 ) (6V-V th M2 ) P 03V VP1 =clock 03V VP1 3V0 a) Start up b) Next clock phase EES 247 Lecture 16: Data onverters- AD Design, Sampling 2010 Page 44

23 lock Voltage Doubler M1 0ff 3V ~6V VDD=3V 1 PB 03V P VP1 M2 03V 2 3V0 M2 Triode (6V-V th M2 ) (3V-V th M2 ) ~ 3V Acquires charge Both 1 & 2 charged to VDD after 1.5 clock cycle Note that bottom plate of 1 & 2 is either 0 or VDD while top plates are at VDD or 2VDD c) Next clock phase EES 247 Lecture 16: Data onverters- AD Design, Sampling 2010 Page 45 lock Voltage Doubler VDD=3V 2VDD M1 M2 P_Boost R1 PB 1 2 R2 VDD P 0 VP1 lock period: 100ns *R1 & R2=1GOhm dummy resistors added for simulation only EES 247 Lecture 16: Data onverters- AD Design, Sampling 2010 Page 46

24 onstant V GS Sampler: F Low VDD=3V ~ 2 VDD (boosted clock) M3 Triode OFF VDD 3 M4 Sampling switch M11 is OFF VDD M12 Triode Input voltage source OFF M11 OFF VS1 1.5V 1MHz hold 1pF Device OFF 3 charged to ~VDD EES 247 Lecture 16: Data onverters- AD Design, Sampling 2010 Page 47 onstant V GS Sampler: F High VDD 3 1pF M8 3 previously charged to VDD M8 & M9 are on: 3 across G-S of M11 M9 VS1 1.5V 1MHz M11 hold M11 on with constant VGS = VDD Mission accomplished!? EES 247 Lecture 16: Data onverters- AD Design, Sampling 2010 Page 48

25 onstant V GS Sampling Input Switch V Gate hold Signal Input Signal EES 247 Lecture 16: Data onverters- AD Design, Sampling 2010 Page 49 onstant V GS Sampling? EES 247 Lecture 16: Data onverters- AD Design, Sampling 2010 Page 50

26 onstant V GS Sampling? During the time period: V in < V out V GS =constant=v DD Larger V GS -V th compared to no boost V GS =cte and not a function of input voltage Significant linearity improvement IR During the time period: V in >V out : V GS = V DD - IR Larger V GS -V th compared to no boost V GS is a function of IR and hence input voltage Linearity improvement not as pronounced as for V in < V out EES 247 Lecture 16: Data onverters- AD Design, Sampling 2010 Page 51 lock Multiplier M7 & M13 for reliability Remaining issues: -V GS constant only for V in <V out Boosted lock Sampling omplete ircuit -Nonlinearity due to Vth dependence of M11on bodysource voltage Switch Ref: A. Abo et al, A 1.5-V, 10-bit, 14.3-MS/s MOS Pipeline Analog-to-Digital onverter, JSS May 1999, pp EES 247 Lecture 16: Data onverters- AD Design, Sampling 2010 Page 52

27 Boosted lock Sampling Design onsideration hoice of value for 3: 3 too large large charging current large dynamic power dissipation VDD 3 M8 3 too small Vgate-Vs= VDD.3/(3+x) Loss of VGS due to low ratio of x/3 x includes GS of M11 plus all other parasitics caps. M9 x Vin M11 hold Ref: A. Abo et al, A 1.5-V, 10-bit, 14.3-MS/s MOS Pipeline Analog-to-Digital onverter, JSS May 1999, pp EES 247 Lecture 16: Data onverters- AD Design, Sampling 2010 Page 53 Advanced lock Boosting Technique Ref: M. Waltari et al., "A self-calibrated pipeline AD with 200MHz IFsampling frontend," ISS 2002, Dig. Tech. Papers, pp. 314 Sampling Switch Two floating voltages sources generated and connected to Gate and S & D EES 247 Lecture 16: Data onverters- AD Design, Sampling 2010 Page 54

28 Advanced lock Boosting Technique clk low Sampling Switch clk low apacitors 1a & 1b charged to VDD MS off Hold mode EES 247 Lecture 16: Data onverters- AD Design, Sampling 2010 Page 55 Advanced lock Boosting Technique clk high Sampling Switch clk high Top plate of 1a & 1b connected to gate of sampling switch Bottom plate of 1a connected to V IN Bottom plate of 1b connected to V OUT VGS & VGD of MS VDD & ac signal on G of MS average of V IN & V OUT EES 247 Lecture 16: Data onverters- AD Design, Sampling 2010 Page 56

29 Advanced lock Boosting Technique Ref: M. Waltari et al., "A self-calibrated pipeline AD with 200MHz IFsampling frontend," ISS 2002, Dig. Tech. Papers, pp. 314 Sampling Switch Gate tracks average of input and output, reduces effect of I R drop at high frequencies Bulk also tracks signal reduced body effect (technology used allows connecting bulk to S) Reported measured SFDR = 76.5dB at f in =200MHz EES 247 Lecture 16: Data onverters- AD Design, Sampling 2010 Page 57 onstant onductance Switch Ref: H. Pan et al., "A 3.3-V 12-b 50-MS/s A/D converter in 0.6um MOS with over 80-dB SFDR," IEEE J. Solid-State ircuits, pp , Dec EES 247 Lecture 16: Data onverters- AD Design, Sampling 2010 Page 58

30 onstant onductance Switch OFF Ref: H. Pan et al., "A 3.3-V 12-b 50-MS/s A/D converter in 0.6um MOS with over 80-dB SFDR," IEEE J. Solid-State ircuits, pp , Dec EES 247 Lecture 16: Data onverters- AD Design, Sampling 2010 Page 59 onstant onductance Switch M2 onstant current constant g ds ON M1 replica of M2 & same VGS as M2 M1 also constant g ds Note: Authors report requirement of 280MHz GBW for the opamp for 12bit 50Ms/s AD Also, opamp common-mode compliance for full input range required Ref: H. Pan et al., "A 3.3-V 12-b 50-MS/s A/D converter in 0.6um MOS with over 80-dB SFDR," IEEE J. Solid-State ircuits, pp , Dec EES 247 Lecture 16: Data onverters- AD Design, Sampling 2010 Page 60

31 Switch Off-Mode Feedthrough ancellation Ref: M. Waltari et al., "A self-calibrated pipeline AD with 200MHz IF-sampling frontend," ISS 2002, Dig. Techn. Papers, pp. 314 EES 247 Lecture 16: Data onverters- AD Design, Sampling 2010 Page 61 Practical Sampling Issues 1 v IN M1 v OUT Switch induced noise due to M1 finite channel resistance lock jitter Finite R sw limited bandwidth finite acquisition time R sw = f(v in ) distortion Switch charge injection & clock feedthrough EES 247 Lecture 16: Data onverters- AD Design, Sampling 2010 Page 62

32 Sampling Switch harge Injection & lock Feedthrough Switching from Track to Hold V G V H V i +V th V G V i V i M1 VO V L V O V i DV t s t off t First assume V i is a D voltage When switch turns off offset voltage induced on s Why? EES 247 Lecture 16: Data onverters- AD Design, Sampling 2010 Page 63 Sampling Switch harge Injection MOS xtor operating in triode region ross section view L D Distributed channel resistance & gate & junction capacitances G ov ov L S j sb B j db D HOLD hannel distributed R network formed between G,S, and D hannel to substrate junction capacitance distributed & voltage dependant Drain/Source junction capacitors to substrate voltage dependant Over-lap capacitance ov = L D xwx ox associated with G-S & G-D overlap EES 247 Lecture 16: Data onverters- AD Design, Sampling 2010 Page 64

33 Switch harge Injection Slow lock V H V i V G Device still conducting V i +V th V L t- t off t Slow clock clock fall time >> device speed During the period (t- to t off ) current in channel discharges channel charge into low impedance signal source Only source of error lock feedthrough from ov to s EES 247 Lecture 16: Data onverters- AD Design, Sampling 2010 Page 65 Switch lock Feedthrough Slow lock VG V G V H ov V i +V th D V i D ov V Vi Vth VL ov s ov V i V th V L s o i D s V L V O V i V V V V V V V V V 1 V V V V 1 V ov ov ov o i i th L i th L s s s o i os t- t off DV t t ov where ; V V V s ov os th L s EES 247 Lecture 16: Data onverters- AD Design, Sampling 2010 Page 66

34 Switch harge Injection & lock Feedthrough Slow lock- Example V i V G M1 10/0.18 VO s =1pF V G V H V i +V th V i ' 2 ov ox th L 0.1fF / 9 ff / V 0.4V V 0 ov 10x0.1fF /.1% s 1pF Allowing 1/ 2LSB AD resolution ~ 9bit V V V 0. 4mV ov os th L s V L V O V i t- t off DV t t EES 247 Lecture 16: Data onverters- AD Design, Sampling 2010 Page 67 Switch harge Injection & lock Feedthrough Fast lock Q ch V i V G nqch n+m=1 M1 VO mq ch s =1pF V G V H V i +V th V i V L V O V i DV t t off t Sudden gate voltage drop no gate voltage to establish current in channel channel charge has no choice but to escape out towards S & D EES 247 Lecture 16: Data onverters- AD Design, Sampling 2010 Page 68

35 Switch harge Injection & lock Feedthrough Fast lock lock Fall-Time << Device Speed: 1 Q DV V V ov ch o H L ov s 2 s 1 W L V V V 2 Vo Vi 1 Vos 1 WoxL where 2 s 1 WoxL VH Vth V V V 2 ov ox H i th VH VL ov s s ov os H L s s For simplicity it is assumed channel charge divided equally between S & D Source of error channel charge transfer + clock feedthrough via ov to s V H V i V G V L V O V i t off V i +V th DV t t EES 247 Lecture 16: Data onverters- AD Design, Sampling 2010 Page 69 Switch harge Injection & lock Feedthrough Fast lock- Example V i V G M1 10 /0.18 V H VO V i +V th V i s =1pF V G ff ff ov 0.1, ox 9, V 2 th 0.4V,VDD 1.8V, VL 0 WLox 10x0.18 x9 ff / 1/ 2 1.6% ~ 5 bit 1pF ov os H L s s s 2 1 WoxL VH Vth V V V 1.8mV 14.6mV 16.4mV 2 V L V O V i t off DV t t EES 247 Lecture 16: Data onverters- AD Design, Sampling 2010 Page 70

36 Switch harge Injection & lock Feedthrough Example-Summary 1.6% 16mV V OS.1% lock fall time 0.4mV lock fall time Error function of: lock fall time Input voltage level Source impedance Sampling capacitance size Switch size lock fall/rise should be controlled not to be faster (sharper) than necessary EES 247 Lecture 16: Data onverters- AD Design, Sampling 2010 Page 71 Switch harge Injection Error Reduction How do we reduce the error? Reduce switch size to reduce channel charge? 1Qch DVo 2s s Ts RON s ( note : k ) W ox VGS Vth 2 L onsider the figure of merit (FOM): W ox VGS Vth 1 L s FOM 2 DV W LV V V FOM L o s ox H i th 2 Reducing switch size increases increased distortion not a viable solution Small and small DV use minimum chanel length (mandated by technology) For a given technology x DV ~ constant EES 247 Lecture 16: Data onverters- AD Design, Sampling 2010 Page 72

37 Sampling Switch harge Injection & lock Feedthrough Summary Extra charge injected onto sampling switch device turn-off hannel charge injection lock feedthrough to s via ov Issues due to charge injection & clock feedthrough: D offset induced on hold Input dependant error voltage distortion Solutions: Slowing down clock edges as much as possible omplementary switch? Addition of dummy switches? Bottom-plate sampling? EES 247 Lecture 16: Data onverters- AD Design, Sampling 2010 Page 73

Summary of Last Lecture

Summary of Last Lecture EE47 Lecture 7 DAC Converters (continued) Dynamic element matching DAC reconstruction filter ADC Converters Sampling Sampling switch considerations Thermal noise due to switch resistance Sampling switch